US20160337229A1 - Network topology for a scalable multiprocessor system - Google Patents
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- US20160337229A1 US20160337229A1 US15/220,189 US201615220189A US2016337229A1 US 20160337229 A1 US20160337229 A1 US 20160337229A1 US 201615220189 A US201615220189 A US 201615220189A US 2016337229 A1 US2016337229 A1 US 2016337229A1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17306—Intercommunication techniques
- G06F15/17312—Routing techniques specific to parallel machines, e.g. wormhole, store and forward, shortest path problem congestion
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/14—Routing performance; Theoretical aspects
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
- G06F15/17343—Direct connection machines, e.g. completely connected computers, point to point communication networks wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17356—Indirect interconnection networks
- G06F15/17368—Indirect interconnection networks non hierarchical topologies
- G06F15/17381—Two dimensional, e.g. mesh, torus
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/01—Protocols
- H04L67/10—Protocols in which an application is distributed across nodes in the network
- H04L67/1001—Protocols in which an application is distributed across nodes in the network for accessing one among a plurality of replicated servers
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- H04L67/1002—
Abstract
Description
- The present application is a continuation and claims the priority benefit of U.S. patent application Ser. No. 13/873,058 filed Apr. 29, 2013, which is a continuation and claims the priority benefit of U.S. patent application Ser. No. 12/121,941 filed May 16, 2008, now U.S. Pat. No. 8,433,816, which is a continuation and claims the priority benefit of U.S. patent application Ser. No. 11/295,676 filed Dec. 6, 2005, which is a continuation and claims the priority benefit of U.S. patent application Ser. No. 09/408,972 filed Sep. 29, 1999, now U.S. Pat. No. 6,973,559, the disclosures of which are incorporated herein by reference.
- 1. Field of the Invention
- The present invention relates generally to the field of high-speed digital data processing systems, and more particularly, to interconnection topologies for interconnecting processing element nodes in multiprocessor computer systems.
- 2. Description of the Related Art
- Multiprocessor computer systems comprise a number of processing element nodes connected together by an interconnect network. Each processing element node includes at least one processing element. The interconnect network transmits packets of information or messages between processing element nodes. Multiprocessor computer systems having up to hundreds or thousands of processing element nodes are typically referred to as massively parallel processing (MPP) systems. In a typical multiprocessor MPP system, every processing element can directly address all of memory, including the memory of another (remote) processing element, without involving the processor at that processing element. Instead of treating processing element-to-remote-memory communications as an I/O operation, reads or writes to another processing element's memory are accomplished in the same manner as reads or writes to the local memory. In such multiprocessor MPP systems, the infrastructure that supports communications among the various processors greatly affects the performance of the MPP system because of the level of communications required among processors.
- Several different topologies have been proposed to interconnect the various processors in such MPP systems, such as rings, stars, meshes, hypercubes, and torus topologies. For example, in a conventional hypercube network, a plurality of microprocessors are arranged in an n-dimensional cube where the number of nodes k in the network is equal to 2′. In this network, each node is connected to each other node via a plurality of communications paths. The network diameter, the longest communications path from any one node on the network to any other node, is n-links.
- Regardless of the topology chosen, one disadvantage of current multiprocessor systems, and in particular MPP systems, is that in order to expand the system, a significant amount of reconfiguration is required. The reconfiguration often involves removing and replacing cables which is very time consuming. Also, as systems increase the number of processors, the number of physical connections required to support the system increases significantly which increases the complexity of the system.
- Therefore, it is desired that systems could be easily scaled to increase the number of processors with minimal disruption to the original system configuration.
- The present invention provides a system and method for interconnecting a plurality of processing element nodes within a scalable multiprocessor system. Each processing element node includes at least one processor and memory. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in a cluster. A first set of routers in the scalable interconnect network route messages between the plurality of processing element nodes. One or more metarouters in the scalable interconnect network route messages between the first set of routers so that each one of the routers in a first cluster is connected to all other clusters through one or more metarouters.
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FIG. 1 is block diagram of a multiprocessor computer system. -
FIG. 2 is a block diagram of one embodiment of the interface between a scalable interconnect network and four processing element nodes. -
FIG. 3 is a model of a two dimensional (2D) hypercube topology multiprocessor computer system. -
FIG. 4 is a model of a three dimensional (3D) hypercube topology multiprocessor computer system. -
FIG. 5 illustrates an example embodiment of a logical topology used for multiprocessor computer systems having 129 processors to 160 processors. -
FIG. 6 illustrates an example embodiment of a logical topology used for multiprocessor computer systems having 161 processors to 192 processors. -
FIG. 7 illustrates an example embodiment of a logical topology used for multiprocessor computer systems having 193 processors to 224 processors. -
FIG. 8 illustrates an example embodiment of a logical topology used for multiprocessor computer systems having 225 processors to 256 processors. -
FIG. 9 illustrates an example embodiment of a logical topology used for multiprocessor computer systems having up to 288 processors. -
FIG. 10 illustrates an example embodiment of a logical topology used for multiprocessor computer systems having up to 320 processors. -
FIG. 11 illustrates an example embodiment of a logical topology used for multiprocessor computer systems having up to 352 processors. -
FIG. 12 illustrates an example embodiment of a logical topology used for multiprocessor computer systems having up to 384 processors. -
FIG. 13 illustrates an example embodiment of a logical topology used for multiprocessor computer systems having up to 416 processors. -
FIG. 14 illustrates an example embodiment of a logical topology used for multiprocessor computer systems having up to 448 processors. -
FIG. 15 illustrates an example embodiment of a logical topology used for multiprocessor computer systems having up to 480 processors. -
FIG. 16 illustrates an example embodiment of a logical topology used for multiprocessor computer systems having up to 512 processors. -
FIG. 17 illustrates an example embodiment of a multiprocessor computer system having 512 processors. - In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
- System Overview
- A representative multiprocessor computer system according to the present invention is indicated generally at 20 in
FIG. 1 . As indicated inFIG. 1 ,multiprocessor computer system 20 includes up to n nodes, such as indicated by afirst node 22, asecond node 24, and annth node 26. The nodes are interconnected by ascalable interconnect network 28, which permitsmultiprocessor computer systems 20 to be scaled from desk side systems to very large supercomputer configurations. - As illustrated in detail for
first node 22, each node inmultiprocessor computer system 20 includes at least one processor, such as a first processor 30 and asecond processor 32 fornode 22. Aninterface circuit 34 interfaces withscalable interconnect network 28 and communicates with a memory anddirectory 36 and an input/output subsystem 38. - Although the
multiprocessor computer system 20 illustrated inFIG. 1 provides one example environment to implement the below-described network topology according to the present invention, the present invention is in no way limited to this particular application environment. In fact, many alternative environments using alternative node and interface circuit configurations can be utilized. To a large extent, the network topology according to the present invention, as implemented inscalable interconnect network 28, is independent of the complexity of the nodes, such asnodes -
FIG. 2 illustrates, in block diagram form, one embodiment of the interface between ascalable interconnect network 128 and fournodes scalable interconnect network 128 includes one or more routers, such as theexample router 150 shown inFIG. 2 .Router port 163 communicates with afirst node 122. As shown in the expanded view of thefirst node 122,router port 163 communicates with thefirst node 122 viainterface chip 134. In thefirst node 122,interface chip 134 communicates withprocessors router port 164 communicates with asecond node 123,router port 165 communicates with athird node 124, androuter port 166 communicates with afourth node 125.Router ports scalable interconnect network 128 as further described below. In the example embodiment illustrated inFIG. 2 , onerouter 150 communicates directly with up to sixteen processors and up to four other routers in thescalable interconnect network 128. - The
scalable interconnect network 128 of the present invention employs a first set of routers (such asrouter 150 ofFIG. 2 ) for routing messages between a plurality of processing element nodes (such asnodes FIG. 2 ). In one embodiment of the present invention, four of the eight ports of each one of the first set of routers are dedicated to connecting from the routers to four separate nodes, such as indicated inFIG. 2 . As further described below, the remaining ports are connected to the first set of routers for routing messages between the nodes and a second set of routers (referred to herein as “metarouters”) for routing messages between the first set of routers. In one embodiment, the metarouters shown inFIGS. 5-16 below are multiport routers having at least four ports. One of skill in the art will recognize that a single multiport router or any combination of multiport routers can be used in the configurations shown inFIGS. 5-16 . - As will be better understood by the following discussion, the topology of a scalable interconnect network according to the present invention, is easily scaleable, has increased resiliency and allows system upgrades/expansion to be performed with minimal disruption to the system.
- Example Network Topologies. A grouping of a plurality of processing element nodes, a plurality of physical interconnections (such as cables) for connecting the plurality of processing element nodes, and a first set of routers for routing messages between a plurality of processing element nodes is referred to herein as a “cluster.” In a multiprocessing system of the present invention, each cluster is connected to each one of the other clusters using one or more metarouters. Thus, each one of the clusters can communicate directly with another one of the clusters without having to communicate through a third cluster.
- In one embodiment, the processing element nodes and first set of routers form one or more two-dimensional hypercube systems. An example two dimensional (2D) hypercube topology multiprocessor computer system is shown in
FIG. 3 . InFIG. 3 , the fourrouters 150 are numbered 0 through 3 and are interconnected as a 2D hypercube. In one embodiment, the 2D hypercube comprises up to sixty-four processors because each of the four routers communicates with up to sixteen processors as shown inFIG. 2 . In the following detailed description clusters are configured in a two-dimensional hypercube for illustrative purposes only. The invention is not limited to arranging the first set of routers in a two-dimensional hypercube. Alternate embodiments in which the first set of routers are grouped in different topologies are contemplated as within the scope of the invention. - In one embodiment, a multiprocessor computer system is constructed with up to 128 processors without the use of metarouters. Such an embodiment is shown in
FIG. 4 . in which afirst cluster 400 and asecond cluster 402 are each arranged as two-dimensional hypercubes. As shown inFIG. 4 , the routers of afirst cluster 400 and asecond cluster 402 are interconnected to form a three-dimensional (3D) hypercube. The 3D hypercube is comprised of eightrouters 150 numbered 0 through 7. In an example embodiment, each one of the routers is an eight port router connected to four processing element nodes such as the router shown inFIG. 2 . For processing element nodes having four processors each, the 3D hypercube interconnects up to 128 processors. - Larger scale system configurations and the corresponding logical topologies for example systems having 128 or more processors are described below. The larger scale systems employ a second set of routers (referred to herein as “metarouters”) to interconnect the clusters. The novel network topologies of the present invention allow two clusters to communicate directly without having to route messages through a third cluster. Rather than routing messages through a third cluster, the routers in each cluster are connected to all other clusters through the metarouters.
- As shown in
FIGS. 5-16 , each router is either connected directly to a router of another cluster or is connected to a router of another cluster using one or more metarouters. In the example embodiments shown inFIGS. 5-16 , the connections from a single router in one cluster to routers in all other clusters are represented by particular line styles. The dashed lines inFIGS. 5-16 represent the connections from a first router in a first cluster to a single router in each one of the other clusters. The solid lines inFIGS. 5-16 represent the connections from a second router in the first cluster to a second router in each one of the other clusters. The dotted lines inFIGS. 5-16 represent the connections from a third router in the first cluster to a third router in each one of the other clusters. The dash/dot lines inFIGS. 5-16 represent the connection from a fourth router in a first cluster to a fourth router in each one of the other clusters. -
FIG. 5 illustrates an example embodiment of a logical topology used for systems having 129 processors to 160 processors. The logical topology comprises threeclusters metarouters metarouters first cluster 502 comprises sixty-four processors and thesecond cluster 504 also comprises sixty-four processors. The third cluster 506 can include any number of processors from one to thirty-two making a total of 129 to 160 processors in the multiprocessor computer system shown inFIG. 5 . - A router in each one of the three
clusters clusters metarouters first router 512 in afirst cluster 502 is connected to afirst router 520 in asecond cluster 504 through ametarouter 508. Thefirst router 512 in thefirst cluster 502 is also connected to afirst router 530 in a third cluster 506 through themetarouter 508. - Likewise, the solid lines represent the connection between a second router in the first cluster with a second router in each one of the other clusters. The
second router 514 in thefirst cluster 502 is connected to asecond router 522 in thesecond cluster 504 through ametarouter 510. Thesecond router 514 in thefirst cluster 502 is also connected to asecond router 532 in third cluster 506 throughmetarouter 510. - Similarly, the dotted lines represent the connection between a third router in the first cluster with a third router in each one of the other clusters and dash/dot lines in the diagrams represent the connection between a fourth router in the first cluster with a fourth router in each one of the other clusters. The
third router 516 and thefourth router 518 in thefirst cluster 502 are directly connected to athird router 524 and a fourth router 528 in thesecond cluster 504. The third cluster 506 lacks a third router and a fourth router in this configuration. Thus, as shown inFIG. 5 , each one of the routers in a cluster communicates with a router in each of the other clusters through either a direct connection or through one or more metarouters. This eliminates the dependency of one cluster to communicate with another cluster through a third cluster and thus creates a more resilient system. The topologies of the present invention allow clusters to communicate directly with each other without communicating through a third cluster. -
FIG. 6 illustrates an example embodiment of a logical topology used for multiprocessor computer systems having 161 processors to 192 processors. The logical topology comprises threeclusters metarouters metarouters FIG. 6 , afirst cluster 602 comprises sixty-four processors and asecond cluster 604 also comprises sixty-four processors. Athird cluster 606 can include any number of processors from thirty-three processors to sixty-four processors for a total of 161 to 192 processors in the multiprocessor computer system shown inFIG. 6 . - A router in each one of the three
clusters clusters metarouters first router 612 in afirst cluster 602 is connected to afirst router 620 in asecond cluster 604 through ametarouter 608. Thefirst router 612 in thefirst cluster 602 is also connected to afirst router 630 in athird cluster 606 through themetarouter 608. Connections between thefirst router 612 in thefirst cluster 602 and each one of the other clusters are represented inFIG. 6 with dashed lines. - Likewise, the
second router 614 in thefirst cluster 602 is connected to asecond router 622 in thesecond cluster 604 through ametarouter 610. Thesecond router 614 in thefirst cluster 602 is also connected to asecond router 632 inthird cluster 606 throughmetarouter 610. Connections between thesecond router 614 in thefirst cluster 602 and each one of the other clusters are represented inFIG. 6 with solid lines. Similarly, the dotted lines inFIG. 6 represent the connections between athird router 616 in thefirst cluster 602 and each one of the other clusters. Thethird router 616 in thefirst cluster 602 is connected to athird router 624 in thesecond cluster 604 throughmetarouter 609. Thethird router 616 in thefirst cluster 602 is also connected to athird router 634 in thethird cluster 606 throughmetarouter 609. Additionally, the dash/dot lines inFIG. 6 represent the connections between afourth router 618 in thefirst cluster 602 and each one of the other clusters. Thefourth router 618 in thefirst cluster 602 is connected to afourth router 628 in thesecond cluster 604 throughmetarouter 611. Thefourth router 618 in thefirst cluster 602 is also connected to afourth router 636 in thethird cluster 606 throughmetarouter 611. Thus, as shown inFIG. 6 , each one of the routers in a cluster communicates with a router in each of the other clusters through metarouters. -
FIG. 7 illustrates an example embodiment of a logical topology used for multiprocessor computer systems having 193 processors to 224 processors. The logical topology comprises fourclusters metarouters metarouters FIG. 7 , afirst cluster 702, asecond cluster 704, and athird cluster 706 each comprise sixty-four processors. Afourth cluster 707 includes any number of processors from one processor up to thirty-two processors for a total of 193 to 224 processors in the multiprocessor computer system shown inFIG. 7 . - A router in each one of the four
clusters clusters metarouters first router 712 in thefirst cluster 702 and each one of the other clusters are represented inFIG. 7 with dashed lines. Thefirst router 712 in afirst cluster 702 is connected to afirst router 720 in asecond cluster 704 through ametarouter 708. Thefirst router 712 in thefirst cluster 702 is also connected to afirst router 730 in athird cluster 706 through themetarouter 708. In addition, as shown inFIG. 7 , thefirst router 712 in thefirst cluster 702 is connected to afirst router 738 in afourth cluster 707 through themetarouter 708. - Connections between the
second router 714 in thefirst cluster 702 and each one of the other clusters are represented inFIG. 7 with solid lines. Thesecond router 714 in thefirst cluster 702 is connected to asecond router 722 in thesecond cluster 704 through ametarouter 710. Thesecond router 714 in thefirst cluster 702 is also connected to a second router 732 inthird cluster 706 throughmetarouter 710 Additionally, inFIG. 7 thesecond router 714 in thefirst cluster 702 is connected to asecond router 740 in afourth cluster 707 through themetarouter 708. - Similarly, the dotted lines in
FIG. 7 represent the connections between athird router 716 in thefirst cluster 702 and each one of the other clusters. Thethird router 716 in thefirst cluster 702 is connected to athird router 724 in thesecond cluster 704 throughmetarouter 709. Thethird router 716 in thefirst cluster 702 is also connected to athird router 734 in thethird cluster 706 throughmetarouter 709. Likewise, the dash/dot lines inFIG. 7 represent the connections between afourth router 718 in thefirst cluster 702 and each one of the other clusters. Thefourth router 710 in thefirst cluster 702 is connected to a fourth router 728 in thesecond cluster 704 throughmetarouter 711. Thefourth router 710 in thefirst cluster 702 is also connected to afourth router 736 in thethird cluster 706 throughmetarouter 711. - Thus, as shown in
FIG. 7 , each one of the routers in a cluster communicates with a router in each of the other clusters through metarouters. Furthermore, the 224 processor system shown inFIG. 7 is easily created by expanding the 192 processor system shown inFIG. 6 . First, the multiprocessor system ofFIG. 7 is formed by adding thefourth cluster 707. Second, the interconnections are added from themetarouter 708 to afirst router 738 in thefourth cluster 707. Third, the interconnections are added from themetarouter 710 to thesecond router 740 in afourth cluster 707. Thus, a 192 processor system of the present invention is expandable to a 224 processor system without having to recable the first, the second, and thethird clusters -
FIG. 8 illustrates an example embodiment of a logical topology used for multiprocessor computer systems having 225 processors to 256 processors. The logical topology comprises fourclusters metarouters FIG. 8 , afirst cluster 802, asecond cluster 804, and athird cluster 806 each contain sixty-four processors. In addition, thefourth cluster 807 can include from thirty-three processors up to sixty-four processors for a total of 225 to 256 processors in the multiprocessor computer system shown inFIG. 8 . - A router in each one of the four
clusters clusters metarouters first router 812 in thefirst cluster 802 and each one of the other clusters are represented inFIG. 8 with dashed lines. Thefirst router 812 in afirst cluster 802 is connected to afirst router 820 in asecond cluster 804 through ametarouter 808. Thefirst router 812 in thefirst cluster 802 is also connected to afirst router 830 in athird cluster 806 through themetarouter 808. Thefirst router 812 in thefirst cluster 802 is also connected to afirst router 838 in afourth cluster 807 through themetarouter 808. - Connections between the
second router 814 in thefirst cluster 802 and each one of the other clusters are represented inFIG. 8 with solid lines. Thesecond router 814 in thefirst cluster 802 is connected to asecond router 822 in thesecond cluster 804 through ametarouter 810. Thesecond router 814 in thefirst cluster 802 is also connected to a second router 832 inthird cluster 806 throughmetarouter 810, and thesecond router 814 in thefirst cluster 802 is connected to asecond router 840 in afourth cluster 807 through themetarouter 808. - Similarly, the dotted lines in
FIG. 8 represent the connections between athird router 816 in thefirst cluster 802 and each one of the other clusters. Thethird router 816 in thefirst cluster 802 is connected to athird router 824 in thesecond cluster 804 throughmetarouter 809. Thethird router 816 in thefirst cluster 802 is also connected to athird router 834 in thethird cluster 806 throughmetarouter 809. Additionally, the 224 processor system ofFIG. 7 is expanded inFIG. 8 by adding a processing element node and athird router 842 in thefourth cluster 807 and connecting thethird router 816 in thefirst cluster 802 to thethird router 842 in thefourth cluster 807 throughmetarouter 809. - Likewise, the dash/dot lines in
FIG. 8 represent the connections between afourth router 818 in thefirst cluster 802 and each one of the other clusters. Thefourth router 818 in thefirst cluster 802 is connected to afourth router 828 in thesecond cluster 804 throughmetarouter 811. Thefourth router 818 in thefirst cluster 802 is also connected to afourth router 836 in thethird cluster 806 throughmetarouter 811. Additionally, the 224 processor system ofFIG. 7 is further expanded inFIG. 8 by adding a processing element node and afourth router 844 and connecting thefourth router 818 in thefirst cluster 802 to thefourth router 844 in thefourth cluster 807 throughmetarouter 811. - Again, as shown in
FIG. 8 , each one of the routers in a cluster communicates with a router in each of the other clusters through metarouters. Furthermore, the 256 processor system shown inFIG. 8 is easily created by expanding the 224 processor system shown inFIG. 7 . Thus, a 224 processor system of the present invention is expandable to a 256 processor system merely by adding processing element nodes, interconnections, and routers to thefourth cluster 807. The expansion of the system does not require reconfiguration or recabling the first, the second, or thethird clusters FIG. 7 . -
FIGS. 9-16 illustrate example embodiments of multiprocessor systems having greater than 256 processors. The multiprocessor systems shown inFIGS. 9-16 are built by expanding the configuration shown inFIG. 8 comprising up to 256 processors. The 256 processor system shown inFIG. 8 has four clusters configured as 2D hypercubes and interconnected with metarouters. According to the present invention, multiprocessor systems having more than 256 processors are configured by adding clusters to the configuration shown inFIG. 8 and connecting each one of the clusters to the other clusters in the configuration by one or more metarouters. -
FIG. 9 illustrates an example embodiment of a logical topology used for multiprocessor computer systems having up to 288 processors. The 288 processor system shown inFIG. 9 is easily created by expanding the 256 processor system shown inFIG. 8 . Afifth cluster 962 is added to the multiprocessor system and twoadditional metarouters metarouter 950 to afirst router 970 in thefifth cluster 962, and to another metarouter. Interconnections are also added from themetarouter 952 to asecond router 972 in thefifth cluster 962, and to another metarouter. Thus, a 256 processor system of the present invention is easily expandable to a 288 processor system without having to reconfigure the original 256 processor system. -
FIG. 10 illustrates an example embodiment of a logical topology used for multiprocessor computer systems having up to 320 processors. The 320 processor system shown inFIG. 10 is easily created by expanding the 288 processor system shown inFIG. 9 . Asixth cluster 1064 is added to the multiprocessor system. Interconnections are added from themetarouter 1050 to afirst router 1078 in thesixth cluster 1064. Interconnections are also added from themetarouter 1052 to asecond router 1080 in thesixth cluster 1064. As shown inFIG. 10 , a 288 processor system of the present invention is easily expandable to a 320 processor system without having to reconfigure the original 288 processor system. -
FIG. 11 illustrates an example embodiment of a logical topology used for multiprocessor computer systems having up to 352 processors. The 352 processor system shown inFIG. 11 is easily created by expanding the 320 processor system shown inFIG. 10 . A third router 1174 (and a corresponding processor element node) and a fourth router 1176 (and a corresponding processor element node) are added to thefifth cluster 1162 of the multiprocessor system. Interconnections are added from the metarouter 1154 (which is also added to the multiprocessor system) to thethird router 1174 in thefifth cluster 1162. Interconnections are also added from the metarouter 1156 (which is also added to the system) to thefourth router 1176 in thefifth cluster 1162. Thenew metarouters 1154, 1156 are also interconnected to the previous metarouters. As shown inFIG. 11 , a 320 processor system of the present invention is easily expandable to a 352 processor system without having to reconfigure the original 320 processor system. -
FIG. 12 illustrates an example embodiment of a logical topology used for multiprocessor computer systems having up to 384 processors. The 384 processor system shown inFIG. 12 is easily created by expanding the 352 processor system shown inFIG. 11 . Athird router 1282 and afourth router 1284 and the corresponding processing element nodes are added to thesixth cluster 1264 of the multiprocessor system. Interconnections are added from themetarouter 1254 to thethird router 1282 in thesixth cluster 1264. Interconnections are also added from themetarouter 1256 to thefourth router 1284 in thesixth cluster 1264. As shown inFIG. 12 , a 352 processor system of the present invention is easily expandable to a 384 processor system without having to reconfigure the original 352 processor system. -
FIG. 13 illustrates an example embodiment of a logical topology used for multiprocessor computer systems having up to 416 processors. The 416 processor system shown inFIG. 13 is easily created by expanding the 384 processor system shown inFIG. 12 . Aseventh cluster 1386 having afirst router 1388 and asecond router 1389 are added to the multiprocessor system. Twometarouters metarouter 1355 to thefirst router 1388 in theseventh cluster 1386 and to one of the metarouters. Interconnections are also added from themetarouter 1357 to thesecond router 1389 in theseventh cluster 1386 and to one of the other metarouters. As shown inFIG. 13 , a 384 processor system of the present invention is easily expandable to a 416 processor system without having to reconfigure the original 384 processor system. -
FIG. 14 illustrates an example embodiment of a logical topology used for multiprocessor computer systems having up to 448 processors. The 448 processor system shown inFIG. 14 is easily created by expanding the 416 processor system shown inFIG. 13 . Aneighth cluster 1487 having a first router 1492 (and corresponding processing element node) and a second router 1493 (and corresponding processing element node) are added to the multiprocessor system. Interconnections are added from themetarouter 1455 to thefirst router 1492 in theeighth cluster 1487. Interconnections are also added from themetarouter 1457 to thesecond router 1493 in theeighth cluster 1487. As shown inFIG. 14 , a 416 processor system of the present invention is easily expandable to a 448 processor system without having to reconfigure the original 416 processor system. -
FIG. 15 illustrates an example embodiment of a logical topology used for multiprocessor computer systems having up to 480 processors. The 480 processor system shown inFIG. 15 is easily created by expanding the 448 processor system shown inFIG. 14 . Athird router 1590 and afourth router 1591 are added theseventh cluster 1586 of the multiprocessor system. Two metarouters are also added 1558, 1559 and interconnections are added from the twometarouters metarouter 1558 to thethird router 1590 in theseventh cluster 1586. Interconnections are also added from themetarouter 1559 to thefourth router 1591 in theseventh cluster 1586. As shown inFIG. 15 , a 448 processor system of the present invention is easily expandable to a 480 processor system without having to reconfigure the original 448 processor system. -
FIG. 16 illustrates an example embodiment of a logical topology used for multiprocessor computer systems having up to 512 processors. The 512 processor system shown inFIG. 16 is easily created by expanding the 480 processor system shown inFIG. 15 . A third router 1694 (and a corresponding processing element node) and a fourth router 1695 (and a corresponding processing element node) are added theeighth cluster 1687 of the multiprocessor system. Interconnections are added from themetarouter 1658 to thethird router 1694 in theeighth cluster 1687. Interconnections are also added from themetarouter 1659 to the fourth router 1695 in theeighth cluster 1687. As shown inFIG. 16 , a 480 processor system of the present invention is easily expandable to a 512 processor system without having to reconfigure the original 480 processor system. -
FIG. 17 illustrates an example embodiment of a system according toFIG. 16 . Each router (19, 27) is connected to four compute nodes (Cbricks). The remaining four ports are connected to other routers.Router 38 provides between routers,routers 27 andother routers 38. - The present invention, as described above, permits smaller systems to be expanded to larger systems with minimal disruption to the original system configuration. Although specific embodiments have been illustrated and described herein for purposes of description of the preferred embodiment, it will be appreciated by those of ordinary skill in the art that a wide variety of alternate and/or equivalent implementations calculated to achieve the same purposes may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. Those with skill in the mechanical, electro-mechanical, electrical, and computer arts will readily appreciate that the present invention may be implemented in a very wide variety of embodiments. This application is intended to cover any adaptations or variations of the preferred embodiments discussed herein. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/220,189 US20160337229A1 (en) | 1999-09-29 | 2016-07-26 | Network topology for a scalable multiprocessor system |
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/408,972 US6973559B1 (en) | 1999-09-29 | 1999-09-29 | Scalable hypercube multiprocessor network for massive parallel processing |
US11/295,676 US20060282648A1 (en) | 1999-09-29 | 2005-12-06 | Network topology for a scalable multiprocessor system |
US12/121,941 US8433816B2 (en) | 1999-09-29 | 2008-05-16 | Network topology for a scalable multiprocessor system |
US13/873,058 US9514092B2 (en) | 1999-09-29 | 2013-04-29 | Network topology for a scalable multiprocessor system |
US15/220,189 US20160337229A1 (en) | 1999-09-29 | 2016-07-26 | Network topology for a scalable multiprocessor system |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/873,058 Continuation US9514092B2 (en) | 1999-09-29 | 2013-04-29 | Network topology for a scalable multiprocessor system |
Publications (1)
Publication Number | Publication Date |
---|---|
US20160337229A1 true US20160337229A1 (en) | 2016-11-17 |
Family
ID=23618525
Family Applications (5)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/408,972 Expired - Lifetime US6973559B1 (en) | 1999-09-29 | 1999-09-29 | Scalable hypercube multiprocessor network for massive parallel processing |
US11/295,676 Abandoned US20060282648A1 (en) | 1999-09-29 | 2005-12-06 | Network topology for a scalable multiprocessor system |
US12/121,941 Expired - Fee Related US8433816B2 (en) | 1999-09-29 | 2008-05-16 | Network topology for a scalable multiprocessor system |
US13/873,058 Expired - Lifetime US9514092B2 (en) | 1999-09-29 | 2013-04-29 | Network topology for a scalable multiprocessor system |
US15/220,189 Abandoned US20160337229A1 (en) | 1999-09-29 | 2016-07-26 | Network topology for a scalable multiprocessor system |
Family Applications Before (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/408,972 Expired - Lifetime US6973559B1 (en) | 1999-09-29 | 1999-09-29 | Scalable hypercube multiprocessor network for massive parallel processing |
US11/295,676 Abandoned US20060282648A1 (en) | 1999-09-29 | 2005-12-06 | Network topology for a scalable multiprocessor system |
US12/121,941 Expired - Fee Related US8433816B2 (en) | 1999-09-29 | 2008-05-16 | Network topology for a scalable multiprocessor system |
US13/873,058 Expired - Lifetime US9514092B2 (en) | 1999-09-29 | 2013-04-29 | Network topology for a scalable multiprocessor system |
Country Status (5)
Country | Link |
---|---|
US (5) | US6973559B1 (en) |
EP (1) | EP1222557B1 (en) |
JP (1) | JP4480315B2 (en) |
DE (1) | DE60034470T2 (en) |
WO (1) | WO2001024029A2 (en) |
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US8307116B2 (en) * | 2009-06-19 | 2012-11-06 | Board Of Regents Of The University Of Texas System | Scalable bus-based on-chip interconnection networks |
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RU2635896C1 (en) * | 2016-07-07 | 2017-11-16 | Акционерное общество "Научно-исследовательский институт вычислительных комплексов им. М.А. Карцева" (АО "НИИВК им. М.А. Карцева") | High-performance computer platform based on processors with heterogeneous architecture |
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RU2708794C2 (en) * | 2018-05-21 | 2019-12-11 | Общество с ограниченной ответственностью "Центр инженерной физики при МГУ имени М.В. Ломоносова" | Computational module for multi-stream processing of digital data and processing method using said module |
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-
1999
- 1999-09-29 US US09/408,972 patent/US6973559B1/en not_active Expired - Lifetime
-
2000
- 2000-09-29 WO PCT/US2000/027024 patent/WO2001024029A2/en active IP Right Grant
- 2000-09-29 JP JP2001526728A patent/JP4480315B2/en not_active Expired - Fee Related
- 2000-09-29 EP EP00967199A patent/EP1222557B1/en not_active Expired - Lifetime
- 2000-09-29 DE DE60034470T patent/DE60034470T2/en not_active Expired - Fee Related
-
2005
- 2005-12-06 US US11/295,676 patent/US20060282648A1/en not_active Abandoned
-
2008
- 2008-05-16 US US12/121,941 patent/US8433816B2/en not_active Expired - Fee Related
-
2013
- 2013-04-29 US US13/873,058 patent/US9514092B2/en not_active Expired - Lifetime
-
2016
- 2016-07-26 US US15/220,189 patent/US20160337229A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US9514092B2 (en) | 2016-12-06 |
EP1222557A2 (en) | 2002-07-17 |
JP4480315B2 (en) | 2010-06-16 |
DE60034470T2 (en) | 2008-01-03 |
US20090113172A1 (en) | 2009-04-30 |
WO2001024029A3 (en) | 2001-08-30 |
US8433816B2 (en) | 2013-04-30 |
US6973559B1 (en) | 2005-12-06 |
US20060282648A1 (en) | 2006-12-14 |
EP1222557B1 (en) | 2007-04-18 |
DE60034470D1 (en) | 2007-05-31 |
US20130246653A1 (en) | 2013-09-19 |
JP2003510720A (en) | 2003-03-18 |
WO2001024029A2 (en) | 2001-04-05 |
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