US20170084513A1 - Semiconductor package - Google Patents

Semiconductor package Download PDF

Info

Publication number
US20170084513A1
US20170084513A1 US15/369,802 US201615369802A US2017084513A1 US 20170084513 A1 US20170084513 A1 US 20170084513A1 US 201615369802 A US201615369802 A US 201615369802A US 2017084513 A1 US2017084513 A1 US 2017084513A1
Authority
US
United States
Prior art keywords
chip
heat
thermal interface
semiconductor package
interface material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US15/369,802
Inventor
Shou-Chian Hsu
Hiroyuki Fujishima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Powertech Technology Inc
Original Assignee
Powertech Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powertech Technology Inc filed Critical Powertech Technology Inc
Priority to US15/369,802 priority Critical patent/US20170084513A1/en
Publication of US20170084513A1 publication Critical patent/US20170084513A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3675—Cooling facilitated by shape of device characterised by the shape of the housing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0236—Shape of the insulating layers therebetween
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Definitions

  • the invention relates to a package, and more particularly to a semiconductor package.
  • CMOS complementary metal-oxide-semiconductor
  • CMOS complementary metal-oxide-semiconductor
  • WLCSP Wafer-Level Chip-Size Package
  • Current WLCSP is generally manufactured by first performing a molding process so that a molding compound covers a backside of the chip and a side surface connected to the backside while exposing an active surface opposite to the backside. Then, a re-distribution layer is formed on the molding compound and the active surface of the chip, and the input/output terminals (I/O) on the active surface of the chip are electrically connected to the re-distribution layer.
  • the molding compound formed via the molding process is thicker, which is unfavorable to the miniaturization of the WLCSP.
  • the molding compound has a lower thermal conductivity coefficient and unfavorable heat-dissipating effects
  • heat generated by the chip is mostly transmitted outside via a re-distribution layer, which has limited heat-dissipating area or heat-dissipating path. Therefore, heat-dissipating efficiency is unfavorable. Under the circumstance that the heat cannot be rapidly transmitted to the outside and is accumulated inside the WLCSP, a warpage may easily occur in the WLCSP.
  • a semiconductor package is provided, which has preferable heat-dissipating efficiency.
  • a semiconductor package including an insulating layer, a chip, a thermal interface material, a heat-dissipating cover and a re-distribution layer.
  • the insulating layer has an accommodating opening.
  • the chip is disposed in the accommodating opening.
  • the chip has an active surface, a back surface opposite to the active surface and a side surface connected to the active surface and the back surface.
  • the thermal interface material is filled in the accommodating opening for at least encapsulating the side surface of the chip and exposing the active surface.
  • the re-distribution layer and the heat-dissipating cover are disposed on two sides of the insulating layer respectively, and the heat-dissipating cover is thermally coupled to the chip via the thermal interface material.
  • the re-distribution layer directly covers the insulating layer, the active surface of the chip and the thermal interface material, and the re-distribution layer is electrically connected to the chip.
  • the thermal interface material covers the back surface and the side surface of the chip.
  • the heat-dissipating cover contacts the insulating layer and the thermal interface material.
  • the thermal interface material exposes the back surface of the chip, and the heat-dissipating cover contacts the insulating layer, the thermal interface material and the back surface of the chip.
  • the insulating layer has a first surface and a second surface opposite to the first surface.
  • the heat-dissipating cover is disposed on the first surface.
  • the second surface and the active surface are coplanar to each other, and the re-distribution layer is disposed on the second surface and the active surface, and the back surface of the chip cuts with the first surface of the insulating layer.
  • the re-distribution layer includes at least one patterned conductive layer and at least one patterned dielectric layer that are stacked alternately, and the patterned conductive layer is electrically connected to the chip.
  • the semiconductor package further includes a plurality of solder balls.
  • the plurality of solder balls are electrically connected to the chip via the re-distribution layer.
  • the solder balls and the chips are located on two sides of the re-distribution layer respectively.
  • the back surface of the chip is covered by at least one part of the heat-dissipating cover.
  • the side surface is perpendicular to an interface between the heat-dissipating cover and the thermal interface material.
  • Another semiconductor package including an insulating layer, a chip, a thermal interface material, a heat-dissipating cover and a re-distribution layer.
  • the insulating layer has an accommodating opening.
  • the chip is disposed in the accommodating opening.
  • the chip has an active surface, a back surface opposite to the active surface and a side surface connected to the active surface and the back surface.
  • the thermal interface material is filled in the accommodating opening for at least encapsulating the side surface of the chip and exposing the active surface, wherein the insulating layer, the thermal interface material, and the active surfaces of the chips are coplanar to each other.
  • the re-distribution layer and the heat-dissipating cover are disposed on two sides of the insulating layer respectively, and the heat-dissipating cover is thermally coupled to the chip via the thermal interface material.
  • the re-distribution layer directly covers the insulating layer, the active surface of the chip and the thermal interface material, and the re-distribution layer is electrically connected to the chip
  • the semiconductor package of the invention at least covers the side surface of the chip located within the accommodating opening of the insulating layer via the thermal interface material and contacts the thermal interface material via the heat-dissipating cover, so as to have preferable heat-dissipating efficiency.
  • FIGS. 1A to 1G illustrate a manufacturing process of a semiconductor package according to an embodiment of the invention.
  • FIG. 2 is a schematic view of a semiconductor package according to another embodiment of the invention.
  • FIGS. 1A to 1G illustrate a manufacturing process of a semiconductor package according to an embodiment of the invention.
  • a carrier 10 is provided first, and a heat-dissipating material layer 110 is formed on the carrier 10 .
  • the carrier 10 may be a sheet formed by a rigid material or a flexible material, or a release film such as a thermal release film, a UV release film or other adequate films), but the invention does not limit on the material of the carrier 10 .
  • the heat-dissipating material layer 110 is, for example, temporarily secured on the carrier 10 by means of adhesion, so as to facilitate subsequent processes.
  • the heat-dissipating material layer 110 may be formed by aluminum, magnesium, copper, silver, gold or other metal or metal alloys having good thermal conductivity, or formed by graphite or other non-metal materials having good thermal conductivity.
  • an insulating material layer 120 is formed on the heat-dissipating material layer 110 , wherein a material of the insulating material layer 120 may be polyimide, epoxy, Si, SiO x or other adequate insulating materials.
  • the insulating material layer 120 may have a plurality of accommodating openings 121 to expose a portion of the heat-dissipating material layer 110 .
  • the manufacturing of the insulating material layer 120 may be performed by first forming a layer of the insulating material all over the heat-dissipating material layer 110 , and then forming the accommodating openings 121 on a specific area of the insulating material via processes such as exposure and development or laser opening, so as to obtain an patterned insulating material layer 120 .
  • the insulating material layer 120 having accommodating openings 121 may be formed directly on the heat-dissipating material layer 110 by means of ink-jet printing, screen printing, curtain printing, spray coating printing or dry film adhesion, etc.
  • the invention does not pose any limit on the manufacturing method for forming the insulating material layer 120 .
  • a plurality of chips 130 are disposed in the accommodating openings 121 respectively, and a thermal interface material 140 is filled in the accommodating openings 121 , wherein the thermal interface material 140 may be a thermal glue, a thermal grease, a thermal film or a thermal tape.
  • the invention does not limit on the order of placing the chips 130 in the accommodating openings 121 and filling the thermal interface material 140 in the accommodating openings 121 , so as to be applicable to manufacturing processes for the thermal interface material 140 to cover at least a side surface 133 of the chips 130 and expose active surfaces 131 of the chips 130 .
  • the thermal interface material 140 is filled in the accommodating openings 121 first, and then the chips 130 are placed in the accommodating openings 121 having the thermal interface material 140 while back surfaces 132 opposite to the active surfaces 131 of the chips 130 keep distances D from the heat-dissipating material layer 110 (that is, the back surfaces 132 of the chips 130 do not contact the heat-dissipating material layers 110 ).
  • the chips 130 are placed in the accommodating openings 121 first, so that the back surfaces 132 of the chips 130 contact the heat-dissipating material layer 110 .
  • the thermal interface material 140 is filled in the accommodating openings 121 along a gap between the side surfaces 133 of the chips 130 and inner walls of the accommodating openings 121 .
  • the chips 130 are placed in the accommodating openings 121 first, so that the back surfaces 132 of the chips 130 contact the heat-dissipating material layer 110 .
  • a thermal tape or a thermal film is pressed into the accommodating openings 121 by means of vacuum lamination. When needed, a portion of the thermal tape or the thermal film covering the active surfaces 131 of the chips 130 may be removed to expose the active surface 131 .
  • a re-distribution circuit structure 150 is formed on the insulating material layer 120 , the thermal interface material 140 and the active surface 131 of each chip 130 via re-distribution process, wherein the re-distribution circuit structure 150 includes a plurality of re-distribution layers 151 , and each of the re-distribution layers 151 is electrically connected to the corresponding chip 130 respectively.
  • each of the re-distribution layers 151 includes patterned conductive layers 151 a and 151 b and an patterned dielectric layer 151 c that are stacked alternately, wherein each of the re-distribution layers 151 connects to the active surface 131 of the corresponding chip 130 via the patterned conductive layer 151 a , and a portion of the patterned conductive pattern 151 a contacts the thermal interface material 140 .
  • the patterned dielectric layer 151 c exposes the patterned dielectric conductive layer 151 b .
  • the re-distribution layers are, for example, multi-layer circuit structures, and the number of circuit layers may vary according to actual needs.
  • a material of the solder balls B may include Tin, a Tin-Lead alloy or a Lead-free solder.
  • the carrier 10 is removed from the heat-dissipating material layer 110 , that is, the heat-dissipating material layer 110 and the carrier 10 are separated.
  • a singulation process is performed along a pre-determined cutting line L between any two adjacent chips 130 , so as to form a plurality of semiconductor packages 100 .
  • a cutting tool or a laser cuts along the pre-determined cutting line L that passes through the heat-dissipating material layer 110 , the insulating material layer 120 and the patterned dielectric layer 151 c of the re-distribution circuit structure 150 , and the primary principle is to avoid harming the solder balls B.
  • the manufacturing of the semiconductor package 100 has been substantially completed, wherein the cut heat-dissipating material layer 110 forms a heat-dissipating cover 110 a of the semiconductor package 100 , and the cut insulating material layer 120 forms an insulating layer 120 a of the semiconductor package 100 .
  • the patterned insulating material layer 120 (i.e. the insulating material layer 120 having the plurality of accommodating openings 121 ) is used to substitute for a frame used in conventional press molding processes. Therefore, part of the manufacturing processes and required assistive device in conventional semiconductor packaging are dispensed, which thereby helps reduce a package thickness of the semiconductor package 100 and a cost for manufacturing the same.
  • the semiconductor package 100 includes the heat-dissipating cover 110 a , the insulating layer 120 a , the chip 130 , the thermal interface material 140 and the re-distribution layer 151 .
  • the chip 130 is disposed within the accommodating opening 121 of the insulating layer 120 a .
  • the thermal interface material 140 is filled in the accommodating opening 121 for encapsulating the side surface 133 and the back surface 132 of the chip 130 and exposing the active surface 131 .
  • the re-distribution layer 151 and the heat-dissipating cover 110 a are disposed on two opposite sides of the insulating layer 120 a respectively.
  • the heat-dissipating cover 110 a contacts the insulating layer 120 a and the thermal interface material 140 without directly contacting the back surface 132 of the chip 130 , the heat-dissipating cover 110 a in this embodiment is, for example, thermally coupled to the chip 130 via the thermal interface material 140 .
  • the re-distribution layer 151 covers the active surface 131 and the thermal interface material 140 of the chip 130 , wherein the re-distribution layer 151 is, for example, connected to the active surface 131 of the chip 130 via the patterned conductive layer 151 a to be electrically connected to the chip 130 , and a portion of the patterned conductive layer 151 a contacts the thermal interface material 140 .
  • the solder balls B are respectively connected to the patterned conductive layers 151 b of the re-distribution layer 151 , so as to be electrically connected to the chip 130 .
  • the solder balls B and the chip 130 are disposed respectively on two opposite sides of the re-distribution layer 151 .
  • the back surface 132 and the side surface 133 of the chip 130 are covered by the thermal interface material 140 , and therefore the heat-dissipating area of the chip 130 is enhanced. Furthermore, the heat-dissipating cover 110 a is thermally coupled to the chip 130 via the thermal interface material 140 , and therefore heat generated during operation of the chip 130 is transmitted to the outside rapidly via the thermal interface material 150 and the heat-dissipating cover 110 a .
  • FIG. 2 is a schematic view of a semiconductor package according to another embodiment of the invention.
  • the semiconductor package 100 A in this embodiment is substantially similar to the semiconductor package 100 in the previous embodiment, and the primary difference therebetween lies in: the thermal interface material 140 in this embodiment exposes the back surface 132 of the chip 130 , and the heat-dissipating cover 110 a contacts the insulating layer 120 a , the thermal interface material 140 and the back surface 132 of the chip 130 .
  • the insulating layer 120 a has a first surface 121 a and a second surface 122 a opposite to the first surface 121 a , and the heat-dissipating cover 110 a is disposed on the first surface 121 a while the re-distribution layer 151 is disposed on the second surface 122 a .
  • the back surface 132 of the chip 130 for example, cuts with the first surface 121 a of the insulating layer 120 a.
  • the semiconductor package of the invention at least covers the side surface of the chip within the accommodating opening of the insulating layer via the thermal interface material and contacts the thermal interface material via the heat-dissipating cover, so that the heat-dissipating cover is thermally coupled to the chip via the thermal interface material.
  • the heat generated during operation of the chip is transmitted to the outside rapidly via the thermal interface material and the heat-dissipating cover.
  • heat generated in the re-distribution layer is also transmitted to the outside rapidly via the thermal interface material and the heat-dissipating cover or be transmitted to the outside via the solder balls. Accordingly, the semiconductor package of the invention has preferable heat-dissipating efficiency, and the warpage does not easily occur due to the heat.

Abstract

A semiconductor package including an insulating layer, a chip, a thermal interface material, a heat-dissipating cover and a re-distribution layer is provided. The insulating layer has an accommodating opening. The chip is disposed in the accommodating opening. The chip has an active surface, a back surface opposite to the active surface and a side surface connected to the active surface and the back surface. The thermal interface material is filled in the accommodating opening for at least encapsulating the side surface of the chip and exposing the active surface. The re-distribution layer and the heat-dissipating cover are disposed on two side of the insulating layer respectively. The heat-dissipating cover is thermally coupled to the chip through the thermal interface material. The re-distribution layer directly covers the insulating layer, the active surface of the chip and the thermal interface material, and the re-distribution layer is electrically connected to the chip.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application is a divisional application of and claims the priority benefit of U.S. application Ser. No. 14/794,834, filed on Jul. 9, 2015, now allowed. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
    • BACKGROUND
  • Field of the Invention
  • The invention relates to a package, and more particularly to a semiconductor package.
  • Description of Related Art
  • To satisfy the needs for electronic products to be slim and small, semiconductor packages serving as core elements of the electronic products also develop toward miniaturization. Recently in the industry, a miniature semiconductor package such as chip-size package (CSP) has been developed, which is characterized in that a size of the CSP is approximately a size of a chip thereof or slightly larger than the size of the chip thereof. On the other hand, in addition to the miniature size, the semiconductor packages also need to enhance integrity and an amount of input/output terminals (I/O) for electrical connection to external electronic devices such as a circuit board, so as to satisfy the needs for electronic products to have high performance and high processing speed. To be able to arrange more input/output terminals (I/O) on a limited area of an active surface of the chip, wafer-level semiconductor packages such as Wafer-Level Chip-Size Package (WLCSP) is emerged.
  • Current WLCSP is generally manufactured by first performing a molding process so that a molding compound covers a backside of the chip and a side surface connected to the backside while exposing an active surface opposite to the backside. Then, a re-distribution layer is formed on the molding compound and the active surface of the chip, and the input/output terminals (I/O) on the active surface of the chip are electrically connected to the re-distribution layer. Generally speaking, the molding compound formed via the molding process is thicker, which is unfavorable to the miniaturization of the WLCSP. In addition, since the molding compound has a lower thermal conductivity coefficient and unfavorable heat-dissipating effects, heat generated by the chip is mostly transmitted outside via a re-distribution layer, which has limited heat-dissipating area or heat-dissipating path. Therefore, heat-dissipating efficiency is unfavorable. Under the circumstance that the heat cannot be rapidly transmitted to the outside and is accumulated inside the WLCSP, a warpage may easily occur in the WLCSP.
    • SUMMARY OF THE INVENTION
  • A semiconductor package is provided, which has preferable heat-dissipating efficiency.
  • A semiconductor package is provided, including an insulating layer, a chip, a thermal interface material, a heat-dissipating cover and a re-distribution layer. The insulating layer has an accommodating opening. The chip is disposed in the accommodating opening. The chip has an active surface, a back surface opposite to the active surface and a side surface connected to the active surface and the back surface. The thermal interface material is filled in the accommodating opening for at least encapsulating the side surface of the chip and exposing the active surface. The re-distribution layer and the heat-dissipating cover are disposed on two sides of the insulating layer respectively, and the heat-dissipating cover is thermally coupled to the chip via the thermal interface material. The re-distribution layer directly covers the insulating layer, the active surface of the chip and the thermal interface material, and the re-distribution layer is electrically connected to the chip.
  • In an embodiment of the invention, the thermal interface material covers the back surface and the side surface of the chip.
  • In an embodiment of the invention, the heat-dissipating cover contacts the insulating layer and the thermal interface material.
  • In an embodiment of the invention, the thermal interface material exposes the back surface of the chip, and the heat-dissipating cover contacts the insulating layer, the thermal interface material and the back surface of the chip.
  • In an embodiment of the invention, the insulating layer has a first surface and a second surface opposite to the first surface. The heat-dissipating cover is disposed on the first surface. The second surface and the active surface are coplanar to each other, and the re-distribution layer is disposed on the second surface and the active surface, and the back surface of the chip cuts with the first surface of the insulating layer.
  • In an embodiment of the invention, the re-distribution layer includes at least one patterned conductive layer and at least one patterned dielectric layer that are stacked alternately, and the patterned conductive layer is electrically connected to the chip.
  • In an embodiment of the invention, the semiconductor package further includes a plurality of solder balls. The plurality of solder balls are electrically connected to the chip via the re-distribution layer.
  • In an embodiment of the invention, the solder balls and the chips are located on two sides of the re-distribution layer respectively.
  • In an embodiment of the invention, the back surface of the chip is covered by at least one part of the heat-dissipating cover.
  • an embodiment of the invention, the side surface is perpendicular to an interface between the heat-dissipating cover and the thermal interface material.
  • Another semiconductor package is provided, including an insulating layer, a chip, a thermal interface material, a heat-dissipating cover and a re-distribution layer. The insulating layer has an accommodating opening. The chip is disposed in the accommodating opening. The chip has an active surface, a back surface opposite to the active surface and a side surface connected to the active surface and the back surface. The thermal interface material is filled in the accommodating opening for at least encapsulating the side surface of the chip and exposing the active surface, wherein the insulating layer, the thermal interface material, and the active surfaces of the chips are coplanar to each other. The re-distribution layer and the heat-dissipating cover are disposed on two sides of the insulating layer respectively, and the heat-dissipating cover is thermally coupled to the chip via the thermal interface material. The re-distribution layer directly covers the insulating layer, the active surface of the chip and the thermal interface material, and the re-distribution layer is electrically connected to the chip
  • Based on the above, the semiconductor package of the invention at least covers the side surface of the chip located within the accommodating opening of the insulating layer via the thermal interface material and contacts the thermal interface material via the heat-dissipating cover, so as to have preferable heat-dissipating efficiency.
  • To make the above features and advantages of the present invention more comprehensible, several embodiments accompanied with drawings are described in detail as follows.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings are included to provide further understanding, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments and, together with the description, serve to explain the principles of the disclosure.
  • FIGS. 1A to 1G illustrate a manufacturing process of a semiconductor package according to an embodiment of the invention.
  • FIG. 2 is a schematic view of a semiconductor package according to another embodiment of the invention.
    •  DESCRIPTION OF EMBODIMENTS
  • FIGS. 1A to 1G illustrate a manufacturing process of a semiconductor package according to an embodiment of the invention. Referring to FIG. 1A, a carrier 10 is provided first, and a heat-dissipating material layer 110 is formed on the carrier 10. For instance, the carrier 10 may be a sheet formed by a rigid material or a flexible material, or a release film such as a thermal release film, a UV release film or other adequate films), but the invention does not limit on the material of the carrier 10. Herein, the heat-dissipating material layer 110 is, for example, temporarily secured on the carrier 10 by means of adhesion, so as to facilitate subsequent processes. In this embodiment, the heat-dissipating material layer 110 may be formed by aluminum, magnesium, copper, silver, gold or other metal or metal alloys having good thermal conductivity, or formed by graphite or other non-metal materials having good thermal conductivity.
  • Then, referring to FIG. 1B, an insulating material layer 120 is formed on the heat-dissipating material layer 110, wherein a material of the insulating material layer 120 may be polyimide, epoxy, Si, SiOx or other adequate insulating materials. Herein, the insulating material layer 120 may have a plurality of accommodating openings 121 to expose a portion of the heat-dissipating material layer 110. For instance, the manufacturing of the insulating material layer 120 may be performed by first forming a layer of the insulating material all over the heat-dissipating material layer 110, and then forming the accommodating openings 121 on a specific area of the insulating material via processes such as exposure and development or laser opening, so as to obtain an patterned insulating material layer 120. Alternatively, the insulating material layer 120 having accommodating openings 121 may be formed directly on the heat-dissipating material layer 110 by means of ink-jet printing, screen printing, curtain printing, spray coating printing or dry film adhesion, etc. However, the invention does not pose any limit on the manufacturing method for forming the insulating material layer 120.
  • Next, referring to FIG. 1C, a plurality of chips 130 are disposed in the accommodating openings 121 respectively, and a thermal interface material 140 is filled in the accommodating openings 121, wherein the thermal interface material 140 may be a thermal glue, a thermal grease, a thermal film or a thermal tape. It should be noted that the invention does not limit on the order of placing the chips 130 in the accommodating openings 121 and filling the thermal interface material 140 in the accommodating openings 121, so as to be applicable to manufacturing processes for the thermal interface material 140 to cover at least a side surface 133 of the chips 130 and expose active surfaces 131 of the chips 130.
  • In this embodiment, for example, the thermal interface material 140 is filled in the accommodating openings 121 first, and then the chips 130 are placed in the accommodating openings 121 having the thermal interface material 140 while back surfaces 132 opposite to the active surfaces 131 of the chips 130 keep distances D from the heat-dissipating material layer 110 (that is, the back surfaces 132 of the chips 130 do not contact the heat-dissipating material layers 110). In another embodiment, for example, the chips 130 are placed in the accommodating openings 121 first, so that the back surfaces 132 of the chips 130 contact the heat-dissipating material layer 110. Then, the thermal interface material 140 is filled in the accommodating openings 121 along a gap between the side surfaces 133 of the chips 130 and inner walls of the accommodating openings 121. In yet another embodiment, for example, the chips 130 are placed in the accommodating openings 121 first, so that the back surfaces 132 of the chips 130 contact the heat-dissipating material layer 110. Then, a thermal tape or a thermal film is pressed into the accommodating openings 121 by means of vacuum lamination. When needed, a portion of the thermal tape or the thermal film covering the active surfaces 131 of the chips 130 may be removed to expose the active surface 131.
  • Next, referring to FIG. 1D, a re-distribution circuit structure 150 is formed on the insulating material layer 120, the thermal interface material 140 and the active surface 131 of each chip 130 via re-distribution process, wherein the re-distribution circuit structure 150 includes a plurality of re-distribution layers 151, and each of the re-distribution layers 151 is electrically connected to the corresponding chip 130 respectively. More specifically, each of the re-distribution layers 151 includes patterned conductive layers 151 a and 151 b and an patterned dielectric layer 151 c that are stacked alternately, wherein each of the re-distribution layers 151 connects to the active surface 131 of the corresponding chip 130 via the patterned conductive layer 151 a, and a portion of the patterned conductive pattern 151 a contacts the thermal interface material 140. On the other hand, the patterned dielectric layer 151 c exposes the patterned dielectric conductive layer 151 b. It should be noted that the re-distribution layers are, for example, multi-layer circuit structures, and the number of circuit layers may vary according to actual needs.
  • Then, referring to FIG. 1E, balling and reflowing processes are performed to form a plurality of groups of solder balls B on the re-distribution layers 151, wherein each of the groups of solder balls B is connected to the corresponding patterned conductive layer 151 b in the re-distribution layers 151 respectively, so as to be electrically connected to the corresponding chip 130. In general, a material of the solder balls B may include Tin, a Tin-Lead alloy or a Lead-free solder. Next, referring to FIG. 1F, the carrier 10 is removed from the heat-dissipating material layer 110, that is, the heat-dissipating material layer 110 and the carrier 10 are separated.
  • Finally, referring to both FIGS. 1F and 1G, a singulation process is performed along a pre-determined cutting line L between any two adjacent chips 130, so as to form a plurality of semiconductor packages 100. For instance, a cutting tool or a laser cuts along the pre-determined cutting line L that passes through the heat-dissipating material layer 110, the insulating material layer 120 and the patterned dielectric layer 151 c of the re-distribution circuit structure 150, and the primary principle is to avoid harming the solder balls B. Now, the manufacturing of the semiconductor package 100 has been substantially completed, wherein the cut heat-dissipating material layer 110 forms a heat-dissipating cover 110 a of the semiconductor package 100, and the cut insulating material layer 120 forms an insulating layer 120 a of the semiconductor package 100.
  • During the manufacturing process of the semiconductor package 100, the patterned insulating material layer 120 (i.e. the insulating material layer 120 having the plurality of accommodating openings 121) is used to substitute for a frame used in conventional press molding processes. Therefore, part of the manufacturing processes and required assistive device in conventional semiconductor packaging are dispensed, which thereby helps reduce a package thickness of the semiconductor package 100 and a cost for manufacturing the same.
  • Referring to FIG. 1G, in this embodiment, the semiconductor package 100 includes the heat-dissipating cover 110 a, the insulating layer 120 a, the chip 130, the thermal interface material 140 and the re-distribution layer 151. The chip 130 is disposed within the accommodating opening 121 of the insulating layer 120 a. The thermal interface material 140 is filled in the accommodating opening 121 for encapsulating the side surface 133 and the back surface 132 of the chip 130 and exposing the active surface 131. The re-distribution layer 151 and the heat-dissipating cover 110 a are disposed on two opposite sides of the insulating layer 120 a respectively. Since the heat-dissipating cover 110 a contacts the insulating layer 120 a and the thermal interface material 140 without directly contacting the back surface 132 of the chip 130, the heat-dissipating cover 110 a in this embodiment is, for example, thermally coupled to the chip 130 via the thermal interface material 140.
  • On the other hand, the re-distribution layer 151 covers the active surface 131 and the thermal interface material 140 of the chip 130, wherein the re-distribution layer 151 is, for example, connected to the active surface 131 of the chip 130 via the patterned conductive layer 151 a to be electrically connected to the chip 130, and a portion of the patterned conductive layer 151 a contacts the thermal interface material 140. The solder balls B are respectively connected to the patterned conductive layers 151 b of the re-distribution layer 151, so as to be electrically connected to the chip 130. Herein, the solder balls B and the chip 130 are disposed respectively on two opposite sides of the re-distribution layer 151.
  • In this embodiment, the back surface 132 and the side surface 133 of the chip 130 are covered by the thermal interface material 140, and therefore the heat-dissipating area of the chip 130 is enhanced. Furthermore, the heat-dissipating cover 110 a is thermally coupled to the chip 130 via the thermal interface material 140, and therefore heat generated during operation of the chip 130 is transmitted to the outside rapidly via the thermal interface material 150 and the heat-dissipating cover 110 a. In addition, since the portion of the patterned conductive layer 151 a contacts the thermal interface material 140, heat generated in the re-distribution layer 151 is also transmitted to the outside rapidly via the thermal interface material 140 and the heat-dissipating cover 110 a or be transmitted to the outside via the solder balls B. Accordingly, a warpage does not easily occur in the semiconductor package 100 due to the heat accumulated therein.
  • Other embodiments are provided below for further illustration. It should be noted herein that the reference numerals and part of the contents in the previous embodiment are used in the following embodiments, in which identical reference numerals indicate identical or similar components, and repeated description of the same technical contents is omitted. For detailed description of the omitted parts, reference can be found in the previous embodiment, and no description will be repeated in the following embodiments.
  • FIG. 2 is a schematic view of a semiconductor package according to another embodiment of the invention. Referring to FIG. 2, the semiconductor package 100A in this embodiment is substantially similar to the semiconductor package 100 in the previous embodiment, and the primary difference therebetween lies in: the thermal interface material 140 in this embodiment exposes the back surface 132 of the chip 130, and the heat-dissipating cover 110 a contacts the insulating layer 120 a, the thermal interface material 140 and the back surface 132 of the chip 130. More particularly, the insulating layer 120 a has a first surface 121 a and a second surface 122 a opposite to the first surface 121 a, and the heat-dissipating cover 110 a is disposed on the first surface 121 a while the re-distribution layer 151 is disposed on the second surface 122 a. In addition, the back surface 132 of the chip 130, for example, cuts with the first surface 121 a of the insulating layer 120 a.
  • Based on the above, the semiconductor package of the invention at least covers the side surface of the chip within the accommodating opening of the insulating layer via the thermal interface material and contacts the thermal interface material via the heat-dissipating cover, so that the heat-dissipating cover is thermally coupled to the chip via the thermal interface material. Thereby, the heat generated during operation of the chip is transmitted to the outside rapidly via the thermal interface material and the heat-dissipating cover. In addition, since a portion of the patterned conductive layer contacts the thermal interface material, heat generated in the re-distribution layer is also transmitted to the outside rapidly via the thermal interface material and the heat-dissipating cover or be transmitted to the outside via the solder balls. Accordingly, the semiconductor package of the invention has preferable heat-dissipating efficiency, and the warpage does not easily occur due to the heat.
  • Although the invention has been described with reference to the above embodiments, it will be apparent to one of ordinary skill in the art that modifications to the described embodiments may be made without departing from the spirit of the invention. Accordingly, the scope of the invention will be defined by the attached claims and not by the above detailed descriptions.

Claims (20)

What is claimed is:
1. A semiconductor package, comprising:
an insulating layer, having an accommodating opening;
a chip, disposed in the accommodating opening, the chip having an active surface, a back surface opposite to the active surface and a side surface connected to the active surface and the back surface;
a thermal interface material, filled in the accommodating opening for at least encapsulating the side surface of the chip and exposing the active surface;
a heat-dissipating cover; and
a re-distribution layer, wherein the re-distribution layer and the heat-dissipating cover are disposed on two side of the insulating layer respectively, the heat-dissipating cover is thermally coupled to the chip through the thermal interface material, and the re-distribution layer directly covers the insulating layer, the active surface of the chip and the thermal interface material, and the re-distribution layer is electrically connected to the chip.
2. The semiconductor package according to claim 1, wherein the thermal interface material covers the back surface and the side surface of the chip.
3. The semiconductor package according to claim 2, wherein the heat-dissipating cover contacts the insulating layer and the thermal interface material.
4. The semiconductor package according to claim 1, wherein the thermal interface material exposes the back surface of the chip, and the heat-dissipating cover contacts the insulating layer, the thermal interface material and the back surface of the chip.
5. The semiconductor package according to claim 4, wherein the insulating layer has a first surface and a second surface opposite to the first surface, the heat-dissipating cover is disposed on the first surface, the second surface and the active surface are coplanar to each other, the re-distribution layer is disposed on the second surface and the active surface, and the back surface of the chip cuts with the first surface of the insulating layer.
6. The semiconductor package according to claim 1, wherein the re-distribution layer comprises at least one patterned conductive layer and at least one patterned dielectric layer that are stacked alternately, and the patterned conductive layer is electrically connected to the chip.
7. The semiconductor package according to claim 1, further comprising:
a plurality of solder balls, electrically connected to the chip via the re-distribution layer.
8. The semiconductor package according to claim 7, wherein the solder balls and the chips are located on two sides of the re-distribution layer respectively.
9. The semiconductor package according to claim 1, wherein the back surface of the chip is covered by at least one part of the heat-dissipating cover.
10. The semiconductor package according to claim 1, wherein the side surface is perpendicular to an interface between the heat-dissipating cover and the thermal interface material.
11. A semiconductor package, comprising:
an insulating layer, having an accommodating opening;
a chip, disposed in the accommodating opening, the chip having an active surface, a back surface opposite to the active surface and a side surface connected to the active surface and the back surface;
a thermal interface material, filled in the accommodating opening for at least encapsulating the side surface of the chip and exposing the active surface, wherein the insulating layer, the thermal interface material, and the active surfaces of the chips are coplanar to each other;
a heat-dissipating cover; and
a re-distribution layer, wherein the re-distribution layer and the heat-dissipating cover are disposed on two side of the insulating layer respectively, the heat-dissipating cover is thermally coupled to the chip through the thermal interface material, and the re-distribution layer directly covers the insulating layer, the active surface of the chip and the thermal interface material, and the re-distribution layer is electrically connected to the chip.
12. The semiconductor package according to claim 11, wherein the thermal interface material covers the back surface and the side surface of the chip.
13. The semiconductor package according to claim 12, wherein the heat-dissipating cover contacts the insulating layer and the thermal interface material.
14. The semiconductor package according to claim 11, wherein the thermal interface material exposes the back surface of the chip, and the heat-dissipating cover contacts the insulating layer, the thermal interface material and the back surface of the chip.
15. The semiconductor package according to claim 14, wherein the insulating layer has a first surface and a second surface opposite to the first surface, the heat-dissipating cover is disposed on the first surface, the second surface and the active surface are coplanar to each other, the re-distribution layer is disposed on the second surface and the active surface, and the back surface of the chip cuts with the first surface of the insulating layer.
16. The semiconductor package according to claim 11, wherein the re-distribution layer comprises at least one patterned conductive layer and at least one patterned dielectric layer that are stacked alternately, and the patterned conductive layer is electrically connected to the chip.
17. The semiconductor package according to claim 1, further comprising:
a plurality of solder balls, electrically connected to the chip via the re-distribution layer.
18. The semiconductor package according to claim 17, wherein the solder balls and the chips are located on two sides of the re-distribution layer respectively.
19. The semiconductor package according to claim 11, wherein the back surface of the chip is covered by at least one part of the heat-dissipating cover.
20. The semiconductor package according to claim 11, wherein the side surface is perpendicular to an interface between the heat-dissipating cover and the thermal interface material.
US15/369,802 2015-07-09 2016-12-05 Semiconductor package Abandoned US20170084513A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/369,802 US20170084513A1 (en) 2015-07-09 2016-12-05 Semiconductor package

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/794,834 US9553036B1 (en) 2015-07-09 2015-07-09 Semiconductor package and manufacturing method thereof
US15/369,802 US20170084513A1 (en) 2015-07-09 2016-12-05 Semiconductor package

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US14/794,834 Division US9553036B1 (en) 2015-07-09 2015-07-09 Semiconductor package and manufacturing method thereof

Publications (1)

Publication Number Publication Date
US20170084513A1 true US20170084513A1 (en) 2017-03-23

Family

ID=57731517

Family Applications (2)

Application Number Title Priority Date Filing Date
US14/794,834 Active US9553036B1 (en) 2015-07-09 2015-07-09 Semiconductor package and manufacturing method thereof
US15/369,802 Abandoned US20170084513A1 (en) 2015-07-09 2016-12-05 Semiconductor package

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US14/794,834 Active US9553036B1 (en) 2015-07-09 2015-07-09 Semiconductor package and manufacturing method thereof

Country Status (1)

Country Link
US (2) US9553036B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10354936B2 (en) * 2016-07-14 2019-07-16 Rohm Co., Ltd. Electronic component having a heat dissipation member formed on a sealing member

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113491007A (en) * 2019-03-11 2021-10-08 Hrl实验室有限责任公司 Method of protecting die during Metal Embedded Chip Assembly (MECA) processing
CN112582366A (en) * 2020-12-11 2021-03-30 矽磐微电子(重庆)有限公司 Semiconductor packaging structure and preparation method thereof

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5909056A (en) * 1997-06-03 1999-06-01 Lsi Logic Corporation High performance heat spreader for flip chip packages
US20090321118A1 (en) * 2008-06-25 2009-12-31 Samsung Electro-Mechanics Co., Ltd. Printed circuit board embedded chip and manufacturing method thereof
US20100112889A1 (en) * 2008-10-31 2010-05-06 Industrial Technology Research Institute Methods for forming gas barriers on elctronic devices
US20110156236A1 (en) * 2009-12-30 2011-06-30 Stmicroelectronics Asia Pacific Pte Ltd. Thermally enhanced expanded wafer level package ball grid array structure and method of making the same
US20120153445A1 (en) * 2010-12-15 2012-06-21 Samsung Electronics Co., Ltd. Hybrid substrates, semiconductor packages including the same and methods for fabricating semiconductor packages
US20140299980A1 (en) * 2013-04-05 2014-10-09 Samsung Electronics Co., Ltd. Semiconductor packages including a heat spreader and methods of forming the same
US20160218049A1 (en) * 2015-01-23 2016-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Method of Manufactures

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020070443A1 (en) * 2000-12-08 2002-06-13 Xiao-Chun Mu Microelectronic package having an integrated heat sink and build-up layers
US8003496B2 (en) * 2009-08-14 2011-08-23 Stats Chippac, Ltd. Semiconductor device and method of mounting semiconductor die to heat spreader on temporary carrier and forming polymer layer and conductive layer over the die
US8564114B1 (en) 2010-03-23 2013-10-22 Amkor Technology, Inc. Semiconductor package thermal tape window frame for heat sink attachment
US8779582B2 (en) 2010-10-20 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Compliant heat spreader for flip chip packaging having thermally-conductive element with different metal material areas
US9087701B2 (en) * 2011-04-30 2015-07-21 Stats Chippac, Ltd. Semiconductor device and method of embedding TSV semiconductor die within substrate for vertical interconnect in POP
US20120306067A1 (en) 2011-06-02 2012-12-06 Taiwan Semiconductor Manufacturing Company, Ltd. Thermally Enhanced Integrated Circuit Package
KR20140057982A (en) 2012-11-05 2014-05-14 삼성전자주식회사 Semiconductor package and method of manufacturing the semiconductor package

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5909056A (en) * 1997-06-03 1999-06-01 Lsi Logic Corporation High performance heat spreader for flip chip packages
US20090321118A1 (en) * 2008-06-25 2009-12-31 Samsung Electro-Mechanics Co., Ltd. Printed circuit board embedded chip and manufacturing method thereof
US20100112889A1 (en) * 2008-10-31 2010-05-06 Industrial Technology Research Institute Methods for forming gas barriers on elctronic devices
US20110156236A1 (en) * 2009-12-30 2011-06-30 Stmicroelectronics Asia Pacific Pte Ltd. Thermally enhanced expanded wafer level package ball grid array structure and method of making the same
US20120153445A1 (en) * 2010-12-15 2012-06-21 Samsung Electronics Co., Ltd. Hybrid substrates, semiconductor packages including the same and methods for fabricating semiconductor packages
US20140299980A1 (en) * 2013-04-05 2014-10-09 Samsung Electronics Co., Ltd. Semiconductor packages including a heat spreader and methods of forming the same
US20160218049A1 (en) * 2015-01-23 2016-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor Device and Method of Manufactures

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10354936B2 (en) * 2016-07-14 2019-07-16 Rohm Co., Ltd. Electronic component having a heat dissipation member formed on a sealing member

Also Published As

Publication number Publication date
US20170011983A1 (en) 2017-01-12
US9553036B1 (en) 2017-01-24

Similar Documents

Publication Publication Date Title
TWI355034B (en) Wafer level package structure and fabrication meth
US8354598B2 (en) Packaging substrate and fabrication method thereof
US9431325B2 (en) Semiconductor packaging structure
US7833881B2 (en) Methods for fabricating semiconductor components and packaged semiconductor components
US9040361B2 (en) Chip scale package with electronic component received in encapsulant, and fabrication method thereof
US9666536B2 (en) Package structure and fabrication method thereof
US9748162B2 (en) Chip to wafer package with top electrodes and method of forming
US8446000B2 (en) Package structure and package process
US8222080B2 (en) Fabrication method of package structure
JP5615936B2 (en) Panel-based leadframe packaging method and apparatus
JP4103342B2 (en) Manufacturing method of semiconductor device
US20170084513A1 (en) Semiconductor package
US10461002B2 (en) Fabrication method of electronic module
WO2017114353A1 (en) Image sensing chip packaging structure and packaging method therefor
US20170207156A1 (en) Substrate structure
US20080135939A1 (en) Fabrication method of semiconductor package and structure thereof
US9196553B2 (en) Semiconductor package structure and manufacturing method thereof
TWI553798B (en) Semiconductor package and manufacturing method thereof
KR100941984B1 (en) Packaging method of wafer
US8691630B2 (en) Semiconductor package structure and manufacturing method thereof
US10950535B2 (en) Package structure and method of manufacturing the same
US20060105502A1 (en) Assembly process
TWI596678B (en) Semiconductor package structure and manufacturing method thereof
TWI600096B (en) Circuit component packaging method and its products
TW202123349A (en) Package structure and manufacturing method thereof

Legal Events

Date Code Title Description
STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION