US3271286A - Selective removal of material using cathodic sputtering - Google Patents

Selective removal of material using cathodic sputtering Download PDF

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US3271286A
US3271286A US347173A US34717364A US3271286A US 3271286 A US3271286 A US 3271286A US 347173 A US347173 A US 347173A US 34717364 A US34717364 A US 34717364A US 3271286 A US3271286 A US 3271286A
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United States
Prior art keywords
cathode
workpiece
glow discharge
sputtering
selective removal
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US347173A
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Marthin P Lepselter
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AT&T Corp
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Bell Telephone Laboratories Inc
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Priority to NL134170D priority Critical patent/NL134170C/xx
Priority to JP7080263A priority patent/JPS4316163B1/ja
Application filed by Bell Telephone Laboratories Inc filed Critical Bell Telephone Laboratories Inc
Priority to US347173A priority patent/US3271286A/en
Priority to US388039A priority patent/US3335338A/en
Priority to GB41932/64A priority patent/GB1082317A/en
Priority to GB8614/67A priority patent/GB1082319A/en
Priority to IL22370A priority patent/IL22370A/en
Priority to IL22419A priority patent/IL22419A/en
Priority to NL6413364A priority patent/NL6413364A/xx
Priority to IL22465A priority patent/IL22465A/en
Priority to DEW38002A priority patent/DE1282196B/en
Priority to DE1639051A priority patent/DE1639051C2/en
Priority to DEW38017A priority patent/DE1266406B/en
Priority to CH1535264A priority patent/CH427044A/en
Priority to NL6414107A priority patent/NL6414107A/xx
Priority to DE1964W0038104 priority patent/DE1515321A1/en
Priority to CH1604364A priority patent/CH426042A/en
Priority to NL6414441A priority patent/NL6414441A/xx
Priority to BE657021A priority patent/BE657021A/xx
Priority to BE657023A priority patent/BE657023A/xx
Priority to BE657022A priority patent/BE657022A/xx
Priority to FR998732A priority patent/FR1417621A/en
Priority to SE15227/64A priority patent/SE325334B/xx
Priority to FR998912A priority patent/FR1417695A/en
Priority to FR999073A priority patent/FR1417760A/en
Priority to CH1653864A priority patent/CH444969A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/34—Gas-filled discharge tubes operating with cathodic sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/764—Air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
    • H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
    • H01L27/0652—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
    • H01L27/0658—Vertical bipolar transistor in combination with resistors or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • C—CHEMISTRY; METALLURGY
    • C10—PETROLEUM, GAS OR COKE INDUSTRIES; TECHNICAL GASES CONTAINING CARBON MONOXIDE; FUELS; LUBRICANTS; PEAT
    • C10M—LUBRICATING COMPOSITIONS; USE OF CHEMICAL SUBSTANCES EITHER ALONE OR AS LUBRICATING INGREDIENTS IN A LUBRICATING COMPOSITION
    • C10M2201/00—Inorganic compounds or elements as ingredients in lubricant compositions
    • C10M2201/02—Water
    • C—CHEMISTRY; METALLURGY
    • C10—PETROLEUM, GAS OR COKE INDUSTRIES; TECHNICAL GASES CONTAINING CARBON MONOXIDE; FUELS; LUBRICANTS; PEAT
    • C10M—LUBRICATING COMPOSITIONS; USE OF CHEMICAL SUBSTANCES EITHER ALONE OR AS LUBRICATING INGREDIENTS IN A LUBRICATING COMPOSITION
    • C10M2219/00—Organic non-macromolecular compounds containing sulfur, selenium or tellurium as ingredients in lubricant compositions
    • C10M2219/10—Heterocyclic compounds containing sulfur, selenium or tellurium compounds in the ring
    • C—CHEMISTRY; METALLURGY
    • C10—PETROLEUM, GAS OR COKE INDUSTRIES; TECHNICAL GASES CONTAINING CARBON MONOXIDE; FUELS; LUBRICANTS; PEAT
    • C10M—LUBRICATING COMPOSITIONS; USE OF CHEMICAL SUBSTANCES EITHER ALONE OR AS LUBRICATING INGREDIENTS IN A LUBRICATING COMPOSITION
    • C10M2219/00—Organic non-macromolecular compounds containing sulfur, selenium or tellurium as ingredients in lubricant compositions
    • C10M2219/10—Heterocyclic compounds containing sulfur, selenium or tellurium compounds in the ring
    • C10M2219/102—Heterocyclic compounds containing sulfur, selenium or tellurium compounds in the ring containing sulfur and carbon only in the ring
    • C—CHEMISTRY; METALLURGY
    • C10—PETROLEUM, GAS OR COKE INDUSTRIES; TECHNICAL GASES CONTAINING CARBON MONOXIDE; FUELS; LUBRICANTS; PEAT
    • C10M—LUBRICATING COMPOSITIONS; USE OF CHEMICAL SUBSTANCES EITHER ALONE OR AS LUBRICATING INGREDIENTS IN A LUBRICATING COMPOSITION
    • C10M2219/00—Organic non-macromolecular compounds containing sulfur, selenium or tellurium as ingredients in lubricant compositions
    • C10M2219/10—Heterocyclic compounds containing sulfur, selenium or tellurium compounds in the ring
    • C10M2219/104—Heterocyclic compounds containing sulfur, selenium or tellurium compounds in the ring containing sulfur and carbon with nitrogen or oxygen in the ring
    • C—CHEMISTRY; METALLURGY
    • C10—PETROLEUM, GAS OR COKE INDUSTRIES; TECHNICAL GASES CONTAINING CARBON MONOXIDE; FUELS; LUBRICANTS; PEAT
    • C10M—LUBRICATING COMPOSITIONS; USE OF CHEMICAL SUBSTANCES EITHER ALONE OR AS LUBRICATING INGREDIENTS IN A LUBRICATING COMPOSITION
    • C10M2219/00—Organic non-macromolecular compounds containing sulfur, selenium or tellurium as ingredients in lubricant compositions
    • C10M2219/10—Heterocyclic compounds containing sulfur, selenium or tellurium compounds in the ring
    • C10M2219/104—Heterocyclic compounds containing sulfur, selenium or tellurium compounds in the ring containing sulfur and carbon with nitrogen or oxygen in the ring
    • C10M2219/106—Thiadiazoles
    • C—CHEMISTRY; METALLURGY
    • C10—PETROLEUM, GAS OR COKE INDUSTRIES; TECHNICAL GASES CONTAINING CARBON MONOXIDE; FUELS; LUBRICANTS; PEAT
    • C10N—INDEXING SCHEME ASSOCIATED WITH SUBCLASS C10M RELATING TO LUBRICATING COMPOSITIONS
    • C10N2040/00—Specified use or application for which the lubricating composition is intended
    • C10N2040/20—Metal working
    • C10N2040/22—Metal working with essential removal of material, e.g. cutting, grinding or drilling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/158—Sputtering
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/169—Vacuum deposition, e.g. including molecular beam epitaxy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths

Definitions

  • This invention relates to a method for selective removal of material from a workpiece by cathodic sputtering.
  • the method of this invention is useful for selectively removing material from a workpiece which cannot be subjected to the high potentials usually applied to the cathode member in the sputtering process.
  • the surfaces of materials may be cleaned or, in effect, etched by means of the sputtering process inasmuch as the cathode member itself is eroded by the bombardment which is basic to sputtering. It is apparent that a form of cleaning occurs as a consequence of the removal of surface layers.
  • the application of the cathode sputtering technique to remove layers from the surface of semiconductor bodies using potentials of the order of three to ten kilovolts across the cathode member is likely to cause permanent damage to the semiconductor body. This damage is particularly significant in the case of oxide-protected semiconductor bodies inasmuch as high electric fields cause permanent breakdown of the dielectric coatings.
  • an object of this invention is an arrangement for selectively removing material from the surface of a workpiece without directly applying high voltages across the workpiece.
  • an object of the invention is a backsputtering technique for effecting selective removal of portions of surface coatings on a semiconductor surface which includes dielectric oxide films.
  • the workpiece is separated from the cathode member by an insulating layer and the cathode is so shielded as to result in the formation of a glow dischage region around the periphery of the semiconductor workpiece.
  • the glow discharge region may be in the form of an annular ring or a rectilinear loop or annulus. This glow discharge region tends to spread somewhat with distance away from the cathode surface and, accordingly, tends to fill up some of the central volume directly over the workpiece.
  • the result of the formation of a cathode glow discharge in this pattern is to cause the gas ions, which are produced within the vacuum chamber of the sputtering apparatus, to move into the glow discharge region, gain energy and move out by the collision process to the space above the workpiece, and thence by further collision with other ions to impact substantially normally upon the surface of the workpiece. As is known, it is this ion impact which apparently products the sputtering action and material removal from the impacted surface. Thus, the semiconductor workpiece surface is bombarded Without applying directly across the semiconductor member the high voltage field which exists across the cathode member for producing the glow discharge region.
  • the invention is applicable to any differentially coated surface.
  • a surface which either has layers of differing thickness of the same material over different portions of the surface or in which different portions of the surface have coatings of different materials each having different sputtering efficiencies.
  • the material will be removed by sputtering to a substantially equal depth over the entire surface but will, of course, disappear completely from the more thinly coated areas first.
  • one material which sputters less efiiciently, and thus more slowly, than the others may constitute a mask to preserve portions underlying the mask while other portions are eroded and removed.
  • FIG. 1 shows in schematic form apparatus suitable for the practice of the invention
  • FIG. 2 is a plan view of the cathode member, the workpiece and the interposed insulating and shielding member,
  • FIG. 3 is a schematic representation of a portion of the apparatus depicting outlines in cross section of the glow discharge region in accordance with this invention.
  • FIG. 4 is a partial cross section of the semiconductor workpiece, the underlying portion of the insulating member and a portion of the supporting cathode member.
  • FIG. 1 there is shown in schematic form a vacuum enclosure 10 represented by the broken line 11.
  • anode member 12 Within the chamber and forming the base thereof is an anode member 12 which is held at ground potential. Shieldingly supported within the enclosure is a cathode member 13 to which a D.-C. supply is connected for applying relatively high negative potentials of the order of from three to ten kil-ovolts.
  • connections 14 for evacuating the chamber by conventional means such as diffusion pumps, and an inlet connection 15 with suitable stop valves 16 and 17.
  • the main supply line may be connected to a source of argon gas and the auxiliary line controlled by stop valve 17 to an oxygen supply for providing protective oxide coatings, as will be explained more fully hereinafter.
  • centrally placed on the cathode 13 is a similarly shaped ceramic member 18, and centrally mounted on ceramic member 18 is a semiconductor workpiece 19.
  • a pattern of deposited metallic electrodes in the form of stripes 20 are shown on the surface of the semiconductor workpiece. This pattern is primarily for exemplary purposes, and it will be understood that a variety of metal patterns may be used with this invention.
  • the relationship of these stripes 20 to the other parts of the device structure are illustrated in more detail in the partial cross section shown in FIG. 4.
  • the semiconductor workpiece portion 41 contains a series of three conductivity type regions making, for example, a transist-or.
  • a base region 44 defined by the pn junction 45 and an emitter region 46 defined by the second dilfused pn junction 47.
  • a layer 48 of silicon oxide On the surface of the silicon slice is a layer 48 of silicon oxide through which openings 61 and 62 have been made to expose surface portions of the base and emitter regions 44 and 46, respectively.
  • Ohmic contact is made initially to the silicon by depositing platinum over the entire oxide layer and heating the material to about 600 degrees centigrade. As disclosed in the aforementioned application of Lepselter, this causes a solid phase reaction akin to alloying between the platinum and the silicon. The platinum on the oxide surface, which is uncombined, then is readily removed by treating the surface with aqua regia. Solutions stronger than the usual three parts hydrochloric acid to one part nitric acid may be used to hasten the speed of platinum removal. This technique has the advantage I of leaving the alloyed platinum unaffected.
  • a layer 49 of titanium is deposited so as to overlie the oxide layer 48 and to make contact to the alloyed surface regions.
  • a second layer 50 of platinum is deposited on top of the titanium layer.
  • a thin layer of aluminum is deposited on top of the platinum layer.
  • the first and second metal layers namely titanium and platinum, must be removed from the workpiece surface except where these layers underlie the aluminum stripe electrodes 5-1 and 52.
  • this removal is conveniently done by the process of backsputtering. This technique is particularly valuable where the spacing between the electrodes 51 and 52 is in the order of microns.
  • the method of the invention requires an aluminum cathode number 43 upon which the semiconductor workpiece is mounted using an intermediate ceramic insulator 42.
  • cathodic sputtering The conditions employed in cathodic sputtering are known (see Vacuum Deposition of Thin Films, L. Holland, I. Wiley & Sons, Inc., New York, 1956). In this process a known reactive gas such as, for example, hydrogen or any of the members of the rare gas family such as helium, argon or neon is introduced into the chamber.
  • a known reactive gas such as, for example, hydrogen or any of the members of the rare gas family such as helium, argon or neon is introduced into the chamber.
  • the cathode sputtering system may be operated statically by providing a fixed pressure of gas in the system, or dynamically such that a fixed gas pressure is maintained with a constant flow of gas through the system.
  • the apparatus of FIG. 1 is subjected to a pressure of approximately ten microns of argon gas, and with the anode 12 at ground potential a negative voltage of five kilovolts is applied to the cathode.
  • a glow discharge region having a cross section substantially as depicted by the broken outlines 31 is produced around the periphery of the ceramic member 18.
  • This glow discharge region is annular in form and surrounds the workpiece on all sides, and extends, to some extent, over the space above the workpiece 19.
  • This glow discharge region 31 represents primarily the cathode discharge region and is the source of energy for particles passing through or located within the region.
  • argon gas ions are produced Within the vacuum chamber.
  • the effectiveness of the arrangement described herein for back-sputtering material from a semiconductor surface on which a protective oxide coating has been placed will be recognized from the effect produced if the high cathode potential is applied across the workpiece itself. If, for example, the silicon oxide coating is about 5000 angstroms thick and the applied voltage is five -kilovolts, both of which are typical values, than the field applied to the dielectric oxide is about 10 volts per centimeter. This assumes that, as is the fact, most of the voltage drop occurs across the oxide layer.
  • oxide coatings may be produced on the semiconductor workpiece surface at any desired stage in the fabrication process by admitting controlled amounts of oxygen to the inlet lines using stop valve 17 as noted hereinbefore.
  • oxide coatings of aluminum for example, where the cathode member is aluminum may be deposited on the semiconductor member.
  • the devices disclosed in accordance with this invention are not provided with the overlay structure of metal and oxide layers disclosed in the aforementioned Lepselter applicaton, the devices herein have extremely good longterm stability which seems to arise simply as a consequence of the oxide coating having once been covered with metal.
  • devices of the type disclosed herein where the oxide coating covers p-type conductivity material and where the two layers of metal have been deposited on, and then removed from the oxide surface there appears to be very complete resistance to the formation of surface channels in this material which generally rendered such devices unusable.
  • cathode configurations may be employed, even omitting the ceramic spacing member so long as the workpiece is electrically insulated from the cathode and the glow discharge region produced is peripherally disposed and out of contact with the workpiece.
  • a method for the selective removal of material from the surface of a substrate having a dielectric coating thereon comprising effecting a glow discharge in a low pressure gaseous ambient between an anode and a cath ode whereby an ionized gaseous plasma is formed in said glow discharge, electrically isolating an area of the surface of said cathode facing said anode larger than the References Cited by the Examiner UNITED STATES PATENTS 2,103,623 12/1937 Kott 204-192 2,702,274 2/1955 Law 204-192 2,848,542 7/ 195 8 Callahan 204-298 JOHN H. MACK, Primary Examiner.

Description

Sept. 6, 1966 M. P. LEPSELTER 3, 7 8
SELECTIVE REMOVAL OF MATERIAL USING CATHODIC SPUTTERING Filed Feb. 25, 1964 2 Sheets-Sheet 1 APGON MINIMUM uunnnnnu [/3 nuuuuuun -T uuunun 4 //\/l/E/V7OP By M. F. LEPSEL TER A T TORNEV P 6, 1966 M. P. LEPSELTER 3,271,286
SELECTIVE REMOVAL OF MATERIAL USING CATHODIC SPUTTERING Filed Feb. 25, 1964 2 Sheets-Sheet 2 O O /32 3 i I United States Patent 3,271,286 SELECTIVE REMOVAL 6F MATERHAL USING CATHODIC SPUTTERlNG Martin P. Lepselter, Franklin Park, N.J., assignor to Bell Telephone Laboratories, Incorporated, New York,
N.Y., a corporation of New York Filed Feb. 25, 1964, Ser. No. 347,173 2 Claims. (Cl. 204192) This application is a continuation-in-part of my application Serial No. 331,168, filed December 17, 1963, wherein a technique is disclosed for the selective removal of material from the surface of a semiconductive member by what has been termed back-sputtering.
This invention relates to a method for selective removal of material from a workpiece by cathodic sputtering. In particular, the method of this invention is useful for selectively removing material from a workpiece which cannot be subjected to the high potentials usually applied to the cathode member in the sputtering process.
In connection with the cathode sputtering process, it it known that the surfaces of materials may be cleaned or, in effect, etched by means of the sputtering process inasmuch as the cathode member itself is eroded by the bombardment which is basic to sputtering. It is apparent that a form of cleaning occurs as a consequence of the removal of surface layers. However, the application of the cathode sputtering technique to remove layers from the surface of semiconductor bodies using potentials of the order of three to ten kilovolts across the cathode member is likely to cause permanent damage to the semiconductor body. This damage is particularly significant in the case of oxide-protected semiconductor bodies inasmuch as high electric fields cause permanent breakdown of the dielectric coatings.
Accordingly, an object of this invention is an arrangement for selectively removing material from the surface of a workpiece without directly applying high voltages across the workpiece.
More specifically, an object of the invention is a backsputtering technique for effecting selective removal of portions of surface coatings on a semiconductor surface which includes dielectric oxide films.
In accordance with this invention, the workpiece is separated from the cathode member by an insulating layer and the cathode is so shielded as to result in the formation of a glow dischage region around the periphery of the semiconductor workpiece. Typically, the glow discharge region may be in the form of an annular ring or a rectilinear loop or annulus. This glow discharge region tends to spread somewhat with distance away from the cathode surface and, accordingly, tends to fill up some of the central volume directly over the workpiece.
The result of the formation of a cathode glow discharge in this pattern is to cause the gas ions, which are produced within the vacuum chamber of the sputtering apparatus, to move into the glow discharge region, gain energy and move out by the collision process to the space above the workpiece, and thence by further collision with other ions to impact substantially normally upon the surface of the workpiece. As is known, it is this ion impact which apparently products the sputtering action and material removal from the impacted surface. Thus, the semiconductor workpiece surface is bombarded Without applying directly across the semiconductor member the high voltage field which exists across the cathode member for producing the glow discharge region.
Inasmuch as the ions impact substantially normally on the workpiece surface, the material removal tends to occur in a very precise manner with a practically straightsided cutting action along the boundaries of the differentially Ice coated surface. In this connection, the invention is applicable to any differentially coated surface. By this is meant a surface which either has layers of differing thickness of the same material over different portions of the surface or in which different portions of the surface have coatings of different materials each having different sputtering efficiencies. In the former case where the same material is used but with heavier layers over some portions, the material will be removed by sputtering to a substantially equal depth over the entire surface but will, of course, disappear completely from the more thinly coated areas first. In the latter case where different materials are used, one material which sputters less efiiciently, and thus more slowly, than the others may constitute a mask to preserve portions underlying the mask while other portions are eroded and removed.
The invention and its other objects and features will be more clearly understood from the following detailed explanation taken in connection with the drawing in which:
FIG. 1 shows in schematic form apparatus suitable for the practice of the invention;
FIG. 2 is a plan view of the cathode member, the workpiece and the interposed insulating and shielding member,
FIG. 3 is a schematic representation of a portion of the apparatus depicting outlines in cross section of the glow discharge region in accordance with this invention; and
FIG. 4 is a partial cross section of the semiconductor workpiece, the underlying portion of the insulating member and a portion of the supporting cathode member.
Referring to FIG. 1, there is shown in schematic form a vacuum enclosure 10 represented by the broken line 11. Within the chamber and forming the base thereof is an anode member 12 which is held at ground potential. Shieldingly supported within the enclosure is a cathode member 13 to which a D.-C. supply is connected for applying relatively high negative potentials of the order of from three to ten kil-ovolts. schematically shown penetrating the base of the chamber are connections 14 for evacuating the chamber by conventional means such as diffusion pumps, and an inlet connection 15 with suitable stop valves 16 and 17. As represented by the inlet arrows, the main supply line may be connected to a source of argon gas and the auxiliary line controlled by stop valve 17 to an oxygen supply for providing protective oxide coatings, as will be explained more fully hereinafter.
As shown in FIG. 2, centrally placed on the cathode 13 is a similarly shaped ceramic member 18, and centrally mounted on ceramic member 18 is a semiconductor workpiece 19.
A pattern of deposited metallic electrodes in the form of stripes 20 are shown on the surface of the semiconductor workpiece. This pattern is primarily for exemplary purposes, and it will be understood that a variety of metal patterns may be used with this invention. The relationship of these stripes 20 to the other parts of the device structure are illustrated in more detail in the partial cross section shown in FIG. 4. In FIG. 4 the semiconductor workpiece portion 41 contains a series of three conductivity type regions making, for example, a transist-or. In addition to the original bulk portion of the silicon 41, there is shown a base region 44 defined by the pn junction 45 and an emitter region 46 defined by the second dilfused pn junction 47. On the surface of the silicon slice is a layer 48 of silicon oxide through which openings 61 and 62 have been made to expose surface portions of the base and emitter regions 44 and 46, respectively.
Ohmic contact is made initially to the silicon by depositing platinum over the entire oxide layer and heating the material to about 600 degrees centigrade. As disclosed in the aforementioned application of Lepselter, this causes a solid phase reaction akin to alloying between the platinum and the silicon. The platinum on the oxide surface, which is uncombined, then is readily removed by treating the surface with aqua regia. Solutions stronger than the usual three parts hydrochloric acid to one part nitric acid may be used to hasten the speed of platinum removal. This technique has the advantage I of leaving the alloyed platinum unaffected.
Following this a layer 49 of titanium is deposited so as to overlie the oxide layer 48 and to make contact to the alloyed surface regions. On top of the titanium layer is a second layer 50 of platinum. Finally, on top of the platinum layer a thin layer of aluminum is deposited. By means of a photoresist technique the aluminum plating is removed, using a suitable etchant, except for the stripe electrodes 51 and 52 which are in registration with the openings to the base and emitter regions. Inasmuch as the aluminum layer is relatively thin, of the order of several hundred angstroms, chemical etching produces a precise pattern delineation.
An alternative to the formation of these aluminum stripes is the formation of similar gold stripes which are of much greater thickness. Such gold stripes are readily produced to a precise pattern by depositing the gold on a photoresist pattern which defines the stripe area as uncoated portions of the surface. The gold deposited stripes may be built up to considerable thickness so as to provide a differentially coated surface. Thus, as described hereinafter, although the aluminum has poor sputtering efliciency and thus is not attacked substantially, the gold will be sputtered but because of its greater thickness will persist after all of the platinum and titanium have been removed.
To complete the fabrication of the electrode structure of the device in the semiconductor workpiece, the first and second metal layers, namely titanium and platinum, must be removed from the workpiece surface except where these layers underlie the aluminum stripe electrodes 5-1 and 52. In accordance with this invention, this removal is conveniently done by the process of backsputtering. This technique is particularly valuable where the spacing between the electrodes 51 and 52 is in the order of microns.
As shown in the cross sectional view of FIG. 4, the method of the invention requires an aluminum cathode number 43 upon which the semiconductor workpiece is mounted using an intermediate ceramic insulator 42.
An understanding of the uniqueness of the arrangement in accordance with this invention may be had from a description of the use of the apparatus. The conditions employed in cathodic sputtering are known (see Vacuum Deposition of Thin Films, L. Holland, I. Wiley & Sons, Inc., New York, 1956). In this process a known reactive gas such as, for example, hydrogen or any of the members of the rare gas family such as helium, argon or neon is introduced into the chamber. As set forth in the above text by Holland, the cathode sputtering system may be operated statically by providing a fixed pressure of gas in the system, or dynamically such that a fixed gas pressure is maintained with a constant flow of gas through the system.
In operation, the apparatus of FIG. 1 is subjected to a pressure of approximately ten microns of argon gas, and with the anode 12 at ground potential a negative voltage of five kilovolts is applied to the cathode. Under these conditions, as shown in FIG. 3, a glow discharge region having a cross section substantially as depicted by the broken outlines 31 is produced around the periphery of the ceramic member 18. This glow discharge region is annular in form and surrounds the workpiece on all sides, and extends, to some extent, over the space above the workpiece 19. This glow discharge region 31 represents primarily the cathode discharge region and is the source of energy for particles passing through or located within the region. Under the conditions described, argon gas ions are produced Within the vacuum chamber. As these particles move about, they collide and some are propelled into the glow discharge region where they gain energy and, by further collision, travel into the space above the workpiece and from thence into impact with the workpiece surface. One possible path is depicted by the arrowed broken line 32 connecting the circles representing gas particles in FIG. 3. It has been found that with the configuration shown, the bulk of the bombarding particles impact the workpiece surface substantially normally and consequently the cutting action of the sputtering process produces straightsided structures as represented by the broken lines 53 of FIG. 4. As shown in this same figure, the masking effect of the aluminum electrodes 51 and 52 combined with this sputtering process result in very sharply delineated patterns on the semiconductor workpiece surface.
The process described above in connection with this invention is most advantageous when compared with ordinary chemical etching techniques in which the eroding action proceeds at a differential rate as the etching depth increases. This tends to produce either undercutting or slope-sided cross sections rather than precise rectilinear cross sections. The value of the back-sputtering technique is particularly notable where the unmasked area has a width of the order of one-half mil or less. For such configurations, the use of chemical etching to depths of greater than several thousand angstroms is a practical impossibility insofar as applicant is aware.
The effectiveness of the arrangement described herein for back-sputtering material from a semiconductor surface on which a protective oxide coating has been placed will be recognized from the effect produced if the high cathode potential is applied across the workpiece itself. If, for example, the silicon oxide coating is about 5000 angstroms thick and the applied voltage is five -kilovolts, both of which are typical values, than the field applied to the dielectric oxide is about 10 volts per centimeter. This assumes that, as is the fact, most of the voltage drop occurs across the oxide layer. Inasmuch as the breakdown voltage for relatively high quality dielectric oxides is about 10 volts per centimeter, the result of such high applied fields tends to be pin-hole breaks through the oxide coating which, of course, effectively destroy the coating as a protective layer. In accordance with this invention, such consequences are avoided by the arrangement described above.
The foregoing back-sputtering technique for the selective removal of metal may be combined advantageously with known procedures for depositing coatings by cathode sputtering within the same vacuum chamber. In particular, oxide coatings may be produced on the semiconductor workpiece surface at any desired stage in the fabrication process by admitting controlled amounts of oxygen to the inlet lines using stop valve 17 as noted hereinbefore. By the reactive sputtering process well known in the art, oxide coatings of aluminum, for example, where the cathode member is aluminum may be deposited on the semiconductor member. Thus, it will be apparent that surfaces may be built up by deposition of metals, removed in who-1e or in part, and coated with dielectric layers, in succession using the apparatus as described above.
Moreover, it has been found that even though the devices disclosed in accordance with this invention are not provided with the overlay structure of metal and oxide layers disclosed in the aforementioned Lepselter applicaton, the devices herein have extremely good longterm stability which seems to arise simply as a consequence of the oxide coating having once been covered with metal. In particular, devices of the type disclosed herein where the oxide coating covers p-type conductivity material and where the two layers of metal have been deposited on, and then removed from the oxide surface, there appears to be very complete resistance to the formation of surface channels in this material which generally rendered such devices unusable.
Although the invention has been described in terms of a particular embodiment, it will be understood that other arrangemnts may be made by those skilled in the art which likewise will fall within the scope and spirit of the invention.
For example, other cathode configurations may be employed, even omitting the ceramic spacing member so long as the workpiece is electrically insulated from the cathode and the glow discharge region produced is peripherally disposed and out of contact with the workpiece.
What is claimed is:
'1. A method for the selective removal of material from the surface of a substrate having a dielectric coating thereon, comprising effecting a glow discharge in a low pressure gaseous ambient between an anode and a cath ode whereby an ionized gaseous plasma is formed in said glow discharge, electrically isolating an area of the surface of said cathode facing said anode larger than the References Cited by the Examiner UNITED STATES PATENTS 2,103,623 12/1937 Kott 204-192 2,702,274 2/1955 Law 204-192 2,848,542 7/ 195 8 Callahan 204-298 JOHN H. MACK, Primary Examiner.
R. MIHALEK, Assistant Examiner.

Claims (1)

1. A METHOD FOR THE SELECTIVE REMOVAL OF MATERIAL FROM THE SURFACE OF A SUBSTRATE HAVING A DIELECTRIC COATING THEREON, COMPRISING EFFECTING A GLOW DISCHARGE IN A LOW PRESSURE GASEOUS AMBIENT BETWEEN AN ANODE AND A CATHODE WHEREBY AN IONIZED GASEOUS PLASMA IS FORMED IN SAID GLOW DISCHARGE, ELECTRICALLY ISOLATING AN AREA OF THE SURFACE OF SAID CATHODE FACING SAID ANODE LARGER THAN THE CROSS SECTIONAL AREA OF SAID SUBSTRATE, BUT HAVING THE PERIPHERAL PORTIONS OF SAID CATHODE IN ELECTRICAL COMMUNICATION WITH SAID DISCHARGE, AND MOUNTING SAID SUBSTRATE BETWEEN SAID ANODE AND SAID ELECTRICALLY ISOLATED AREA OF SAID CATHODE SO THAT NO VOLTAGE DROP OCCURS THROUGH SAID DIELECTRIC COATING WHEREBY SAID GLOW DISCHARGE IS RESTRICTED TO THE REGION PERIPHERAL TO SAID SURFACE SO THAT IONS ARE IMPACTED ON SAID SURFACE REMOVING MATERIAL THEREFROM.
US347173A 1961-12-01 1964-02-25 Selective removal of material using cathodic sputtering Expired - Lifetime US3271286A (en)

Priority Applications (26)

Application Number Priority Date Filing Date Title
NL134170D NL134170C (en) 1963-12-17
JP7080263A JPS4316163B1 (en) 1963-12-17 1963-12-17
US347173A US3271286A (en) 1964-02-25 1964-02-25 Selective removal of material using cathodic sputtering
US388039A US3335338A (en) 1963-12-17 1964-08-07 Integrated circuit device and method
GB41932/64A GB1082317A (en) 1963-12-17 1964-10-14 Semiconductor devices and methods of making them
GB8614/67A GB1082319A (en) 1963-12-17 1964-10-14 Integrated circuit devices and methods of making them
IL22370A IL22370A (en) 1963-12-17 1964-11-02 Semiconductor devices and methods for their manufacture
IL22419A IL22419A (en) 1963-12-17 1964-11-09 Integrated circuit devices
NL6413364A NL6413364A (en) 1963-12-17 1964-11-17
IL22465A IL22465A (en) 1963-12-17 1964-11-17 Selective removal of material using cathodic etching
DE1639051A DE1639051C2 (en) 1961-12-01 1964-11-21 Method for producing an ohmic contact on a silicon semiconductor body
DEW38002A DE1282196B (en) 1963-12-17 1964-11-21 Semiconductor component with a protection device for its pn transitions
DEW38017A DE1266406B (en) 1963-12-17 1964-11-24 Method for producing mechanically retaining and electrically conductive connections on small plates, in particular on semiconductor plates
CH1535264A CH427044A (en) 1963-12-17 1964-11-27 Method for producing a semiconductor body with a protected pn junction
NL6414107A NL6414107A (en) 1963-12-17 1964-12-04
DE1964W0038104 DE1515321A1 (en) 1963-12-17 1964-12-08 Selective material removal with the aid of cathodic atomization
BE657022A BE657022A (en) 1963-12-17 1964-12-11
NL6414441A NL6414441A (en) 1963-12-17 1964-12-11
BE657021A BE657021A (en) 1963-12-17 1964-12-11
BE657023A BE657023A (en) 1963-12-17 1964-12-11
CH1604364A CH426042A (en) 1963-12-17 1964-12-11 Method for removing material from a body by means of cathodic sputtering
FR998732A FR1417621A (en) 1963-12-17 1964-12-15 Semiconductor contacts, and protective coatings
SE15227/64A SE325334B (en) 1963-12-17 1964-12-16
FR998912A FR1417695A (en) 1963-12-17 1964-12-16 Selective material removal using sputtering
FR999073A FR1417760A (en) 1963-12-17 1964-12-17 Integrated circuit semiconductor devices
CH1653864A CH444969A (en) 1963-12-17 1964-12-23 Contacted circuit arrangement and method for its production

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US3343256A (en) * 1964-12-28 1967-09-26 Ibm Methods of making thru-connections in semiconductor wafers
US3479269A (en) * 1967-01-04 1969-11-18 Bell Telephone Labor Inc Method for sputter etching using a high frequency negative pulse train
US3516920A (en) * 1967-06-09 1970-06-23 Nat Res Corp Sputtering apparatus
US3640811A (en) * 1969-11-03 1972-02-08 Rca Corp Method of metalizing semiconductor devices
US3640812A (en) * 1970-09-02 1972-02-08 Rca Corp Method of making electrical contacts on the surface of a semiconductor device
US3642548A (en) * 1969-08-20 1972-02-15 Siemens Ag Method of producing integrated circuits
US3708418A (en) * 1970-03-05 1973-01-02 Rca Corp Apparatus for etching of thin layers of material by ion bombardment
US3714521A (en) * 1971-07-26 1973-01-30 Rca Corp Semiconductor device or monolithic integrated circuit with tungsten interconnections
US3900944A (en) * 1973-12-19 1975-08-26 Texas Instruments Inc Method of contacting and connecting semiconductor devices in integrated circuits
US3904462A (en) * 1972-11-29 1975-09-09 Philips Corp Method of manufacturing etched structures in substrates by ion etching
US3932232A (en) * 1974-11-29 1976-01-13 Bell Telephone Laboratories, Incorporated Suppression of X-ray radiation during sputter-etching
US3984301A (en) * 1973-08-11 1976-10-05 Nippon Electric Varian, Ltd. Sputter-etching method employing fluorohalogenohydrocarbon etching gas and a planar electrode for a glow discharge
EP0005163A1 (en) * 1978-04-26 1979-11-14 International Business Machines Corporation Method for forming a Pt-Si Schottky barrier contact
US4248688A (en) * 1979-09-04 1981-02-03 International Business Machines Corporation Ion milling of thin metal films
US4620898A (en) * 1985-09-13 1986-11-04 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Ion beam sputter etching
US5310703A (en) * 1987-12-01 1994-05-10 U.S. Philips Corporation Method of manufacturing a semiconductor device, in which photoresist on a silicon oxide layer on a semiconductor substrate is stripped using an oxygen plasma afterglow and a biased substrate
US5362672A (en) * 1988-06-17 1994-11-08 Tadahiro Ohmi Method of forming a monocrystalline film having a closed loop step portion on the substrate
US6039168A (en) * 1971-04-16 2000-03-21 Texas Instruments Incorporated Method of manufacturing a product from a workpiece
US6176967B1 (en) 1998-09-16 2001-01-23 International Business Machines Corporation Reactive ion etch chamber wafer masking system
US9507232B2 (en) 2011-09-14 2016-11-29 View, Inc. Portable defect mitigator for electrochromic windows
US9638977B2 (en) 2012-03-13 2017-05-02 View, Inc. Pinhole mitigation for optical devices
US9885934B2 (en) 2011-09-14 2018-02-06 View, Inc. Portable defect mitigators for electrochromic windows
US10002764B1 (en) 2016-12-16 2018-06-19 Varian Semiconductor Equipment Associates, Inc. Sputter etch material selectivity
US10583523B2 (en) 2012-05-18 2020-03-10 View, Inc. Circumscribing defects in optical devices
US10684524B2 (en) 2010-11-08 2020-06-16 View, Inc. Electrochromic window fabrication methods
US10914118B2 (en) 2012-03-13 2021-02-09 View, Inc. Multi-zone EC windows
US11053580B2 (en) 2018-02-21 2021-07-06 Varian Semiconductor Equipment Associates, Inc. Techniques for selective deposition using angled ions

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Cited By (34)

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Publication number Priority date Publication date Assignee Title
US3343256A (en) * 1964-12-28 1967-09-26 Ibm Methods of making thru-connections in semiconductor wafers
US3479269A (en) * 1967-01-04 1969-11-18 Bell Telephone Labor Inc Method for sputter etching using a high frequency negative pulse train
US3516920A (en) * 1967-06-09 1970-06-23 Nat Res Corp Sputtering apparatus
US3642548A (en) * 1969-08-20 1972-02-15 Siemens Ag Method of producing integrated circuits
US3640811A (en) * 1969-11-03 1972-02-08 Rca Corp Method of metalizing semiconductor devices
US3708418A (en) * 1970-03-05 1973-01-02 Rca Corp Apparatus for etching of thin layers of material by ion bombardment
US3640812A (en) * 1970-09-02 1972-02-08 Rca Corp Method of making electrical contacts on the surface of a semiconductor device
US6467605B1 (en) 1971-04-16 2002-10-22 Texas Instruments Incorporated Process of manufacturing
US6076652A (en) * 1971-04-16 2000-06-20 Texas Instruments Incorporated Assembly line system and apparatus controlling transfer of a workpiece
US6039168A (en) * 1971-04-16 2000-03-21 Texas Instruments Incorporated Method of manufacturing a product from a workpiece
US3714521A (en) * 1971-07-26 1973-01-30 Rca Corp Semiconductor device or monolithic integrated circuit with tungsten interconnections
US3904462A (en) * 1972-11-29 1975-09-09 Philips Corp Method of manufacturing etched structures in substrates by ion etching
US3984301A (en) * 1973-08-11 1976-10-05 Nippon Electric Varian, Ltd. Sputter-etching method employing fluorohalogenohydrocarbon etching gas and a planar electrode for a glow discharge
US3900944A (en) * 1973-12-19 1975-08-26 Texas Instruments Inc Method of contacting and connecting semiconductor devices in integrated circuits
US3932232A (en) * 1974-11-29 1976-01-13 Bell Telephone Laboratories, Incorporated Suppression of X-ray radiation during sputter-etching
EP0005163A1 (en) * 1978-04-26 1979-11-14 International Business Machines Corporation Method for forming a Pt-Si Schottky barrier contact
US4248688A (en) * 1979-09-04 1981-02-03 International Business Machines Corporation Ion milling of thin metal films
US4620898A (en) * 1985-09-13 1986-11-04 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Ion beam sputter etching
US5310703A (en) * 1987-12-01 1994-05-10 U.S. Philips Corporation Method of manufacturing a semiconductor device, in which photoresist on a silicon oxide layer on a semiconductor substrate is stripped using an oxygen plasma afterglow and a biased substrate
US5362672A (en) * 1988-06-17 1994-11-08 Tadahiro Ohmi Method of forming a monocrystalline film having a closed loop step portion on the substrate
US6176967B1 (en) 1998-09-16 2001-01-23 International Business Machines Corporation Reactive ion etch chamber wafer masking system
US10684524B2 (en) 2010-11-08 2020-06-16 View, Inc. Electrochromic window fabrication methods
US10884310B2 (en) 2011-09-14 2021-01-05 View, Inc. Portable defect mitigators for electrochromic windows
US9885934B2 (en) 2011-09-14 2018-02-06 View, Inc. Portable defect mitigators for electrochromic windows
US10532948B2 (en) 2011-09-14 2020-01-14 View, Inc. Portable defect mitigator for electrochromic windows
US9507232B2 (en) 2011-09-14 2016-11-29 View, Inc. Portable defect mitigator for electrochromic windows
US11886088B2 (en) 2011-09-14 2024-01-30 View, Inc. Portable defect mitigators for electrochromic windows
US10534237B2 (en) 2012-03-13 2020-01-14 View, Inc. Pinhole mitigation for optical devices
US9638977B2 (en) 2012-03-13 2017-05-02 View, Inc. Pinhole mitigation for optical devices
US10914118B2 (en) 2012-03-13 2021-02-09 View, Inc. Multi-zone EC windows
US11550197B2 (en) 2012-03-13 2023-01-10 View, Inc. Pinhole mitigation for optical devices
US10583523B2 (en) 2012-05-18 2020-03-10 View, Inc. Circumscribing defects in optical devices
US10002764B1 (en) 2016-12-16 2018-06-19 Varian Semiconductor Equipment Associates, Inc. Sputter etch material selectivity
US11053580B2 (en) 2018-02-21 2021-07-06 Varian Semiconductor Equipment Associates, Inc. Techniques for selective deposition using angled ions

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