US3515892A - Load disabling circuit - Google Patents

Description

June 2, 1970 D. R. WITTBRODT LOAD DISABLING CIRCUIT Filed April 26, 1968 Patented June 2, 1970 3,515,892 LOAD DISABLING CIRCUIT Donald R. Wittbrodt, Warren, Mich., assignor to the United States of America as represented by the Secretary of the Army Filed Apr. 26, 1968, Ser. No. 724,353 Int. Cl. H025 3/00 U.S. Cl. 307-38 9 Claims ABSTRACT OF THE DISCLOSURE A load disabling circuit for preventing the simultaneous flow of current in more than one load of a multi-load circuit. An electronic valve means is connected to each of the loads. A switch means is connected to each of the valve means for controlling the conductive state of the valve means. Potential coupling means are connected between the valve means so that when one valve means is rendered conductive and current ilows to one load, all other valve means are prevented from conducting, thereby precluding current ilow to all other loads.

The invention described herein may be manufactured, used, and licensed by or for the Government for governmental purposes without payment to me of any royalty thereon.

This invention relates to a load disabling circuit and more particularly to an electronic circuit which will allow only one load of a multi-load circuit to be energized at any time.

In the past, it has been desirable to provide positive means for preventing the iloiw of current to more than one load of a multi-load circuit. rllhis has been accomplished by several devices, all of which has been proved unsatisfactory. For example, a gang switch may be utilized to interrupt current flow to more than one load, however, this is cumbersome and very slow reacting. Other devices have included relays which open and close suitable contacts connected to the Various loads, however, there 'has been no positive means of precl-uding the simultaneous iloW of current to more than one load. As will be obvious to one skilled in the art, a circuit which would prevent the ow of current to all loads with the exception of one could be utilized in many different types of equipment. For example, this circuit could be utilized to absolutely preclude the flow of current to the external lights of a military vehicle when the internal light were turned on. It could be used to preclude the flow of current to more than one of a series of motors. 1It could be utilized to insure that a press will not operate when material is being inserted into a machine.

It is an object of the present invention therefore to eliminate the aforementioned disadvantages.

It is another object of the present invention to provide a load disabling circuit for preventing the simultaneous flow of current in more than one load of multi-load circuit.

Still another object of the present invention is to provide an electronic circuit means for precluding the ow of current to more than one load of a multi-load circuit.

In order to accomplish the foregoing objects and in accordance with the .present invention, there is provided a load disabling circuit for preventing the dlow o-f current to more than one load of a multi-load circuit which utilizes an electronic valve means connected to each of the loads. A switch is connected to the electronic valve means for providing proper biasing potential for the electronic valve means to control its conduction. Conductor coupling means are provided between the valve means of the respective loads to couple the potential from the valve means of one load circuit to the valve -means of another load circuit.

Other objects and advantages of the present invention become apparent to those of ordinary skill in the art by the following description when considered in relation to the accompanying drawing of which:

The circuit diagram of the load disabling circuit according to the invention is shown in the single gure.

Referring now to the drawing, a source of D.C. potential is shown at 10 connected to each of loads 14, 16 and 18 by means of conductor 12. These loads can be any electronic, electrical, or electro-mechanical device. For simplification however, larrrploads are being used according to the embodiment shown. The `opposite side of loads 14, 16 and 18 are connected to collectors 22, 32, and 42 of NPN transistors 20, 30 and 40 respectively. Source 10 also supplies power to conductor 27 and reset switch 2S is closed as shown in the drawing. Biasing resistors 28, 38, and 48 are connected to conductor 27` for providing proper biasing potential for turning on each of transistors 20, 30 and 40. To prevent an inadvertent turn on in each of the transistors, a Zener diode 50, 52, and 54 is connected to the` base 24, 34 and 44 of transistors 20, 30 and 40 respectively.

The D.C. potential source 10 is also applied to conductor 13 through resistor 56. Connected to conductor 13 are switches 58, 60 and `62, These switches may be either manually controlled, electronically controlled, or remotely controlled in any suitable acceptable manner. Each of switches 5'8, 60 and 62 are connected to gate electrodes 64, 78 and 86 of silicon controlled rectitiers (SCRs) 70, 72 and `80. SCR 70` is shown as having its anode 66 connected to the emitter 26 of transistor 20. The cathode -68 of SCR 70 is connected to ground potential. Similarly SCR 72 has its anode 74 connected to connector 3'6 of transistor 30 and its cathode 76r connected to ground potential. Likewise SCR 80 has its anode 82 connected to emitter 46I of transistor 40 and its cathode y84 to ground potential. As is well known in the art, a positiver gating potential must be applied to the gates 64, 78 and 86 to forward bias the SCRs into. a conductive state. With the solid state device so biased, it conducts current through its anode-cathode path.

Connected between the collector 22 of transistor 20 and the base circuits of transistors 30- and 40 are potential coupling means comprising conductors 81 and 83 and diodes 82 and 84. Similarly potential coupling means comprising diodes 86 and 88 are connected between the collector 32 of transistor 30 and the base circuits of transistors 20 and 40.

By conductor means and diodes and 102 the collector 42 o-f transistor 40 is connected to the base circuit of transistors 20` and 30. In this manner the potential which appears at the collector of each of the transistors is coupled to the diodes 50, 52 and 54 which are located in the base circuit. If the lpotential appearing across the Zener diodes is greater than the break-down potential, the potential appearing at the collectors of the respective transistors will be transmitted directly to the base circuits of the other transistors. As will be described more fully hereinbelow in describing the operation of the system, when SCR 70 is turned on and transistor 20 is biased into conduction, the potential appearing at collector 22 of transistor 20 is near ground. This potential is coupled to the base electrodes 34 and 44 of transistors 30 and 4U. This near ground potential will be suicient to keep either of these transistors from conducting even though SCR 72 or 80 are turned on.

In operation, the initial state of the circuit will be assumed to have reset switch 25 in the closed position and switches 58, 60 and 62 in the opened position as shown in thedrawinglnitially, no power will be applied to any of the load circuits. Assuming that it is desired to apply current to load 14 only and to prevent a load current to be supplied to either load 16 or 18, switch 58 would be closed-applying a gating potential to a electrode 64. The potential appearing at the junction lof resistor 28 and Zener diode 50 will be assumed to be sufficient to exceed the break-down potential of Zener diode 50. With the SCR 70 turned on, current will fiow through resistor 28, diode 50, base 24 and emitter 26 through the anode cathode path 66, 68 and to ground. Transistor 20 will saturate and current will flow through the collector emitter path 212-26. As soon as SCR 70 is turned on, the anode 66 will approach near ground otential. Similarly the collector 22 of transistor 20 will approach near ground potential as transistor 20 saturates. The potential of collector 22 will be slightly above ground due to the small drop to the emitter collector of transistor 20 and the anode-cathode of SCR 70.

The potential appearing at collector 22 will be coupled through diodes 82 and 84 to the junction of diode 52 and resistor 38 and diode 54 and resistor 48. The Zener diodes 52 and 54 may be of such a value that the small potential appearing at the collector 22 will be insufficient to overcome the breakdown potential of these diodes, hence, precluding the transistors 30 and 40 from being biased into conduction. Assuming, however, that Zener diodes 52 and 54 are replaced by ordinary diodes having its cathode connected to the base 34 and 44 of transistors 30 and 40 respectively, these transistors would'still not turn on due to the low potential appearing at collector 22 of transistor 20. With the circuit in this condition, even though switches 60 and 62 were inadvertently closed so as to turn on SCR 72 and 80, the potential appearing at the base of transistors 30 and 40 would be sufiiciently low to preclude the turning on of either of these transistors. The circuit will remain in this condition until power is interrupted to the load 14 by either interrupting the current through SCR 70 or opening reset switch 25. This would cut off transistor 20 and the circuit would turn to its initial state.

Assuming that the gate potential is applied to gate 78 of SCR 72 by closing switch 60, transistor 30 would turn on and its collector 32 would go near ground potential. This potential would be coupled to the base circuits of transistors 20 and 40 by means of diodes 86 and 88 and would preclude their being turned on even though SCRS 70 and 80 were inadvertently gated on.

Therefore it can be seen that a circuit is provided wherein it is impossible to have more than one load energized at any time. When one load has been energized, it is impossible to turn on any of the other loads due to the hold-off potential at the base circuits of the transistors.

While the circuit has been shown and described with relation to the use of NPN transistors, it should be understood that these transistors may be replaced by suitable PNP transistors with accompanying change in the load potential source.

While the circuit has been shown and described with respect to an SCR, it should be understood that a solid state device which would enable it to be turned off as well `as on by applying suitable potential to its gate electrode could be utilized.

While the circuit has been shown and described as having the potential coupling means connected between the collectors of the transistors and the bases of the other transistors, it should be understood that the conductor means could be connected to the emitters of the respective transistors rather than the collectors. This would require further modification of the circuit and the attending problems associated with this modification provides less advantage than the preferred embodiment showing in the drawing.

I claim:

1. A load disabling circuit for preventing the simultaneous flow of current in more than one load of a multiload circuit comprising:

at least first and second loads,

4 d first and second switch means in circuit'relation-with said first and second loads respectively,

said first and second switch means includes rst and second gate controlled rectifiers each including anode, cathode and gate electrodes and means for changing the potential applied to said gate electrodes,

supply circuit means for connecting said first and second loads with a source of electrical power, first and second electronic valve means connected in circuit with said rst and second loads and said rst and second switch means respectively for interrupting the flow of current from said source to said loads in response to the opening and closing of said switch means whereby the conductive state of such valve means may be selectively changed, and potential coupling means in circuit relation with said first and second valve means for biasing said first and second valve means into oppositely conductive states,

whereby, when one of said loads is conducting current from said source, the other of said loads is precluded from conducting current.

2. A load disabling circuit as set forth in claim 1 whereeach valve means include first, second, and third terminals, said first terminal of said first and second valve means connected to said first and second loads respectively, said second terminal of said first and second valve means connected to said first and second switch means respectively, said potential coupling means comprising: rst conductor means connected between said first valve means and said third terminal of said second transistor and said conductor means connected between said second transistor and said third terminal of said first transistor.

3. A load disabling circuit according to claim 2 wherein said first and second conductor means includes diode means for precluding the interflow of current from said first load and said second valve means and said second load and said first valve means.

4. A load disabling circuit according to claim 1 wherein said first valve means comprises:

a first terminal connected to said first load,

a second terminal connected to said first switch mean and a third terminal connected to said second valve means.

5. A load disabling circuit as set forth in claim 4 wherein:

said second valve means includes first, second and third terminals, and

said potential coupling means comprises:

conductor means connected between said third terminal of said second valve means and said first valve means,

whereby the potential appearing at said first valve means is coupled to said third terminal of said second valve means.

6. A load disabling circuit according to claim 4 wherein said second valve means comprises:

said first terminal connected to said second load,

said second terminal connected to said second switch means and said third terminal, and said coupling means comprises:

' a first conductor means connected between said first valve means and said third terminal of said second valve means.

7. A disabling circuit according to claim 5 further comprising reset circuit means connected to each of said electronic valve means for precluding the flow of current to each of said first and second loads.

l8. A load disabling circuit as set forth in claim 1 wherein said first and second valve means comprise firstfand second transistors each including collector, emitter and base electrodes, said collector electrode of said rst and second transistors being connected to said rst and second loads respectively, said emitter electrodes of said rst and second transistors being connected to said first and second switch means respectively, said base electrodes of said iirst and second transistors connected to said potential coupling means.

9. A load disabling circuit as set forth in claim 8 wherein said potential coupling means comprises:

first diode having an anode connected to said collector of said lirst transistor and a cathode Connected to the base circuit of said second transistor;

a second diode having an anode connected to the co1- lector of said second transistor and a cathode connected to the base circuit of said first transistor.

References Cited UNITED STATES PATENTS 3,311,795 3/1967 Gilbert 307-*38 X ROBERT K. SCHAEFER, Primary Examiner 10 H. J. HoHAUsER, Assistant Examiner

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