US3617817A - Laminated ceramic structure for containing a semiconductor element - Google Patents

Laminated ceramic structure for containing a semiconductor element Download PDF

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US3617817A
US3617817A US887681A US3617817DA US3617817A US 3617817 A US3617817 A US 3617817A US 887681 A US887681 A US 887681A US 3617817D A US3617817D A US 3617817DA US 3617817 A US3617817 A US 3617817A
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conducting layer
perforated holes
conducting
ceramic sheet
ceramic
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US887681A
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Fumimaro Kawakatsu
Takahiko Ihochi
Takahiro Okabe
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Hitachi Ltd
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Hitachi Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01025—Manganese [Mn]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01039—Yttrium [Y]
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    • H01L2924/01079—Gold [Au]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
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    • H01L2924/30—Technical effects
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    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Definitions

  • a semiconductor element is generally enclosed in an airtight vessel, but it becomes more difficult to lead out many electrical paths with low resistivity from the element inside the vessel to the outside as the structure of the semiconductor element itself becomes more complex, for example, as in the case of an integrated circuit. That is, since such a type of package as a T-5 which has been used for transistors in the past is unsuitable for enclosing an integrated circuit, the so-called flat package and dual-in-line type package have been proposed as suitable a packages for an integrated circuit.
  • An object of the present invention is to reduce the electrical resistivity of an operation current supplying path to a semiconductor element in a package for a semiconductor element, particularly, an integrated circuit.
  • Another object of the present invention is to provide a package of which the heat dissipation function is increased.
  • Still another object of the present invention is to provide a package having a bottom plate comprised of laminated ceramics, in which a capacitor is contained in the bottom plate.
  • a package having a bottom plate comprised by piling up or laminated at least two ceramic plates, in which a semiconductor integrated circuit and a sealing means for enclosing the circuit are disposed on the principal surface of said bottom plate and the first metallized layer is extended between said ceramic plates, the operating electric power being supplied to said integrated circuit through the metallized layer which has a low electrical resistivity.
  • a second metallized layer is formed on one of the surfaces of said ceramic plates, and the second metallized layer faces said first metallized layer interposing a ceramic plate adjacent to the second metallized layer, thereby forming a capacitor.
  • the capacitor functions to decrease the power source impedance and to suppress the spike current.
  • FIGS. 1 and 2 are partial sectional views of a package according to an embodiment of the present invention.
  • FIG. 3 is a perspective view showing four ceramic sheets for constructing a bottom plate of the package shown in FIGS. 1 and 2;
  • FIG. 4 is a diagram showing connection of the Transistor- Transistor Logic circuit provided with an Off Buffer circuit, which is to be integrated in one semiconductor substrate.
  • a ceramic package 16 having a bottom plate 15, a middle plate 14 fixed on the bottom plate and an upper plate, that is, a sealing plate 8 attached to the middle plate.
  • the package having many leads 20-26 is suitable for containing, for example, a semiconductor integrated circuit as a semiconductor element 10.
  • the bottom plate 15 has a recess and the element 10 is fixed to a metallized layer 13 formed in the recess interposing a thin plate 9 such as a molybdenum plate plated with gold.
  • An elec trode of the element 10 is connected to a conducting layer 7 on a surface of the bottom plate by means of a connecting wire 11 comprised of, for example, gold.
  • This conducting layer 7 is connected to an outer lead 26.
  • the bottom plate 15 is comprised by four ceramic sheets 2, 4, 6 and 12 having a thickness of 005-1 mm. respectively. Most parts of the surface of the first ceramic sheet 2 are covered by a conducting layer 3.
  • the second ceramic sheet 4 to be piled on the first sheet 2 has perforated holes 310, 33c, 34c, 36c and 380 with, for example, 0.2 mm. in diameter having conducting layers formed on the inner wall of them and has a conducting layer 5 extending separately from the conducting layers in those holes.
  • the third ceramic sheet 6 to be piled on the second sheet has holes 3Ib,33b, 34b, 36b and 38b corresponding to the'perforated holes provided in the second sheet, respectively, and perforated holes 32b, 35b and 37b which meet said conducting layer 5.
  • a conducting layer 13 which short-circuits the perforated holes 32b, 35b and 37b is arranged.
  • the surface of the third sheet 6 and receives the semiconductor element.
  • the conducting layer 13 is connected to the conducting layer 5 with low resistivity through the inside of said perforated holes 32b, 35b and 37b.
  • a relatively large hole 40 for example, 8-9 mm.
  • Another wide conducting layers 42 is electrically connected to the conducting layer 13 through a conducting layer in the hole 35a and the conducting layer I3 is connected to the conducting layer 5 on the second sheet 4 through conducting layers in the perforated holes 32b, 35b and 3712. Therefore, the conducting layers 42, 44 and 48 are short-circuited with each other via the conducting layer 13 and 5.
  • the conducting layer 13 is not necessarily connected electrically to the conducting layers in the perforated holes 32b, 35b and 37b.
  • the bottom plate is manufactured by printing predeter mined patterns on four green ceramic sheets i.c.
  • the thus constructed bottom plate has a recess encircled by the inner wall of the hole 40 perforated in the fourth sheet 12.
  • a semiconductor integrated circuit substrate is connected to the conducting layer B in the recess interposing the thin metal plate 9 as shown in FIGS. 1 and 2. in this case the metal thin plate 9 is met necessarily required.
  • An input or output signal electrode of the integrated circuit is connected to the narrow conducting layer 7 for signal transmission. but a pair of power source terminals where the operation current flows are desirably connected to the wide conducting layers 41 and 42. in this case, the potential of the conducting layer 42 can be fixed to a reference potential such as earth potential.
  • a vessel for enclosing a semiconductor substrate in which the so-called large scale integration is realized is actually constructed to have a dimension of 25 mm. 22mm. 3 mm. and 40 outer lead wires according to the teaching of the present inventron.
  • One advantageous point of the above described vessel is that it can decrease the resistance of the operation current path. That is, many electrodes for transmitting operation current can be formed on the integrated circuit substrate, since many power source paths (for example, conducting layers 41-48 shown in FIG. 3) can be arranged on the surface of the bottom plate, therefore, there becomes unnecessary to extend the power source paths or to carry out a complex crossover interconnection on the surface of the semiconductor substrate.
  • many power source paths for example, conducting layers 41-48 shown in FIG. 3
  • Another advantageous point is that the heat generated in the integrated circuit substrate is rapidly dissipated since the conducting layers 3, 5 and 13 are formed on the surface of the ceramic sheets 2, 4 and 6 having a thickness of 0.05-1 mm.
  • the bottom plate also serves to increase the mechanical strength of the said package.
  • the capacitor constructed in the bottom plate of the vessel can be ad vantageously utilized as the capacitor C which is connected parallel to the power supply in order to decrease the power supply impedance. That is, in the package a capacitance nearly equal to a capacitance measured between the conducting layers 3 and 5 is measured between the conducting layers 41 and 42. Therefore, when a positive potential is applied to the conducting layer ill and a predetermined negative potential is applied to the conducting layer 42, the circuit shown in FIG. 4 is constructed and operates as follows. in the TTL circuit of FIG.
  • transistors 0 and Q which receive signals having a phase difference of 180 (Tr) to each other from a transistor Q, switch usually in such way that one of them is in the on state the other is in the off state.
  • Tr 180
  • delivery and acceptance of charge to a stray capacity C connected parallel to a load R is compulsorily carried out by the transistors 0 and Q then the response speed of the TTL circuit is risen.
  • transistors Q and Q sometimes take the same switching state simultaneously because of the relation of delay time. if both transistors Q, and Q take the one-state simultaneously, an excessive spike current flows. The bad influence on the power supply due to this spike current can be avoided by a suitable capacitor connected between the bus bars of the power source.
  • a capacitor for absorbing a spike current can be formed in a package without connecting a discrete capacitor between bus bars of a power source outside the package.
  • the conducting layer 13 shown in FIG. 3 can connect the conducting layer 13 shown in FIG. 3 to the conducting layer 3 by adjusting the position of the perforated hole instead of connecting it 0 the conducting layer 5, thus the device can be used keeping the conducting layers 13 and 3 at earth potential as occasion demands.
  • the conducting layer 5 is electrically shielded from outside since it is enclosed by the conducting layers 3 and K3 from both sides.
  • the conducting layer 13 can be formed in a wider area on the surface of the third ceramic sheet 6 without making it come into contact with the conducting layers in the perforated holes 31b, 33b, 3412, $1; and 38b. By doing this the dissipation of heat is further promoted.
  • the use of the capacitor formed in the bottom plate is not limited to said use and it can be used for other purposes, and furthermore, other elements such as other a capacitor or resistor can be formed in the bottom plate.
  • a vessel for containing a semiconductor element comprising:
  • first insulating plate having first and second principal surfaces facing each other and first and second perforated holes separated from each other;
  • first insulating plate having fifth and sixth perforated holes corresponding to said third and fourth perforated holes;
  • Another electrode of said element being electrically connected to other portions of said second conducting layer through said sixth and fourth perforated holes.
  • a vessel according to claim 1 wherein said first and second conducting layers are piled interposing said second insulating plate, thus forming a capacitor.
  • a vessel according to claim 1 wherein a power source is connected between said lead connected to said first conduct-' connected to one of said first and second conducting layers and said semiconductor element being placed on the third conducting layer.
  • a vessel according to claim 1 wherein a third insulating plate adheres closely to the whole surface of said second principal surface of said second insulating plate.
  • An integrated circuit device including,
  • a fourth ceramic sheet piled on said third ceramic sheet having seventh, eighth, ninth and tenth perforated holes corresponding to said third, fourth, fifth and sixth perforated holes respectively and an eleventh perforated hole having a diameter larger than those of said seventh, eighth, ninth and tenth perforated holes;
  • said electrodes including the first, second, third and j. means for electrically connecting said third, fourth, fifth 1 and sixth conducting layers to said first, second, third and fourth electrodes, respectively;
  • a sealing means constituting an airtight space together with said fourth sheet for enclosing said substrate; and p. a plurality of outer leads extending from said space to the outside through said sealing means and being electrically connected to said third, fourth, fifth and sixth conducting layers and the conducting layers for signal transmission respectively.
  • a device wherein a metallized layer is formed between said substrate and said third sheet and the metallized layer is electrically connected to one of said first and second conducting layers.

Abstract

A package having a bottom plate comprises by laminating at least two ceramic plates, in which a semiconductor substrate including an integrated circuit is fixed on the principal surface of said bottom plate and a conducting layer with low resistivity is extended between said ceramic plates, an operating current being supplied to said integrated circuit through the conducting layer, thus the ohmic loss is reduced at the time of supplying the operating current.

Description

United States Patent Fumimaro Kawakatsu Koganei-shi;
Takahlko lhochi, Kodalra-slii; Takahiro Okabe, llachioji-shi, all of Japan [72] Inventors [2]] Appl. No. 887,681
[22] Filed Dec. 23, i969 [45] Patented Nov. 2, I971 [73] Assignee Hitachi, Ltd.
Tokyo, Japan [32] Priority Dec. 25, 1968 [33] Japan [54] LAMINATED CERAMIC STRUCTURE FOR CONTAINING A SEMICONDUCTOR ELEMENT 8 Claims, 4 Drawing Figs.
' [52] U.S.Cl. 317/234 R,
317/235R,3l7/234G,3l7/234N,3l7]234,E. 3l7/l0l,l74/52R [Sl Int.Cl. l-l0Il5/00 [50] FieldolSearch 317/234. 233,233.l.235.4, lOl; I'M/52 [56] Relerenees Cited UNITED STATES PATENTS 3.497947 3/1970 Ardezzene 29/577 3,520,054 7/1970 Pensack et al.. 29/627 3,496,634 2/1970 Kurtz et al. 29/624 3,480,836 1 H1969 Arenstein.... 3l7/l00 Primary Examiner-John W. Huckert Assistant Examiner-B. Estrin Attorney-Craig, Antonelli & Hill PATENTEDMnv 2 l9?! 3,16 1 7. 8 1 7 SHEET 10F 2 INVENTORS FHMIMIIRO KAWAKATSM, rAKAHIKo ruooH rA AHI/Qo aKABE M4 ATTORNEYS PATENTEDuovz Ian V v 3.611817 snmanrz INVENTOR S "FuMrM/mn KAwAKATSu T KAurKo IHoc/H' and TAKAHIRO ORA/ 4 ATTORNEYS LAMINATED CERAMIC STRUCTURE FOR CONTAINING A SEMICONDUCTOR ELEMENT This invention relates to a vessel for containing a semiconductor element, particularly, a semiconductor integrated circuit.
A semiconductor element is generally enclosed in an airtight vessel, but it becomes more difficult to lead out many electrical paths with low resistivity from the element inside the vessel to the outside as the structure of the semiconductor element itself becomes more complex, for example, as in the case of an integrated circuit. That is, since such a type of package as a T-5 which has been used for transistors in the past is unsuitable for enclosing an integrated circuit, the so-called flat package and dual-in-line type package have been proposed as suitable a packages for an integrated circuit.
Now, recently the tendency has become very pronounced for integrated circuits to be of larger scale, so that it is more and more essential to achieve a circuit arrangement that can perform a complicated function by freely using the crossing interconnection technique on the surface of a semiconductor substrate. When a semiconductor substrate on which a large scale integrated circuit is realized is enclosed in a conventionally proposed vessel, it is difficult to form lead out conducting paths of a wide width, since the circuit requires many such lead out conducting paths. However, the ohmic loss produced in a lead or current path for leading operation current is required tobe made particularly small. In a conventional vessel a suitable alternative must be considered to allow the heat that is produced in a semiconductor substrate to be dissipated.
An object of the present invention is to reduce the electrical resistivity of an operation current supplying path to a semiconductor element in a package for a semiconductor element, particularly, an integrated circuit.
Another object of the present invention is to provide a package of which the heat dissipation function is increased.
Still another object of the present invention is to provide a package having a bottom plate comprised of laminated ceramics, in which a capacitor is contained in the bottom plate.
According to an embodiment of the present invention there is provided a package having a bottom plate comprised by piling up or laminated at least two ceramic plates, in which a semiconductor integrated circuit and a sealing means for enclosing the circuit are disposed on the principal surface of said bottom plate and the first metallized layer is extended between said ceramic plates, the operating electric power being supplied to said integrated circuit through the metallized layer which has a low electrical resistivity.
Further, a second metallized layer is formed on one of the surfaces of said ceramic plates, and the second metallized layer faces said first metallized layer interposing a ceramic plate adjacent to the second metallized layer, thereby forming a capacitor. When said integrated circuit is equivalently considercd to include a spike current source from the viewpoint of electrical circuit network, the capacitor functions to decrease the power source impedance and to suppress the spike current.
It is effective to form such first and second metallized layers on one surface of and between ceramic plates for dissipating the heat generated in said semiconductor integrated circuit.
Other objects and features of the present invention will become more apparent from the following description of some preferred embodiments of the present invention in conjunction with the accompanying drawings, in which:
FIGS. 1 and 2 are partial sectional views of a package according to an embodiment of the present invention;
FIG. 3 is a perspective view showing four ceramic sheets for constructing a bottom plate of the package shown in FIGS. 1 and 2; and
FIG. 4 is a diagram showing connection of the Transistor- Transistor Logic circuit provided with an Off Buffer circuit, which is to be integrated in one semiconductor substrate.
Referring to FIGS. 1 and 2, there is shown a ceramic package 16 having a bottom plate 15, a middle plate 14 fixed on the bottom plate and an upper plate, that is, a sealing plate 8 attached to the middle plate. The package having many leads 20-26 is suitable for containing, for example, a semiconductor integrated circuit as a semiconductor element 10. The bottom plate 15 has a recess and the element 10 is fixed to a metallized layer 13 formed in the recess interposing a thin plate 9 such as a molybdenum plate plated with gold. An elec trode of the element 10 is connected to a conducting layer 7 on a surface of the bottom plate by means of a connecting wire 11 comprised of, for example, gold. This conducting layer 7 is connected to an outer lead 26. The aforementioned problem which arises at the electrode lead out place is mainly solved by means of the special construction of the bottom plate in the present invention.
The construction of the bottom plate is described in detail with reference to FIG. 3, in which the same portion as in FIGS. 1 and 2 are indicated by the same reference numerals. In this embodiment, the bottom plate 15 is comprised by four ceramic sheets 2, 4, 6 and 12 having a thickness of 005-1 mm. respectively. Most parts of the surface of the first ceramic sheet 2 are covered by a conducting layer 3. The second ceramic sheet 4 to be piled on the first sheet 2 has perforated holes 310, 33c, 34c, 36c and 380 with, for example, 0.2 mm. in diameter having conducting layers formed on the inner wall of them and has a conducting layer 5 extending separately from the conducting layers in those holes. The third ceramic sheet 6 to be piled on the second sheet has holes 3Ib,33b, 34b, 36b and 38b corresponding to the'perforated holes provided in the second sheet, respectively, and perforated holes 32b, 35b and 37b which meet said conducting layer 5. A conducting layer 13 which short-circuits the perforated holes 32b, 35b and 37b is arranged. The surface of the third sheet 6 and receives the semiconductor element. The conducting layer 13 is connected to the conducting layer 5 with low resistivity through the inside of said perforated holes 32b, 35b and 37b. A relatively large hole 40, for example, 8-9 mm. in diameter is perforated at the center of the fourth ceramic sheet 12 to be piled on the third sheet and perforated holes 310-3841 corresponding to said perforated holes 3lb-38b are formed around the hole. Many conducting layers are formed radially around the perforated hole 40. Conducting layers 41 and 42 and conducting layers 43-48 adhering to the inner wall of the holes 380, 32a, 33a, 34a. 36a and 37a are formed in a wider width, for example, 0.5l mm. in width than a conducting layer for signal transmission represented by reference numeral 7 (this is, for example, is 0.1-0.3 mm. in width) in order to make the resistivity low. Incidentally, the conducting layers 3, 5 and I3 are clearly wider than the conducting layer 7 to make the re sistivity lower.
When these four ceramic plates are piled up, a part of the wide conducting layer 41 is connected to the conducting layer 3 on the first sheet through conducting layers formed in the holes 31a, 31b and 310. In the same way, conducting layers 45, 46, 47 and 43 contacting the perforated holes 33a, 34a, 36a and 38a, respectively, reach the conducting layer 3 through conducting layers in the holes 33b, 34b, 36b and 38b, and then conducting layers in the holes 33c, 34c, 36c and 38c, respectively. With the result that an electric current supplied to the conducting layer 41 flows firstly to the conducting layer 3 and is then led to the conducting layers 43, 45, 46 and 47 on the fourth ceramic sheet 12 through the conducting layers in said holes.
Another wide conducting layers 42 is electrically connected to the conducting layer 13 through a conducting layer in the hole 35a and the conducting layer I3 is connected to the conducting layer 5 on the second sheet 4 through conducting layers in the perforated holes 32b, 35b and 3712. Therefore, the conducting layers 42, 44 and 48 are short-circuited with each other via the conducting layer 13 and 5. In this case, the conducting layer 13 is not necessarily connected electrically to the conducting layers in the perforated holes 32b, 35b and 37b. The bottom plate is manufactured by printing predeter mined patterns on four green ceramic sheets i.c. an unsintered sheet provided by pressing a ceramic material such as M including a volatile binder) by the use of Mo-Mn ink, piling up the sheets and sintering them in the piled-up or laminated state The thus constructed bottom plate has a recess encircled by the inner wall of the hole 40 perforated in the fourth sheet 12. A semiconductor integrated circuit substrate is connected to the conducting layer B in the recess interposing the thin metal plate 9 as shown in FIGS. 1 and 2. in this case the metal thin plate 9 is met necessarily required. An input or output signal electrode of the integrated circuit is connected to the narrow conducting layer 7 for signal transmission. but a pair of power source terminals where the operation current flows are desirably connected to the wide conducting layers 41 and 42. in this case, the potential of the conducting layer 42 can be fixed to a reference potential such as earth potential.
A vessel for enclosing a semiconductor substrate in which the so-called large scale integration is realized is actually constructed to have a dimension of 25 mm. 22mm. 3 mm. and 40 outer lead wires according to the teaching of the present inventron.
One advantageous point of the above described vessel is that it can decrease the resistance of the operation current path. That is, many electrodes for transmitting operation current can be formed on the integrated circuit substrate, since many power source paths (for example, conducting layers 41-48 shown in FIG. 3) can be arranged on the surface of the bottom plate, therefore, there becomes unnecessary to extend the power source paths or to carry out a complex crossover interconnection on the surface of the semiconductor substrate.
Another advantageous point is that the heat generated in the integrated circuit substrate is rapidly dissipated since the conducting layers 3, 5 and 13 are formed on the surface of the ceramic sheets 2, 4 and 6 having a thickness of 0.05-1 mm. The bottom plate also serves to increase the mechanical strength of the said package.
Moreover, when, for example, such a circuit as shown in FIG. 4 is embodied in a semiconductor substrate, the capacitor constructed in the bottom plate of the vessel can be ad vantageously utilized as the capacitor C which is connected parallel to the power supply in order to decrease the power supply impedance. That is, in the package a capacitance nearly equal to a capacitance measured between the conducting layers 3 and 5 is measured between the conducting layers 41 and 42. Therefore, when a positive potential is applied to the conducting layer ill and a predetermined negative potential is applied to the conducting layer 42, the circuit shown in FIG. 4 is constructed and operates as follows. in the TTL circuit of FIG. 4 having the Off Buffer circuit, transistors 0 and Q which receive signals having a phase difference of 180 (Tr) to each other from a transistor Q, switch usually in such way that one of them is in the on state the other is in the off state. in the said Off Buffer circuit, delivery and acceptance of charge to a stray capacity C connected parallel to a load R is compulsorily carried out by the transistors 0 and Q then the response speed of the TTL circuit is risen. However, transistors Q and Q sometimes take the same switching state simultaneously because of the relation of delay time. if both transistors Q, and Q take the one-state simultaneously, an excessive spike current flows. The bad influence on the power supply due to this spike current can be avoided by a suitable capacitor connected between the bus bars of the power source. lf it is assumed that the spike current is a triangular wave with a peak value l =l 0 mA and a duration of 1r=5 nsec. and the power source voltage Vcc is 5 v., since a capacitance C ofa capacitor is required to absorb the spike current is calculated by a relation C,=O/Vcc=%l,,'1r/Vcc, the required capacitance C becomes 5 pf. or more.
Now, it is known that a capacitance C of a parallehplate condenser is given by the next relation according to the teaching of electrostatics.
zs sd wheree dielectric constant of free space,
5 specific inductive capacity ofa dielectric substance,
A effective area of an electrode plate,
d distance between electrode plates.
Therefore, it is easy for those skilled in the art to make a capacitor having a capacitance C,=5 itf. or larger in said bottom plate according to the above relationship.
After all, according to the present invention a capacitor for absorbing a spike current can be formed in a package without connecting a discrete capacitor between bus bars of a power source outside the package.
Only a few embodiments have been described above by way of understanding the present invention. Those who are skilled in the art can connect the conducting layer 13 shown in FIG. 3 to the conducting layer 3 by adjusting the position of the perforated hole instead of connecting it 0 the conducting layer 5, thus the device can be used keeping the conducting layers 13 and 3 at earth potential as occasion demands. in this case, the conducting layer 5 is electrically shielded from outside since it is enclosed by the conducting layers 3 and K3 from both sides. Further, in this case, the conducting layer 13 can be formed in a wider area on the surface of the third ceramic sheet 6 without making it come into contact with the conducting layers in the perforated holes 31b, 33b, 3412, $1; and 38b. By doing this the dissipation of heat is further promoted.
Moreover, it is clear that the use of the capacitor formed in the bottom plate is not limited to said use and it can be used for other purposes, and furthermore, other elements such as other a capacitor or resistor can be formed in the bottom plate.
We claim:
1. A vessel for containing a semiconductor element, comprising:
a first insulating plate having first and second principal surfaces facing each other and first and second perforated holes separated from each other;
a first conducting layer extending on said second principal surface;
a semiconductor element having a plurality ofelectrodes arranged on said first principal surface;
a sealing means arranged on said first principal surface,
which forms an airtight space together with said first insulating plate for enclosing said element;
a plurality oflead wires extending from said airtight space to the outside;
means for electrically connecting an electrode of said element to a first portion of said first conducting layer through said first perforated hole; and
means for electrically connecting a portion of one of said lead wires within said space to a second portion of said first conducting layer different from said first portion thereof through said second perforated hole, and further comprising a second insulating plate having first and second principal surfaces, the first of which is brought into intimate contact with said second principal surface of said first insulating plate, said second insulating plate being provided with third and fourth perforated holes which are not in conformity with said first and second perforated holes;
a second conducting layer extending on said second principal surface of said second insulating plate facing to said first principal surface thereof;
saifd first insulating plate having fifth and sixth perforated holes corresponding to said third and fourth perforated holes;
a portion of another one of said leads within said space being electrically connected to a portion of said second conducting layer through said fifth and third perforated holes; and
another electrode of said element being electrically connected to other portions of said second conducting layer through said sixth and fourth perforated holes.
2. A vessel according to claim 1, wherein said first and second conducting layers are piled interposing said second insulating plate, thus forming a capacitor.
3. A vessel according to claim 1, wherein a power source is connected between said lead connected to said first conduct-' connected to one of said first and second conducting layers and said semiconductor element being placed on the third conducting layer.
5. A vessel according to claim 1, wherein a third insulating plate adheres closely to the whole surface of said second principal surface of said second insulating plate.
6. A vessel according to claim 5, wherein the first, second and third insulating plate are made of a ceramic material and said first and second conducting layer includes molybdenum and manganese.
7. An integrated circuit device including,
a. a first ceramic sheet;
b. a second ceramic sheet piled on the first ceramic sheet and having first and second perforated holes;
c. a first conducting layer extending between said first and second ceramic sheets so as to form a bridge between the first and second perforated holes;
d. a third ceramic sheet piled on said second ceramic sheet and having third and fourth perforated holes corresponding to said first and second perforated holes and fifth and sixth perforated holes separated from the third and fourth perforated holes;
e. a second conducting layer extending between said second and third ceramic sheets so as to form a bridge between said fifth and sixth perforated holes;
. a fourth ceramic sheet piled on said third ceramic sheet, having seventh, eighth, ninth and tenth perforated holes corresponding to said third, fourth, fifth and sixth perforated holes respectively and an eleventh perforated hole having a diameter larger than those of said seventh, eighth, ninth and tenth perforated holes; 1
g. third, fourth, fifth and sixth conducting layers formed on said fourth ceramic sheet adjacently to said seventh, eighth, ninth and tenth perforated holes respectively;
h. a plurality of conducting layers for signal transmission extending on said fourth ceramic sheet, the width of each conducting layer for signal transmission being smaller than those of said third, fourth, fifth and sixth conducting layers;
i. a semiconductor integrated circuit substrate having a plurality of electrodes, which is arranged on the surface of said third sheet exposed in said eleventh perforated hole,
said electrodes including the first, second, third and j. means for electrically connecting said third, fourth, fifth 1 and sixth conducting layers to said first, second, third and fourth electrodes, respectively;
k. means for electrically connecting said third conducting layer to one portion of said first conducting layer through said seventh, third and first perforated holes;
1. means for electrically connecting said fourth conducting layer to another portion of said first conducting layer through said eighth, fourth and second perforated holes;
m. means for electrically connecting said fifth conducting layer to one portion of said second conducting layer through said ninth and fifth perforated holes;
n. means for electrically connecting said sixth conducting layer to another portion of said second conducting layer through said tenth and sixth perforated holes;
0. a sealing means constituting an airtight space together with said fourth sheet for enclosing said substrate; and p. a plurality of outer leads extending from said space to the outside through said sealing means and being electrically connected to said third, fourth, fifth and sixth conducting layers and the conducting layers for signal transmission respectively.
8. A device according to claim 7, wherein a metallized layer is formed between said substrate and said third sheet and the metallized layer is electrically connected to one of said first and second conducting layers.

Claims (7)

  1. 2. A vessel according to claim 1, wherein said first and second conducting layers are piled interposing said second insulating plate, thus forming a capacitor.
  2. 3. A vessel according to claim 1, wherein a power source is connected between said lead connected to said first conducting layer and said lead connected to said second conducting layer.
  3. 4. A vessel according to claim 1, wherein a third conducting layer is extended onto said first principal surface of said first insulating plate, the third conducting layer being electrically connected to one of said first and second conducting layers and said semiconductor element being placed on the third conducting layer.
  4. 5. A vessel according to claim 1, wherein a third insulating plate adheres closely to the whole surface of said second principal surface of said second insulating plate.
  5. 6. A vessel according to claim 5, wherein the first, second and third insulating plate are made of a ceramic material and said first and second conducting layer includes molybdenum and manganese.
  6. 7. An integrated circuit device including, a. a first ceramic sheet; b. a second ceramic sheet piled on the first ceramic sheet and having first and second perforated holes; c. a first conducting layer extending between said first and second ceramic sheets so as to form a bridge between the first and second perforated holes; d. a third ceramic sheet piled on said second ceramic sheet and having third and fourth perforated holes corresponding to said first and second perforated holes and fifth and sixth perforated holes separated from the third and fourth perforated holes; e. a second conducting layer extending between said second and third ceramic sheets so as to form a bridge between said fiFth and sixth perforated holes; f. a fourth ceramic sheet piled on said third ceramic sheet, having seventh, eighth, ninth and tenth perforated holes corresponding to said third, fourth, fifth and sixth perforated holes respectively and an eleventh perforated hole having a diameter larger than those of said seventh, eighth, ninth and tenth perforated holes; g. third, fourth, fifth and sixth conducting layers formed on said fourth ceramic sheet adjacently to said seventh, eighth, ninth and tenth perforated holes respectively; h. a plurality of conducting layers for signal transmission extending on said fourth ceramic sheet, the width of each conducting layer for signal transmission being smaller than those of said third, fourth, fifth and sixth conducting layers; i. a semiconductor integrated circuit substrate having a plurality of electrodes, which is arranged on the surface of said third sheet exposed in said eleventh perforated hole, said electrodes including the first, second, third and fourth electrodes for supplying the operating electric power to the circuit; j. means for electrically connecting said third, fourth, fifth and sixth conducting layers to said first, second, third and fourth electrodes, respectively; k. means for electrically connecting said third conducting layer to one portion of said first conducting layer through said seventh, third and first perforated holes;
  7. 8. A device according to claim 7, wherein a metallized layer is formed between said substrate and said third sheet and the metallized layer is electrically connected to one of said first and second conducting layers.
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US3730969A (en) * 1972-03-06 1973-05-01 Rca Corp Electronic device package
US3864810A (en) * 1972-09-27 1975-02-11 Minnesota Mining & Mfg Process and composite leadless chip carriers with external connections
JPS51134375U (en) * 1975-04-02 1976-10-29
US4038488A (en) * 1975-05-12 1977-07-26 Cambridge Memories, Inc. Multilayer ceramic multi-chip, dual in-line packaging assembly
US4115837A (en) * 1972-07-10 1978-09-19 Amdahl Corporation LSI Chip package and method
JPS557346U (en) * 1978-06-30 1980-01-18
US4226492A (en) * 1979-07-30 1980-10-07 Bell Telephone Laboratories, Incorporated Electrical interconnection apparatus
US4266239A (en) * 1976-04-05 1981-05-05 Nippon Electric Co., Ltd. Semiconductor device having improved high frequency characteristics
FR2476389A1 (en) * 1980-02-12 1981-08-21 Mostek Corp ELECTRONIC CIRCUIT BOX WITH ALIGNED AND OVERLAY SEMICONDUCTOR PELLETS
US4396971A (en) * 1972-07-10 1983-08-02 Amdahl Corporation LSI Chip package and method
WO1984001470A1 (en) * 1982-10-05 1984-04-12 Mayo Foundation Leadless chip carrier for logic components
US4451845A (en) * 1981-12-22 1984-05-29 Avx Corporation Lead frame device including ceramic encapsulated capacitor and IC chip
US4454529A (en) * 1981-01-12 1984-06-12 Avx Corporation Integrated circuit device having internal dampening for a plurality of power supplies
US4527185A (en) * 1981-01-12 1985-07-02 Avx Corporation Integrated circuit device and subassembly
US4551747A (en) * 1982-10-05 1985-11-05 Mayo Foundation Leadless chip carrier apparatus providing for a transmission line environment and improved heat dissipation
FR2576448A1 (en) * 1985-01-22 1986-07-25 Rogers Corp DECOUPLING CAPACITOR FOR ASSEMBLY WITH A PIN GRID ARRANGEMENT
US4626958A (en) * 1985-01-22 1986-12-02 Rogers Corporation Decoupling capacitor for Pin Grid Array package
US4658327A (en) * 1985-01-22 1987-04-14 Rogers Corporation Decoupling capacitor for surface mounted chip carrier
US4734818A (en) * 1985-01-22 1988-03-29 Rogers Corporation Decoupling capacitor for surface mounted leadless chip carriers, surface mounted leaded chip carriers and Pin Grid Array packages
US4734819A (en) * 1985-12-20 1988-03-29 Rogers Corporation Decoupling capacitor for surface mounted leadless chip carrier, surface mounted leaded chip carrier and pin grid array package
US5007083A (en) * 1981-03-17 1991-04-09 Constant James N Secure computer
US5170245A (en) * 1988-06-15 1992-12-08 International Business Machines Corp. Semiconductor device having metallic interconnects formed by grit blasting
US5196992A (en) * 1989-08-25 1993-03-23 Kabushiki Kaisha Toshiba Resin sealing type semiconductor device in which a very small semiconductor chip is sealed in package with resin
US5218168A (en) * 1991-09-26 1993-06-08 Micron Technology, Inc. Leads over tab
US5296736A (en) * 1992-12-21 1994-03-22 Motorola, Inc. Leveled non-coplanar semiconductor die contacts
US5400210A (en) * 1992-07-06 1995-03-21 Ngk Spark Plug Co., Ltd. Substrate having a built-in capacitor and process for producing the same
US5525834A (en) * 1994-10-17 1996-06-11 W. L. Gore & Associates, Inc. Integrated circuit package
US5576577A (en) * 1993-05-24 1996-11-19 Shinko Electric Industries Co., Ltd. Multi-layer lead-frame for a semiconductor device
US5657811A (en) * 1993-06-04 1997-08-19 Pcc Composites, Inc. Cast-in hermetic electrical feed-throughs
US5701032A (en) * 1994-10-17 1997-12-23 W. L. Gore & Associates, Inc. Integrated circuit package
US5861670A (en) * 1979-10-04 1999-01-19 Fujitsu Limited Semiconductor device package
US5959348A (en) * 1997-08-18 1999-09-28 International Business Machines Corporation Construction of PBGA substrate for flip chip packing
US6016005A (en) * 1998-02-09 2000-01-18 Cellarosi; Mario J. Multilayer, high density micro circuit module and method of manufacturing same
US6072211A (en) * 1998-08-03 2000-06-06 Motorola, Inc. Semiconductor package
US20040183184A1 (en) * 2003-03-20 2004-09-23 International Business Machines Corporation Composite capacitor and stiffener for chip carrier

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FR2514562B1 (en) * 1981-10-09 1985-06-07 Thomson Csf MULTI-LAYER HYBRID CIRCUIT WITH CAPACITORS AND INTERNAL CONNECTIONS
US4593384A (en) * 1984-12-21 1986-06-03 Ncr Corporation Security device for the secure storage of sensitive data
US4835120A (en) * 1987-01-12 1989-05-30 Debendra Mallik Method of making a multilayer molded plastic IC package
US4891687A (en) * 1987-01-12 1990-01-02 Intel Corporation Multi-layer molded plastic IC package
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US5824950A (en) * 1994-03-11 1998-10-20 The Panda Project Low profile semiconductor die carrier
US5821457A (en) * 1994-03-11 1998-10-13 The Panda Project Semiconductor die carrier having a dielectric epoxy between adjacent leads
US6339191B1 (en) 1994-03-11 2002-01-15 Silicon Bandwidth Inc. Prefabricated semiconductor chip carrier
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US3730969A (en) * 1972-03-06 1973-05-01 Rca Corp Electronic device package
US4115837A (en) * 1972-07-10 1978-09-19 Amdahl Corporation LSI Chip package and method
US4396971A (en) * 1972-07-10 1983-08-02 Amdahl Corporation LSI Chip package and method
US3864810A (en) * 1972-09-27 1975-02-11 Minnesota Mining & Mfg Process and composite leadless chip carriers with external connections
JPS5629974Y2 (en) * 1975-04-02 1981-07-16
JPS51134375U (en) * 1975-04-02 1976-10-29
US4038488A (en) * 1975-05-12 1977-07-26 Cambridge Memories, Inc. Multilayer ceramic multi-chip, dual in-line packaging assembly
US4266239A (en) * 1976-04-05 1981-05-05 Nippon Electric Co., Ltd. Semiconductor device having improved high frequency characteristics
JPS557346U (en) * 1978-06-30 1980-01-18
US4226492A (en) * 1979-07-30 1980-10-07 Bell Telephone Laboratories, Incorporated Electrical interconnection apparatus
US5861670A (en) * 1979-10-04 1999-01-19 Fujitsu Limited Semiconductor device package
FR2476389A1 (en) * 1980-02-12 1981-08-21 Mostek Corp ELECTRONIC CIRCUIT BOX WITH ALIGNED AND OVERLAY SEMICONDUCTOR PELLETS
US4527185A (en) * 1981-01-12 1985-07-02 Avx Corporation Integrated circuit device and subassembly
US4454529A (en) * 1981-01-12 1984-06-12 Avx Corporation Integrated circuit device having internal dampening for a plurality of power supplies
US5007083A (en) * 1981-03-17 1991-04-09 Constant James N Secure computer
US4451845A (en) * 1981-12-22 1984-05-29 Avx Corporation Lead frame device including ceramic encapsulated capacitor and IC chip
US4551747A (en) * 1982-10-05 1985-11-05 Mayo Foundation Leadless chip carrier apparatus providing for a transmission line environment and improved heat dissipation
US4551746A (en) * 1982-10-05 1985-11-05 Mayo Foundation Leadless chip carrier apparatus providing an improved transmission line environment and improved heat dissipation
WO1984001470A1 (en) * 1982-10-05 1984-04-12 Mayo Foundation Leadless chip carrier for logic components
US4626958A (en) * 1985-01-22 1986-12-02 Rogers Corporation Decoupling capacitor for Pin Grid Array package
FR2576448A1 (en) * 1985-01-22 1986-07-25 Rogers Corp DECOUPLING CAPACITOR FOR ASSEMBLY WITH A PIN GRID ARRANGEMENT
US4658327A (en) * 1985-01-22 1987-04-14 Rogers Corporation Decoupling capacitor for surface mounted chip carrier
US4734818A (en) * 1985-01-22 1988-03-29 Rogers Corporation Decoupling capacitor for surface mounted leadless chip carriers, surface mounted leaded chip carriers and Pin Grid Array packages
US4734819A (en) * 1985-12-20 1988-03-29 Rogers Corporation Decoupling capacitor for surface mounted leadless chip carrier, surface mounted leaded chip carrier and pin grid array package
US5170245A (en) * 1988-06-15 1992-12-08 International Business Machines Corp. Semiconductor device having metallic interconnects formed by grit blasting
US5196992A (en) * 1989-08-25 1993-03-23 Kabushiki Kaisha Toshiba Resin sealing type semiconductor device in which a very small semiconductor chip is sealed in package with resin
US5218168A (en) * 1991-09-26 1993-06-08 Micron Technology, Inc. Leads over tab
US5400210A (en) * 1992-07-06 1995-03-21 Ngk Spark Plug Co., Ltd. Substrate having a built-in capacitor and process for producing the same
US5296736A (en) * 1992-12-21 1994-03-22 Motorola, Inc. Leveled non-coplanar semiconductor die contacts
US5576577A (en) * 1993-05-24 1996-11-19 Shinko Electric Industries Co., Ltd. Multi-layer lead-frame for a semiconductor device
US5657811A (en) * 1993-06-04 1997-08-19 Pcc Composites, Inc. Cast-in hermetic electrical feed-throughs
US5701032A (en) * 1994-10-17 1997-12-23 W. L. Gore & Associates, Inc. Integrated circuit package
US5525834A (en) * 1994-10-17 1996-06-11 W. L. Gore & Associates, Inc. Integrated circuit package
US5959348A (en) * 1997-08-18 1999-09-28 International Business Machines Corporation Construction of PBGA substrate for flip chip packing
US6016005A (en) * 1998-02-09 2000-01-18 Cellarosi; Mario J. Multilayer, high density micro circuit module and method of manufacturing same
US6242286B1 (en) 1998-02-09 2001-06-05 Mario J. Cellarosi Multilayer high density micro circuit module and method of manufacturing same
US6072211A (en) * 1998-08-03 2000-06-06 Motorola, Inc. Semiconductor package
US20040183184A1 (en) * 2003-03-20 2004-09-23 International Business Machines Corporation Composite capacitor and stiffener for chip carrier
US6806563B2 (en) * 2003-03-20 2004-10-19 International Business Machines Corporation Composite capacitor and stiffener for chip carrier

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