US3757145A

US3757145A - Integrable igfet circuit

Info

Publication number: US3757145A
Application number: US00267794A
Authority: US
Inventors: F Adam; W Gollinger
Original assignee: Deutsche ITT Industries GmbH
Current assignee: TDK Micronas GmbH; ITT Inc
Priority date: 1972-06-30
Filing date: 1972-06-30
Publication date: 1973-09-04
Anticipated expiration: 1990-09-04

Abstract

This invention relates to an integrable solid-state circuit for controlling or regulating the effective threshold voltage of an insulated gate field effect transistor (IGFET). The substrate and the gate electrode of the IGFET are bridged by the series arrangement of a diode operating in the reverse direction and an auxiliary IGFET operated in the saturation range.

Description

United States Patent 1 Adam et al. Sept. 4, 1973 [54] INTEGRABLE IGFET CIRCUIT 3,395,290 7/1968 Farina 307/205 3,566,307 2 1971 M [75] Inventors: Fritz f Freburgi 3,708,694 1l1973 Ev an Wolfgang Golfing", Gundelfingen, 3,624,419 11/1971 Kosonocky 307/279 both of Germany 3,712,995 1 1973 Steudel 307 304 [73] Assignee: ITT Industries, Inc., New York,

NY Primary ExammerJohn W. Huckert Assistant Examiner-R. E. Hart [221 Wed: June 1972 Alt0rney-C. Cornell Remsen, Jr., Menotti J. Lom- [2] 1 Appl. No.: 267,794 bardi,Jr. et al.

52 us. CI. 307/304 [57] ABSTRACT [51] Int. Cl. H031: 3/26 This inv n i n relates to an integrable solid-state cir- [58] Field of Search 307/205, 251, 279, cuit for controlling or regulating the efiective threshold 307/304; 317/235 21 voltage of an insulated gate field effect transistor (IG- FET). The substrate and the gate electrode of the [56] Refer n e Cited IGFET are bridged by the series arrangement of a UNITED STATES PATENTS diode operating in the reverse direction and an auxil- I I 3,610,962 10/1971 Meyer 307 251 my GFET operated m the saturat'on range 10 Claims, 14 Drawing Figures r U B U 7 e" 8 s-- G PATENIED 3.757. 145

SHEET 0 8 (1F 14 PAIENTEB 41975 SHEH 12 0F 14 Fig.

mm m; 3.757.145

sum 130F14n INTEGRABLE IGFET CIRCUIT BACKGROUND OF THE INVENTION This invention relates to an integrable solid-state circuit for controlling or regulating the effective threshold voltage of an insulated gate field effect transistor (IG- FET).

The main difficulty in the manufacture of IGFET transistors and switching circuits, resides in realizing the desired value of the threshold voltage with sufficient accuracy and constancy. In particular, it is difficult to obtain low threshold voltages with a good yield. Low threshold voltages are necessary in cases where the switching circuits, for the sake of obtaining small power losses, are to be operated at low operating voltages.

SUMMARY OF THE INVENTION It is an object of the present invention to realize constant threshold voltages which are extensively independent of the technology. In particular, the problem resides in the fact of realizing constant low threshold voltages and, in one specific type of embodiment, of realizing the threshold voltage zero.

The general idea of invention for solving this problem resides in the fact of enforcing the constancy of the effective threshold voltage by means of an auxiliary circuit integrable in accordance with semiconductor technology, whereas the actual threshold voltage of the individual transistor may vary within relatively wide limits. By means of the auxiliary circuit it shall be possible to adjust the affective threshold voltage by means of an external auxiliary voltage U to a certain value, for example to the value volt. This auxiliary voltage may be derived from the operating voltage U with the aid of a voltage divider.

According to a broad aspect of the invention there is provided an improved integrable solid state circuit for adjusting or controlling the effective threshold voltage of an insulated gate field effect control transistor of the enhancement type, wherein the substrate is applied to ground potential and wherein the input signal with reference to said substrate is applied via a coupling capacitor to the gate electrode, wherein the improvement comprises a semiconductor diode bridging the substrate and the gate electrode of said insulated gate field effect transistor, said diode operating in the reversed direction below the breakdown voltage, an auxiliary insulated gate field effect transistor of the enhancement type forming a series arrangement with said semiconductor diode, said auxiliary transistor operated in the saturation range with a reversed current smaller than the reversed current of said diode, and having a drain electrode at a potential greater than that of the gate potential reduced by the amount of the threshold voltage, and having a substrate applied to ground potential and a source of a constantly adjustable voltage coupled between the substrate and the gate electrode of said auxiliary transistor for controlling the effective threshold voltage of said auxiliary transistor.

Accordingly, and with respect to the substrate, a biasing potential is applied to the gate electrode, which is taken off the diode of a voltage divider consisting of a diode and of an enhancement type auxiliary IGFET. This biasing potential is determined by an auxiliary voltage applied to the gate electrode with respect to the substrate, while the voltage applied to the drain electrode of the auxiliary transistor, has no influence upon the biasing potential within certain limits. The reverse current of the auxiliary transistor must be smaller than the reverse current of the diode.

In the most simple case and in such a type of integrable solid-state circuit according to the invention, the drain electrode of the auxiliary transistor is applied to a battery voltage, while the auxiliary voltage is obtained therefrom with the aid of an ohmic voltage divider.

In one further embodiment of the integrable solidstate circuit according to the invention there is provided instead of the ohmic voltage divider an integrable voltage-dividing arrangement, consisting of the series arrangement of two insulated gate field effect transistors and a semiconductor diode. In this particular case, the auxiliary voltage is taken ofl the series arrangement of these two transistors, with the gate electrodes thereof being electrically connected to the respective associated drain electrodes. In this type of voltage divider too, the reverse current of the series arrangement of these two transistors must be smaller than the reverse current of the diode.

The above and other objects of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows the basic circuit of an integrable solidstate circuit according to the invention;

FIG. 2 explains the voltage division between the transistor T and the diode D of FIG. 1;

FIG. 3 sectionally and in a top view on to a semiconductor waver, shows an integrated circuit according to the invention;

FIG. 4 sectionally shows the sectional views referred to in FIG. 3, and extending vertically in relation to the semiconductor surface,

FIG. 5 the inventive further embodiment of an integrable circuit according to the invention including a circuit for producing an effective threshold voltage of 0 volt;

FIG. 6 serves to explain the voltage division between the series arrangement T, and T on one hand, and D on the other hand;

FIG. 7 shows the mutual conductance g, as a function of the technological threshold voltage U as plotted in a normalized representation y (x);

FIG. 8 is the graphical representation of the substrate effect AU at the transistor T, as a function of U -U- as calculated from equations (2) and (4) with respect to different substrate dopings;

FIG. 9 is the graphical representation of the mutual conductance g, as a function of the technological threshold voltage U as plotted in a normalized representation y (x);

FIG. 10 shows the use of an integrable circuit according to the invention in an arrangement employing complementary insulated gate field effect transistors T and T with an effective threshold voltage of 0 volt;

FIG. 11 shows a circuit diagram of a complementary inverter employing complementary insulated 'gate field effect transistors by using integrable solid-state circuits according to the invention;

FIG. 12, in a top view upon a semiconductor waver, shows the integration of the complementary inverter according to FIG. 10;

FIG. 13 is the graphical representation of the admissible surface charge density N, as a function of the gate capacitance C with respect to the dopings of the substrate, the well and the polycrystalline silicon gate as stated in the associated table I; and

FIG. 14 shows graphical representations in which the speed measure y as a function of the surface charge concentration N, is shown with respect to complementary switching circuits with and without a compensating network.

DESCRIPTION OF THE PREFERRED EMBODIMENT The basic circuit according to the invention is shown in FIG. 1 and consists substantially of the circuit shown within the dashlined box 7 and forming part of the insulated gate field effect transistor T,. Preferably, this circuit is integrated with the transistor T or the entire switching circuit in accordance with the known semiconductor technology, and is supplied with both the operating voltage U and the auxiliary voltage U via an external voltage divider. In cases where an ohmic volrage divider is used, any arbitrary effective threshold voltage can be-adjusted within certain limits by means of the auxiliary voltage.

Between the points B and K there is arranged the internal voltage divider consisting of the diode D and the auxiliary transistor T Owing to 1U IU I it will be seen that T, is always in the state of saturation, i.e., the current-voltage characteristic is given by:

wherein:

I reverse current of transistor T B its mutual conductance parameter,

U its normal threshold voltage for U 0,

U 0 the voltage at G as appearing during normal condition and AU (U =AU ,(U the so-called substrate effect which adds up to the threshold voltage and which is quite generally given by U indicates the voltage between the source and the substrate (bulk) of the respective transistor. At T, it will be seen that U U U In FIG. 1 there are shown p-channel-type transistors. In this case all U-quantities are negative. With positive Us the equation (1) also applies to n-channel-type transistors.

The voltage division at T, and D, is illustrated in FIG. 2 by the current-voltage characteristics 1 (U of the two branches of the voltage divider. With respect to the diode there is assumed a constant reverse current 1 Under the condition that l onsvl l nspl and by equalling |I |I there is obtained the rest potential at G from with When use is made of the equation (2), the equation (4) can be solved algebraically or graphically according to U so that U 0 and U will then be obtained in the form:

0 0 s 0 (UH: 102, 2)

A U A U'rz H, 02 2) The efiective threshold voltage of the transistor T as enlarged by the auxiliary circuit, and when seen from G, i.e. when controlled via C will thus become:

In this i CTI 01 is the sum of the gate capacitance C C W L and the parasitic capacitance of the diode D With the equation (4) the following will become from equation (50):

Withoutthe substrate effect at T i.e. for U 0, equation (5) proceeds to: U =[I (C /C91 [U Um U (UG' o) 8U; -UH] (5C) The factor (1 c,/c, in equations (5a, b, c) is due to the voltage division at the series arrangement of the capacitances C, and C in which case C indicates the oxide capacitance of T and C, indicates a coupling capacitance. Normally, C, will be chosen substantially greater than C so that there will result a large grid transparency from G.

The transistor T, may be driven capacitively into saturation from G via C, by means of a voltage pulse (which is negative in the case of p-channel-type transistors). If, in the course of this, the potential at G, changes from 0 to U then there will appear momentarily at G the potential which, owing to the high resistivity of the internal voltage divider for |U My (see FIG. 2) only decreases very slowly by way of discharge across the diode, again in direction towards U When assuming constant reverse current, U after a period of time A t, will drop from U to When permitting, with respect to the switch-on pulse, a maximum decrease by percent, i.e.,

there will result as the maximum admissible switch-on period If now, at G, the potential is again switched from U, to 0, the U will first of all assume momentarily the value I m spl" IITZ an] but then goes very rapidly back almost near U owing to the low resistivity of the transistor characteristic T, for lU I U 0 (see FIG. 2), in other words,

wherein 8' U o is dependent upon the duration of the switch-on pulse A t, as well as upon the duration of the swtich-off pulse A 1,. Under the condition that Ar, 5 At,

the deviation 8* U 1 also at a random repetition of the pulses, will not exceed the maximum value With respect to the rest value (5c), therefore, the ef fective threshold voltages will increase during pulse operation to:

order to cause the rest value (50) to disappear rea there must be set on the potentiometer the auxiliary voltage Ugo Um Um A U (U o)+ Therefore, acc. to (4) and as it should be in this particular case, the following potential is applied to G:

A top view of an integrated circuit of the type referred to in FIG. 1, is shown in FIG. 3 of the drawings. Various cross-sectional views of this sandwich-gate structure are shown in FIG. 4. As the conductor material for the intermediate gate G it is above all suitable to use polycrystalline deposited highly-doped silicon. However, it is also possible to use evaporated metals, such as tungsten or molybdenum. The diffused source region 1 of T, simultaneously constitutes the pn-diode D, to the substrate 2. The gate G can be realized in the usual way by the evaporation of aluminum. Prior thereto, there is still deposited the dielectric 3 for C, on G. In the interest of a high mutual conductance, C, is made as large as possible, i.e., appropriately by combining the following measures:

a. Large surface for C,(see additional surface for C, over the thick oxide 4 in FIGS. 3 and 4, into which there are etched the windows 5 and 6).

b. Use of a dielectric 3 having a high dielectric constant E with respect to C, (such as silicon nitride).

c. Causing the dielectric 3 for C, to have a very small layer thickness.

In further embodying the invention, the voltage divider is integrated with the semiconductor switching circuit and may be constructed or built up in such a way that the auxiliary voltage U automatically assumes the value U as stated in equation (8). On account of this, the effective threshold voltage of transistor T will become UN-e 0.

A circuit performing this, is shown in FIG. 5 outside the dash-lined box 7. The external voltage divider consists of two insulated gate-field effect control transis tors T, and T, arranged in series with a diode D,. The effect of this voltage divider is illustrated in FIG. 6 by the l( U characteristics of the two divider sections. Under the condition that the diode reverse current is greater than the reverse current I as passing through the control transistors T, and T there will result at G- the voltage When comparing the equations (8) and (9) it will become evident that actually provided that the two conditions and are met.

Normally, the condition (10a) is always met in the case of an integrated structure, because in that case there may be expected the equality of all threshold voltages (Um, U,,,) on-one crystal.

The condition (10b) only involves a relatively small correction. This condition, however, may also be met by way of suitable dimensioning, because the reverse currents and the Bs in (4a) and (9b) are dependent upon geometry. As is well known, the following applies to the Bs:

B, ,u. C W, L, p. mobility, C gate oxide capacity per surface, W, width and L, length of the channel of T,). In the case of an equal reverse-current difference l'nnsv' 12ml l nasnl l msni equal a and equal C the condition such as (10b) is met, e.g., by the following dimensioning:

With the aid of simple means, however, the effective threshold voltage, instead of to zero, may be compensated to a small defined value which is extensively independent of technology.

According to equations (50) and (9), the effective threshold voltage is given by:

When purposely deviating now from the conditions (10a) or (10b) which, together cause the square bracketed expression to disappear, it is possible to realize small defined threshold voltage values.

One deviation from the condition (10a) can be realized, for example, in an advantageous manner, by using gate electrodes having a different electron work function #2,. In the case of p-channel transistors, the necessary negative threshold voltage will be obtained when making the sum of all work functions of the gate electrodes of transistors T, and T, smaller than the corresponding sum of T, and T In the case of n-channel transistors the necessary positive treshold voltage is obtainable by realization of the following condition:

ml m2 m3 fll4 It is of particular advantage to make, in both cases,

4), 4:, and to make only the work functions of the gate electrodes of T,, and T, different, i.e.

,,,, da for p-channel transistors 4), for n-channel transistors The aforementioned special advantage resides in the fact that in this way there will disappear in (5d) the difference of the substrate efi'ects:

When using silicon gate electrodes, the above conditions relating to p-channel as well as to n-channel transistors may be met by doping the gate electrode of T more highly than the one of T, (N N,) if, as customary, the gate electrodes in the case of p-channel transistors are given a p-type doping, and an n-type doping in the case of n-channel transistors.

Accordingly, the following will result in this particular embodiment for the effective threshold voltage:

lU l =[l +(C,/C,)]- kT/q ln (N /M) wherein the condition (10b) is assumed to have been met.

Consequently, the effective threshold voltage is independent of the substrate doping and of the concentration of surface charges and surface conditions. It is only still dependent upon the capacitances C, and C which are technologically easy to control, and upon the dopings N, and N of the gate electrodes. However, no high demands are placed on the accuracy of the dopings N, and N as they only logarithmically enter the expression for the threshold voltage.

A small threshold voltage deviating from zero, however, can be realized also in that the condition (10b) is replaced by This is accomplished e.g. by suitably selecting the transistor geometries, so that the following relation will be applicable:

i 2) [2. 192.89 Ta4,sp) 01. s. In, WW2

The maximum mutual conductance of the circuit according to FIG. 5 is now to be compared with the maximum mutual conductance of the simple insulated gate field efiect transistor T,, respectively for a control voltagfi Gnwz- The following applies to the simple transistor (1):

gm" Bl Gnuu:

The following applies to the circuit (II):

B1 it/( l 2) Gmu- UNA!!!) U may be calculated from equation (50). When assuming with respect to the normal case equal threshold voltages on the crystal (U U and when making, in accordance with equation (10b) 8U, 8U the following will apply to U according to equation (9) and according to FIG. 6:

and the following applies to the effective threshold voltage according to (Sc) and (8b):

T0,efI

0 t for 2U +AUT4 UT )SUB AU, is to be calculated according to equations (2) and (4) with U U 0 and U U With respect to the mutual conductance there will now be obtained with the aid of l 2) and (14) the following relationship or, in a non-dimensional notation, with x U /U and y m (Bl Gnuu) and correspondingly, the following will apply to the simple insulated gate filed effect transistor:

y u, I Bl GIM 1 FIG. 7 shows the normalized mutual conductances Y" (x) and Y""(x) in a graphical representation with respect to the special case where U, U

The following is applicable with respect to the compensating circuit according to FIG. 5:

and in this case U IU l. The substrate efiect A U12 has been calculated from equations (2) and (4) U352 U6" 0 U l,5 VOlt, N I 10"(31'11 and C0; 35 nF/cm 8% has been neglected.

When neglecting the substrate effect, then W" (x) with respect to the various C-conditions, would be represented by the dashlines. The solid lines show to have taken into consideration the substrate effect. They are calculated with respect to

U z U U B

1,5 volt, N 1.10" cm With respect to other N- values, FIG. 8 shows the substrate effect A U as a function of (U,, U

The following may be taken from FIG. 7, as well as from equations (16) and l7):

1. that with respect to a certain medium U -range the mutual conductance of the circuit is better than that of transistor Y" Y" (hatch-lined in FIG. 7 with respect to C lC, 4),

2. that with respect to O U 1/2 [U U (U,,,)] the mutual conductance of the circuit is constant, i.e., independent of U It is possible to extend the range of constant mutual conductance when choosing U to be greater than U that is, when applying the outer voltage divider to a special source of voltage U U This source of voltage is in the course of this only loaded statically with reverse current.

A similar diagram as in FIG. 7 (mutual conductance with respect to threshold voltage) is shown in FIG. 9; in this case, however, with U ZU Now the threshold voltage U may increase up to the magnitude of U before the mutual conductance starts to decrease. I-Iere, as in the general case, the break point (knee) is lying at The following applies to the simple insulated gate field effect transistor:

U Gum:

IN this particular case with U /U 2. The substrate efiect AU has been calculated from (2) and (4) U331: U6 0, U: U3: 3 V, N: 10 CHI and C 35 nF/cm .SU, has been neglected.

Since the described circuit for realizing an externally adjustable effective threshold voltage, or for realizing an effective threshold voltage zero, can be applied to p-channel as well as to nchannel insulated gate field effect transistors, it may also be used advantageously in connection with complementary switching circuits. The described circuit can be advantageously applied especially to complementary switching circuits of the low operating voltage type, because in this case the simultaneous technological realization of the two threshold voltages for the pand n-type channel with the desired accuracy, is particularly difficult.

According to the conventional complementary technique the n-channel transistors are accommodated in

Claims

1. An improved integrable solid state circuit for adjusting or controlling the effective threshold voltage of a first insulated gate field effect control transistor of the enhancement type, wherein the substrate is applied to ground potential and wherein the input signal with reference to said substrate is applied via a coupling capacitor to the gate electrode, wherein the improvement comprises: a semiconductoR diode bridging the substrate and the gate electrode of said insulated gate field effect transistor, said diode operating in the reverse direction below the breakdown voltage; an auxiliary second insulated gate field effect transistor of the enhancement type forming a series arrangement with said semiconductor diode, said auxiliary transistor operated in the saturation range with a reverse current smaller than the reverse current of said diode, and having a drain electrode at a potential greater than that of the gate potential reduced by the amount of the threshold voltage, and having a substrate applied to ground potential; and a source of a constantly adjustable voltage coupled between the substrate and the gate electrode of said auxiliary second transistor for controlling the effective threshold voltage of said auxiliary transistor.

2. An improved integrable solid state circuit according to claim 1 wherein the threshold voltage of said auxiliary second transistor is controlled by a voltage developed across an ohmic voltage divider having one external connection applied to the drain electrode of said auxiliary second transistor.

3. An improved integrable solid state circuit according to claim 1 further comprising: third and fourth insulated gate field effect transistors; a second diode forming a series arrangement consisting of said second diode and said third and fourth insulated gate field effect transistors, said diode having a reverse current which is greater than that of said series arrangement, said third and fourth insulated gate field effect transistors having substrates coupled to ground potential, having gate electrodes connected to the drain electrode of said insulated gate field effect control transistor, the source electrode of said third insulated gate field effect transistor coupled to ground potential and the gate and drain electrode of said third insulated field effect transistor coupled to the source electrode of said fourth insulated gate field effect transistor, and the gate and drain electrode of said fourth insulated gate field effect transistor connected to said second diode.

4. An improved integrable circuit according to claim 3 wherein the channel lengths L, channel width Wand reverse currents IT2,Sp of said auxiliary second transistor, the reverse current IT34,Sp of the series connection of said third and fourth transistors, as well as the reverse currents ID,Sp of said first and second diodes are related by the formula

5. An improved integrable circuit according to claim 4 wherein

6. An improved integrable circuit according to claim 3 wherein the gate electrode of said first transistor, in the case of a circuit consisting of N channel transistors, is made from a material having a smaller electron work function and, in the case of a circuit of P channel transistors, from a material having a greater electron work function than the gate electrodes of said first transistor, said auxiliary second transistor and said fourth transistor.

7. An improved integrable circuit according to claim 6 wherein all gate electrodes are made of silicon and wherein said gate electrodes are doped with the same conductivity type as the associated source and drain zones, and that said gate electrode of said first transistor in the case of circuits employing P channel transistors, as well as in the case of circuits employing N channel transistors, is more strongly doped than the gate electrodes of the remaining transistors of the same channel type.

8. An improved integrable circuit according to claim 7 wherein the source zone of the auxiliary second transistor and the zone of the same conductivity type of said first diode are arranged at the surface of a common semiconductor body.

9. An integrable circuit according to claim 8 wherein the source zone of said auxiliary second transistor is combined with the zone of the same conductivity type of sAid first diode to form one zone.

10. An improved integrable circuit according to claim 8 wherein the source zone of said auxiliary transistor is contacted with a layer designed partly as the gate electrode of said controlled first transistor and partly as the electrode of a coupling capacitor arranged prior to the gate electrode of said controlled transistor.