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Número de publicaciónUS3838395 A
Tipo de publicaciónConcesión
Fecha de publicación24 Sep 1974
Fecha de presentación4 Dic 1972
Fecha de prioridad4 Dic 1972
Número de publicaciónUS 3838395 A, US 3838395A, US-A-3838395, US3838395 A, US3838395A
InventoresJ Holt, R Ray, F Suttill
Cesionario originalCommplex Inc
Exportar citaBiBTeX, EndNote, RefMan
Enlaces externos: USPTO, Cesión de USPTO, Espacenet
Electronic variable combination lock and monitoring system
US 3838395 A
Resumen
A variable combination electronic lock is provided in which the combination may be varied electronically. The lock is provided with means for receiving a key having a combination. The combination of the key is detected and the detected combination is checked or compared with the combination assigned to the lock. If the combination on the inserted key is identical to the assigned combination, a lock release means of the lock is enabled. In one preferred use, a plurality of locks is provided with each lock being assigned an address. All of the locks may be connected to an electronic processor by means of a single system cable. The electronic processor stores a combination for each of the locks. Each of the plurality of locks is addressed in sequence, and the combination of the key, if any, inserted into the key receiving means of the lock is transmitted to the electronic processor for comparison with the combination stored. In addition, other information indicative of predetermined conditions at the location of each lock, such as the existence of excessive heat due to a fire, may be transmitted to the electronic processor. If the combination transmitted to the electronic processor from a particular location agrees with the stored combination, a lock enable signal is transmitted over the system cable with the address of the particular lock thereby enabling or opening that lock.
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Descripción  (El texto procesado por OCR puede contener errores)

nited States Patent Suttill, J r. et al.

[ Sept. 24, 1974 ELECTRONIC VARIABLE COMBINATION LOCK AND MONITORING SYSTEM Assignee: Commplex, Inc., Philadelphia, Pa.

Filed: Dec. 4, 1972 Appl. No.: 312,067

US. or. 340/149 A, 340/149 R 1111. c1. Il04q 5/16 Field of Search 340/149 A, 147 R, 274

References Cited UNITED STATES PATENTS 11/1971 Lehrer 340/147 R 12/1971 Daniel 340/227 X 5/1973 Hedin 340/149 A 6/1973 Poylo 340/149 A Primary ExaminerI-Iarold l. Pitts Attorney, Agent, or FirmStuart E. Beck [57] ABSTRACT A variable combination electronic lock is provided in which the combination may be varied electronically. The lock is provided with means for receiving a key having a combination. The combination of the key is detected and the detected combination is checked or compared with the combination assigned to the lock. If the combination on the inserted key is identical to the assigned combination, a lock release means of the lock is enabled. In one preferred use, a plurality of locks is provided with each lock being assigned an address. All of the locks may be connected to an electronic processor by means of a single system cable. The electronic processor stores a combination for each of the locks. Each of the plurality of locks is addressed in sequence, and the combination of the key, if any, inserted into the key receiving means of the lock is transmitted to the electronic processor for comparison with the combination stored. In addition, other information indicative of predetermined conditions at the location of each lock, such as the existence of excessive heat due to a fire, may be transmitted to the electronic processor. If the combination transmitted to the electronic processor from a particular location agrees with the stored combination, a lock enable signal is transmitted over the system cable with the address of the particular lock thereby enabling or opening that lock.

26 Claims, 11 Drawing Figures TAPE I4 22 2 UNIT f f l 24 L L I IV I l CENTRAL PRINTER PROCESSOR 1o i |F1RE ENTRY. l8

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- F6. 4 FIG. 6 FIG.

FROM/ TO CENTRAL PROCESSOR IO 0 3 E E 5 x a E 3 L n: 5' U Z 3 m O u m U 2 :1 U r- 5 t m I! 5 O t E v 34 z E s g m g 3 E M L) a 5 F1 E E E g a u n: 0: lo t ('71 l! T 1} 4| l6 24 L4 I62 I66 MESSAGE DATA REGISTER 7% (R5) |5o l I & v

TRANSMIT (OUTPUT) DATA TO SYSTEM CABLE 24 m- "'1 F! MESSAGE START I ETECTORI SYNC DECODE ADDRESS DECODE I CNT 3 3.888.395 SHEET SW 8 4 84 I00 88 98 H2 90 O 958 UNITS UNITS 3 COUNTER DECODE? C2 0 8 TENS TENS 2 COUNTER DECODE5 C 3 D 2 F CNTSB C CNT59 IIEIIIIIISEPM 3.8384395 SIEEI 7 0f 8 ROOM I32 I34 READY FIRE DETECTOR IIIIIII IIIIIIIIIIII R3 DATA --I-I J- KEY COMBINATION ISYNcI CODE I38 G26 3 F* ""'"-I 24 I46 88 I IET l I 627 1 -F9 I I42 8 i I I |4)8 MODULATION SIGNAL I L'EE' L EE Q J I494 I36 PMEMEDSEPMQM 3,838.39? SIR! 80$ 8 FIG. I0

CONTROL 4 Y ob ER DO OM I CE M 4 l I I I I I I I II l w COM ARATOR I Q A L V L l/ I I I I I I I I .II. Q L GHT DETECTOR L M 1 M 8 L GHT S R E m A H K LOCK SOLENOID ELECTRONIC VARIABLE COMBINATION LOCK AND MONITORING SYSTEM BACKGROUND OF THE INVENTION This invention relates to an electronic variable cornbination lock and monitoring system. More particularly, this invention relates to an electronic variable combination lock and monitoring system in which the combination of a plurality of locks located at various remote locations may be changed in a random fashion as desired. The present invention further provides a system for monitoring various predetermined conditions at various remote locations and the providing of data and control signals to the various remote locations.

Security is a pressing need which has been sought after and satisfied to limited varying degrees with various forms of intrusion prevention devices. The demand and need for economical security devices and systems has been increasing rapdily in modern society with the increasing rate of crime. The level of security today is most often limited by economics.

In the prior art, the more elaborate systems utilized combination locks backed-up with various alarm and timing release techniques. These systems are expensive and economically out of the reach of all but a few applications, these being mainly financial institutions such as banks and savings and loan associations.

In certain industries, especially in the hotel, motel and other industries where quarters or accommodations are rented or leased for relatively short periods of time, it is desirable to be able to change the combination of the lock mechanism to the room or other accommodation in a random manner after termination of a transaction such as the renting of a room for a night. For example, there is a problem in the motel industry with patrons either leaving with the key or losing the key. The patron or the finder of the key may then return at a later time and remove various articles of property from the room. It is therefore desirable to be able to change the combination of the lock mechanism to the particular room whenever a key is lost or missing. In addition, a person having ill motives may purposely have an additional key made during the period of time in which he has legal access to the room under the rental. This person may then return at a later time to remove items of property from the room. Therefore, it is desirable, as a routine matter, to be able to randomly change the combination of the lock mechanism of each room after the termination of each rental period.

SUMMARY OF THE INVENTION The electronic security and monitoring system in accordance with the present invention offers an increased hicles. Of course, the capacity of the system for home.

and automotive vehicle use is only a small fraction of that required for other uses thereby making it economically feasible for such uses. For example, the capacity of memories and address registers may be substantially reduced. Furthermore, in certain applications. an address register may not even be required.

Briefly, in accordance with the present invention, apparatus is provided for providing a variable combination lock function. A lock means is provided having a means for receiving a key provided with a combination. The key receiving means is provided with means for detecting the combination of a key inserted into the key receiving means. The lock means includes a lock release means which operates to release the lock in re sponse to a lock enable signal. The lock means is connected to an electronic processor which is capable of storing a combination for the lock. In addition. the electronic processor is provided with means for changing the stored combination. The electronic processor generates the lock enable signal in response to the combination detected by the detector means in the lock means being identical to the combination stored in the electronic processors memory or storage.

In another embodiment, an electronic system is provided having a plurality of lock means. Each of the lock means is connected to a system cable which provides interconnection between each of the lock means and an electronic processor. Each of the lock means is provided with a means for detecting a predetermined address signal. In addition, each of the lock means is pro vided with means for receiving a key having a combination. The key receiving means includes means for detecting the combination of the key inserted into the key receiving means and means for transmitting the detected combination of an inserted key over the cable in response to the address detecting means detecting the predetermined address of that particular lock means. The electronic processor is provided with means for storing the combination of each of the plurality of lock means and means for changing the stored combination for each of the plurality of lock means. The electronic processor generates a lock enable signal in response to the combination transmitted by the addressed lock means and the combination stored in the electronic processor for that lock means being identical. The lock enable signal generated by the electronic processor is received by the addressed lock means and operates a lock release means. In addition, the lock means may be provided with means for transmitting data indicative of predetermined conditions at the location of the lock means.

BRIEF DESCRIPTION OF THE DRAWINGS For the purpose of illustrating the invention, there are shown in the drawings forms which are presently preferred; it being understood, however, that this invention is not limited to the precise arrangements and instrumentalities shown.

FIG. 1 is a schematic block diagram of the system in accordance with the present invention.

FIG. 2 is a drawing of the message formats used in accordance with the present invention.

FIG. 3 is a schematic diagram, partially in block diagram form, showing in greater detail a system in accordance with the present invention.

FIG. 4 is a drawing showing the arrangement for viewing FIGS. 5-8.

FIGS. 5-8 are schematic drawings, partially in block diagram form, of the electronics of each lock unit in accordance with the present invention.

FIG. 9 is a schematic diagram, partially in block diagram form, of an interface means between the system cable and the central processor in accordance with the present invention.

FIG. 10 is a schematic diagram, partially in block diagram form, of another embodiment in accordance with the present invention.

FIG. 11 is a schematic diagram of a circuit used in practicing a preferred embodiment of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the drawings in detail, wherein like numerals indicate like elements, there is shown in FIG. 1 a central processor or electronic processor 10. Central processor or electronic processor 10 may be a general purpose digital computer commercially available on the market. That is, central processor 10 may be any suitable general purpose type processor which is programable and contains a memory. Central processor 10 may be any one of numerous commercially available electronic processors. Central processor 10 may be a mini computer although the complexity of a mini computer is not required for proper operation of the system. An example of a commercially available mini computer or mini processor which is suitable for use in accordance with the present invention is the PDP-8 mini processor manufactured by Digital Equipment Corporation of Boston, Massachusetts.

The central processor is provided with an entry terminal 12 which may be a keyboard or other suitable means for a person or operator to communicate with the central processor. The central processor 10 is connected to a tape unit 14 which performs the function of a permanent memory. That is, information, such as lock combinations, may be stored on magnetic tape in addition to being stored within the central processor. This storage on magnetic tape of the lock combinations insures against loss of the combinations in the case of a power failure.

The central processor 10 also feeds a printer 16 for providing a hard copy read-out of various data. The central processor 10 may also be coupled to a telephone line coupler 18 which enables communication with the central processor from a remote location. The central processor 10 also feeds a display unit 20 which enables the display of certain alarms and other information and provides an indication of the particular room or lock unit at which the alarm condition occurred.

The central processor 10 may be connected to a plurality of lock units 22 via a single system cable or other suitable single channel communication system 24. For example, the system cable 24 may be a single twisted pair cable, a coaxial cable, or its equivalent of a single channel frequency communication system. A single twisted pair cable is preferred since it is more economical than either a coaxial cable or radio communication system and is also less subject to radio frequency interference than a radio communication system. However, the present invention is not limited to a single channel communication system and a multi-channel communication system or a multi-conductor cable may be used to communicate between the lock units 22 and the central processor 10.

In a preferred embodiment of the present invention, the system of the present invention may be used to monitor certain predetermined conditions at each of the lock units. For example, where the invention is used in the hotel and motel industry, each lock unit may be provided with means for receiving data indicative of whether the maid has prepared the room for a new guest, whether the television (t.v.) has been removed or whether the t.v. plug has been removed from the wall electrical outlet, whether the temperature has risen to such an extent in the room as to indicate a tire condition or other similar conditions. The means for monitoring various conditions at each of the lock units 22 will be discussed more fully hereinafter.

Referring now to FIG. 2, there is shown the message format for a preferred embodiment of th present invention. Shown at A is the central processors interrogate message. The central processor interrogate message is comprised of a sync or synchronization code, a lock address code, an interrogate/data (I/D) bit indicating whether the message is an interrogate or data message, a number of blank bit positions which contain the lock enable code on the central processor data message shown at C, data bits, parity and a selected number of blanks. The number of bit positions in each part of the message is indicated below the respective part. However, the number of bit positions in each part as indicated in FIG. 2 is for the purpose of illustrating a specific example and are not intended to be limiting. The number of data bits in any particular part of the message or the whole message may, of course, vary depending upon the particular application. For example, one two, or more than three bits may be used to provide a suitable sync code for the central processor interrogate message. Similarly, the number of bit positions in the lock address code part of the message is primarily determined by the maximum number of lock units 22 to be addressed.

As a specific example of a central processor interrogate message, assume that the sync code contains six data bits in three bit positions, i.e., the bits being at twice the pulse rate of all of the other data. As a specific example, the sync code may be comprised of five half bit position ones and one half bit position zero making up three full or normal sync bit positions as shown in FIG. 2A. The lock address code contains 10 data ones and the I/D bit contains a data zero. The next three bits of the central processor interrogate message will contain data zeros and the next 10 bits which correspond to data will contain ones and zeros depending upon the information being transmitted. The parity bit will be either a one or a zero" to provide odd parity. For a central processor interrogate message as described, the central processor 10 would address lock unit 22 having an address of 1024. The digital zero" in the I/D position indicates that this communication from the central processor is an interrogate message.

In response to the central processor interrogate message, lock unit 22 having an address of 1024 generates a lock reply message shown at B in FIG. 2. The lock reply message shown at B in FIG. 2 may be comprised of two sync bits, 12 key code combination bits, three key insert code bits which indicate that a key has been inserted, ten data bits, a parity bit and two blank bit positions. For the purposes of illustration, it will be assumed that the sync code in a lock reply message contains two data ones. The key code combination will depend upon the key inserted into lock unit 22 having an address of 1024, if a key is inserted in the lock unit. The three bit key insert code will contain a digital 101 code if a key is inserted. The data bits will depend upon the conditions being monitored at the lock unit addressed.

Assuming that the key was inserted into the addressed lock unit 22 and that the key code combination transmitted by the lock unit 22 agreed with the combination stored in the central processor, the central processor transmits via system cable 24 a central processor data message as shown at C in FIG. 2. The central processor data message would contain three digital ones" as the sync code. Since the central processor would be addressing the same lock unit 22 previously addressed, the lock address code would contain digital ones in order to address lock 1024. The I/D bit position would contain a digital one in order to indicate to the the lock unit that this was a data message as contrasted to an interrogate message. The lock enable code would contain a digital 101 in order to enable the lock release mechanism in lock unit 22 having an address of 1024. The data bits may contain various "ones and zeros depending upon the information desired to be transmitted to the addressed lock unit 22. In the foregoing example, particular sync codes, I/D codes, key insert codes and lock enable codes have been illustrated in order to provide a concrete example. However, it is understood that various other code combinations and various other numbers of bits may be used in practicing the present invention.

There is shown at 26 in FIG. 2 a typical sequence of central processor interrogate messages A, lock reply messages B and central processor data messages C wherein a key has been inserted in the lock units 22 having addresses of three and five. That is, as shown at 26 in FIG. 2, a central processor interrogate message indicated as A1 is sent to lock unit 22 having an address of one. The lock unit 22 having an address one sends a lock reply message indicated as B1 to the central processor. A similar series of messages occurs on the system cable 24 for the lock unit 22 having an address of two. When lock unit 22 having an address of three is addressed by the central processor interrogate message indicated as A3, a lock unit 22 replies with the lock reply message B3. It is assumed that the lock reply message B3 indicates to the central processor that a key is inserted in the lock unit by means of a proper key insert code and the central processor determines that the key code combination sent by the lock unit corresponds to that stored in the memory of the central processor, data message C3 will contain a lock enable code. In a similar manner, all of the lock units 22 connected to the central processor via system cable 24 will be addressed in sequence. After each lock unit 22 is addressed, the cycle will be started over addressing each of the lock units 22 in sequence. In order to operate on an effectively real time basis, each of the lock units 22 in the system should be addressed at least twice each second.

Referring now to FIG. 3, there is shown a central processor or electronic processor 10 having a memory or a storage means 28. The memory 28 may be any suitable commercially available random access memory.

Memory 28 contains the code combination for each of the lock units 22 under the address of each lock unit. The code combination for each of the lock units 22 may be generated manually by means of keyboard input 12 or it may be generated by a random number generator 30 in response to a particular memory location, corresponding to a particular lock unit 22, being addressed by means ofa keyboard input 12. That is. the person operating the central processor may insert a particular code for a particular lock unit 22 or he may simply address a particular lock unit and random number generator 30 will generate a code or combination for the lock unit addressed. Addresser 32 provides address signals which sequentially address each of the lock units 22 in the system via input/output interface unit 34 and system cable 24. Addresser 32 also provides address information in order to address the proper location of memory 28. Central processor 10 receives and supplies control signals via lines 36 and receives and supplies data via lines 38.

The information transmitted over system cable 24 is amplified by the line transmit and receive amplifiers 40. That is, the receive amplifiers in line transmit and receive amplifiers amplify the incoming central processor interrogate message and central processor data message. The transmit amplifiers in the line transmit and receive amplifiers 40 amplify the lock reply message before it is sent over the system cable 24 to input- /output interface 34.

The received data is applied to control electronics 42. The control electronics 42 will be described in greater detail with reference to FIGS. 5-8 hereinafter. Basically, the control electronics checks whether this particular lock unit 22 is being addressed. If this particular lock unit is being addressed, the light sources 44 are energized via line 46. When the light sources 44 are energized, if no key 48 is inserted in key receiving means 50, the proper key inserted code will not be transmitted to the central processor 10 by control electronics 42 via line transmit and receive amplifiers 40, system cable 24 and input/output interface 34. If when light sources 44 are energized a key 48 is present in key receiving means 50, a proper key inserted code and the combination of the key will be transmitted to central processor 10 by control electronics 42. The key 48 may have transparent areas as indicated at 52 on key 48. These transparent areas may be notches cut into the edge of the key as in conventional tumbler lock keys. Alternatively, the keys may have holes bored in them at particular locations to set a particular combination into the key. The key may be made of any suitable rigid plastic or metallic material. Alternatively, the keys may be made by inserting transparent material in predetermined areas of the key body. Such transparent materials may be transparent plastics or glass.

If the combination of the key transmitted by the control electronics 42 to central processor 10 is identical to the combination stored in memory 28 of central process 10 for the lock unit 22 addressed, comparator 54 will generate an output signal or a lock enable signal. The lock enable signal is transmitted via input/output interface unit 34, system cable 24 and line transmit and receive amplifiers 40 to control electronics 42. In response to the lock enable signal, control electronics 42 energizes lock enable solenoid 56. The energization of lock enable solenoid releases lock mechanism 58 thereby enabling access to the controlled area or room.

Referring now to FIG. 4, there is shown a diagram indicating the manner in which the schematic drawings of FIGS. 5-8 may be placed in order to enable an easier understanding of the subject matter. However, it is not necessary to place the drawings in this arrangement since all interconnecting lines in different Figures are numbered identically.

Prior to a detailed description of the circuitry shown in FIGS. 5-8, reference may be had to FIG. 11 for the purpose of describing the function of the schematic symbols used in the circuitry. Referring now to FIG. 11, there is shown the symbol of an amplifier at 60. An inverting amplifier is shown at 62. Generally, a small circle on the input or output lead of a schematic symbol indicates an inverting function. An AND gate is shown at 64. A NAND gate or in other words an AND gate with an inverted output is shown at 66. The symbol shown at 68 represents an OR gate. The symbol shown at 70 represents an EXCLUSIVE OR gate. All of these gating functions and numerous ways of implementing the gating functions and amplifying functions are well known and conventional in the art and for the purposes of clarity will not be discussed in further detail here.

The symbol shown at 72 represents a flip-flop having a clock pulse input represented by CP and a D input represented by a D. The P input is a preset input in which a low level input on line 74 sets the Q output on line 76 to a one or a high level. The C input is a clear input for which a low level on line 78 resets the Q output to a low level or a zero output. The 6 output is a signal output which is always inverted or opposite to that of the Q output. Generally, a line or a bar over a symbol represents an inverted signal. Although this flip-flop technology is conventional and well known, it is reviewed herein for the purposes of clarity and concreteness.

The most common type of flip-flop operation, which is the Q output changing its level for each input pulse on the clock pulse CP input, may be achieved by wiring the 6 output to the D input. Also, by wiring the Q output to the preset P input, a pulse on the clock pulse CP input will set the flip-flop making the Q input high with this Q input remaining high until the flip-flop is cleared by an input on the clear terminal C or line 78. Further, without any of the additional connections, a high or low signal appearing on the D input appears at the Q output upon the occurrence of the next input pulse on the clock pulse input CP. Without any inputs on the CP and D inputs, the flip-flop output on the output will remain high once set by an input oh the preset terminal P until the flip-flop is cleared by an input on the clear terminal C. This flip-flop circuitry is conventional and well known and is being described herein only for the purpose of concreteness Of course, other suitable equivalent circuitry may be used herein.

Referring now to FIGS. -8. the particularly FIG. 5, there is shown an amplifier Al for amplifying signals received from system cable 24. The output of amplifier A1 is fed to one input of AND gate G1 and is also fed to the D input of flip-flop F1 in the message start detector circuitry. The clock pulse input CP of flip-flop F1 is fed with clock pulses from clock circuit 80. Referring back to the message sequence shown in FIG. 2 in conjunction with the operation of circuitry shown in FIGS. 5-8, it is seen that the end of the last message sent,

whether A, B, or C, contains two blanks or digital 2eros." Therefore, the message start detector flip-flop F1 is in a reset state or in other words the Q output is low or zero. At the beginning of the next message sequence which is the central processor interrogate message A, the first bits received are the sync bits. As discussed above, there are, in the specific example being illustrated, two sync bits in every normal bit position of the sync code. Thus there are six bits in the three sync code bit positions with the first five of these being digital ones. When these digital ones are applied to the D input, flip-flop F1 is set upon the occurrence of the next clock pulse from clock circuit 80. Clock circuit may be a conventional clock circuit having a frequency. by way of example, of one megahertz. When the 0 output of flip-flop F1 goes high in response to flip-flop Fl being set, an enable signal is applied to AND gate G1 which gates the received central processor interrogate message into receive register R1 in response to shift pulses on line 82. The shift pulses on line 82 shift the data in receive data register or shift register R1 one position to the right as each information pulse is received from gate G1.

The output of clock circuit 80 is also supplied to clock counter C1 in FIG. 6 via line 84. Clock counter C1 provides two outputs. The first output is designated CP and is obtained by dividing the output of clock circuit 80 by 16. The second output is at twice the frequence of the first output and is designated two CP and appears on line 86. The clock frequency CP is supplied via line 88 to units counter C2 and gate G24 in FIG. 6, gates G32 and G3 in FIG. 5, and gates G26 and G27 in FIG. 8. Units counter C2 provides count output signals to units decode unit D1. In addition, units counter C2 functions as a divide by ten counter supplying tens counter C3 with a pulse for every 10 input clock pulses CP. The 10s counter C3 supplies count outputs to the l0s decode unit D2. The counters and decode units are conventional and well known and will not be discussed in detail herein. Basically, the units decode provides an output pulse in sequence on each of its outputs zero through nine for each 10 input clock pulses CP. Similarly, the 10s decode unit D2 provides an output pulse in sequence on each of its outputs zero-five for each 10 input clock pulses CP.

The outputs of the units decode unit D1 and the tens decode unit D2 are supplied to gates Gl2-Gl6, Gl8G23, G25 and G37 in order to provide timing pulse signals at the various counts as indicated on the outputs of each of these gates. It is believed unnecessary to trace out each of the input lines to these various gates. However, it may be noted with respect to gate G13 that gate G13 receives an input from the eight output of units decode unit D1 and an input from the output of the two output of the tens decode unit D2 in order to produce a signal on its output at the count of twenty-eight. It may also be noted that the output of gate G13 is inverted and therefore the output of this particular gate is indicated as CNT28. The remainder of the gates operate in a similar manner. However, gates G16, G18 and G19 also receive inputs from the interrogate/data (I/D) flip-flop F3 which stores the I/D bit when it is received. Gates G16 and G18 receive an input from the Q output of flip-flop F3. Therefore, gates G16 and G18 produce outputs on the counts of 29 and 30, respectively, only if flip-flop F3 has been set. Gate G19 receives one of its inputs from the 6 output of flip-flop F3 and therefore gate G19 produces an output only if flip-flop F3 has not been set, or in other words, the I/D bit is a digital zero.

Referring now back to the loading in of the three sync bits as shown in FIG. 2 into the shift register R1, it may be noted that biphase modulation may be used in a preferred embodiment to transmit the information messages over the system cable 24. Biphase modulation is a well known and conventional form of modulation. Biphase modulation is a preferred method of transmitting the information over system cable 24 since it provides synchronization advantages and it reduces the band width required for transmitting data over the sys tem cable 24. As seen from the sync code in FIG. 2, there are three bits of information making up the sync code. At the normal clock frequency CP, the data bits are sampled in the last half of the bit interval or position. The clock rate of two CP samples the data in the first and last half of bit interval of each sync bit. This results in six samples for the three sync bits, that is, two samples per bit and three bits. Instead of storing the sync code in shift register R1 as a 110 sequence as would be the case for the normal clock rate CP, it is stored as 11 11 10. Sampling the sync bits in this manner guarantees that data bits will not be mistaken for sync bits.

The 11 11 10 sinc signal is shifted into shift register R1 during the first three counts at a clock frequency rate of two CP. As discussed above, the clock pulses at I the rate of two CP are applied to the shift control of shift register R1 via line 88. The clock pulses two CP are gated to line 82 by AND gate G2 via OR gate G4. Gate G2 receives the clock pulses 2 CP via input line 86 from clock counter C1. AND gate G2 is controlled by the Q output of flip-flop F4 via line 90. Flip-flop F4 is set by the output of flip-flop Fl at the beginning of the message via line 92. As may be recalled, flip-flop F1 is set immediately at the beginning of the message. Flipflop F4 is reset by the output of gate G14 at the count of three. Therefore, gate G2 in FIG. 5 gates clock pulses 2 CP from the beginning of the message through count three.

The sync code stored in shift register R1 is checked for the proper sync code by sync decode gate G6-and gate G5 at the count of three. The count of three is supplied to the input of gate G5 via lines 94, inverting amplifier 96 and line 98. lnverting amplifier 96 is provided since the output of gage G14 is an inverted output. Since the output of gage G3 is inverted, a proper sync code produces a low output to gage G5 at the count of three. If the sync code is improper, the output of gage G6 is high at the count of three. If the sync code is improper at the count of three, gate G5 produces an output pulse which clears flip-flop Fl through OR gate G7.

If flip-flop F1 is cleared or reset, the 0 output of F1 goes low causing flip-flop F2 to be cleared via line 92. The low signal on line 92 also clears flip-flops F3 and F4 in FIG. 6 and removes an enabling signal from gate G36 in FIG. 7. In addition, the Q output of flip-flop F1 going high clears clock counter C2, units counter C2 and IOs counter C3 via line 100.

Assuming that the proper sync code has been stored in shift register R1 and detected, the shift pulses on line 82 are changed from a clock rate of 2 CF to CF by the turning off of gate G2 and the turning on of gate G3. Gate G3 receives the clock pulse input CP via line 88 from clock counter C1. Gate G3 is enabled by the Q output of flip-flop F5 via line 102. Flip-flop F5 is set by the output of gate G14 at the count of three. Flip-flop F5 is reset or cleared at the count of 28 by the output of G13. The clock pulses gated by gate G3 from clock counter C1 are applied to the shift control of shift register R1 via gate G4 and line 82 during the period between count three and count 28.

The output signal of gate 13 at count twenty-eight is applied via line 104 and inverting amplifier 106 to gate G11 in the parity check circuit 108. Parity check circuit 108 receives the input signal as amplified at the output of amplifier A1, clock pulses via line 88 and the output of flipflop F5 via line 102. The output of gate G32 triggers flip-flop F2 for each digital one appearing on the output of amplifier A1. If the 6 output is a digital one" or a high level at the count of 28, gate G11 produces an output which resets flip-flop F1 ending the message input processing since this indicates an improper polarity. In other words, the 6 output of flipflop F2 must be in a low state at count 28 if the incoming signal has proper parity. As discussed above, the resetting of flip-flop F1 clears counters C1, C2 and C3 and other key circuits enabling the lock unit for the receipt of another message.

At the count of 13, the contents of shift register R1 is checked for the proper address by address decode gates G8 and G9 and AND gate G10. As may be seen from FIG. 5, address decode gates G8 and G9 check for the proper address code. The specific example illustrated in FIG. 5 checks for an address of 1024. That is, all of the inputs of gates G8 and G9 must be provided with a one input to produce a zero output on the output line of gate G9. The output of gate G9 is gated by gate G10 at a count of 13. If the address is improper, the output of gate G9 will be high at the count of 13 thereby causing G10 to produce an output pulse which resets flip-flop F1 via NOR gate G7. Gate G10 receives its count of thirteen signal from the output of gate G12 via line 110.

At the count of 29 with the I/D bit stored in flip-flop F3 being zero, which indicates that the message being received is a central processor interrogate message A, the bits of information stored in shift register R1 are transferred to shift register R2, the light sources in the key sensor assembly are energized, and the combination of any key inserted into the key sensor assembly is stored in shift register R3. At the count of 27, the interrogate/data (I/D) bit present on line 112 was stored in flip-flop F3 in response to the output of gate G15 via line 114. Flip-flop F3 had been previously cleared at the count of three. On the central processor interrogate message, the l/D bit was a digital zero. Therefore, at the count of 29, gate G19 produces an output at the count of 29 with I/D equal to zero. The output of gate G19 is applied to the store terminals of shift register R2 and R3 and to the clock terminal CP of flip-flop F10 via line 116. The data stored in shift register R2 may be used to control various display devices located at the particular lock unit 22. For example, a one bit in the first bit position may be used to energize a wake-up alarm 118. Various other types of similar devices may be controlled at each lock unit from input information entered at the central processor 10 via the keyboard entry terminal 12.

The output of gate G19 on line 116 is also applied to the CP input of flip-flop F10. If a key 48 is inserted into the key receiving means or key sensor assembly 50, the output of light emitting diode 118 is blocked causing the output of photosensitive transistor 120 to go high. The high or digital one output of photosensitive transistor 120 supplies a digital one to the D input of flipflop F which is clocked by the output of gate G19 on the clock pulse input CP of flip-flop F10. The high signal on the Q output of F10 enables transistors Q1 and O2 which energize the 12 light emitting diodes 122. Depending upon the transparent areas or in other words the combination of the key 48, particular ons of the 12 photosensitive transistors 124 will be eradiated producing an output signal. Although a specific example of a preferred embodiment has been described, it is understood that various other suitable light sources and photodetector elements may be used in practicing the present invention. In addition, various other suitable types of means for sensing the combination of a key may be utilized.

The output of gate G19 via line 116 also gates information including the key combination information into shift register R3. The detection of a key 48 inserted into key receiving means or key sensor assembly 50 causes a key insert code to be stored in shift register R3 via line 126 and inverting amplifier 128. That is, a 101 key insert code is generated when the output of photosensitive transistor 120 becomes high in response to a key inserted in key receiving means 50. It is understood that any other suitable key insert code may be used in practicing the present invention. However, the 101 key insert code has been selected as one illustrative embodiment. The combination of key 48 sensed by photosensitive transistors 124 is stored in register R3 by 12 lines indicated schematically as line 130. In addition, the first two bit positions of shift register R3 are tied to a positive potential in order to generate the two sync bits of the lock reply message B.

In addition, data information as to certain predetermined conditions at the location of the particular lock unit addressed may be entered into shift register R3. For example, a switch 132 may be provided which may be operated by a maid or other person responsible for preparing the room for a new guest after the room has been prepared for the new guest. That is, as an example, the maid may close the switch after she has cleaned the room in order to indicate that the room has been prepared for a new guest. Similarly, a fire detector unit 134 may be connected between a positive supply potential and one of the shift register data inputs in order to provide an indication to printer 16 and display unit 20 via the central processor 10 where the room temperature has risen to such an extent that it indicates a fire in the general vicinity of the fire detector 134. That is, when fire detector 134 senses a temperature in excess of a predetermined temperature, fire detector 134 closes a switch connecting the positive potential 8+ to the particular bit position.

Starting at the count of 30, the information stored in shift register R3 is serially stepped out of shift register R3 and transmitted over the system cable 24 along with a parity bit generated by a parity generator 136. At the count of 30, flip-flop F6 on FIG. 6 is preset by the output of gate G20. The digital one signal on the Q output of flip-flop F6 is supplied as an enabling signal to gates G26 and G28 on FIG. 8 via lines 138. Gate G26 receives clock pulses from clock counter C1 via line 88. The enabling of gate G26 provides shift pulses to shift register R3 which causes the data bits stored in R3 to be serially shifted out of shift register R3 and applied to the inputs of gates G28 and G27 via line 140.

Gate G28 is enabled by the Q output of flip-flop F6 via line 138. The output of gate G28 is applied through OR gate G29 to one input of exclusive OR gate G31. The other input to gate G31 is a modulation signal received via line 142 from the output of gate G24. Gate G24 gates the clock signal output of clock counter C1 on line 88 in response to the output of flip-flop F7. Flipflop F7 is preset at the count of 31 and cleared at the count of 58. Therefore, flip-flop F7 provides an enabling signal to gate G24 from the count of 31 to the count of 58. The gating of the information stepped out of shift register R3 with the clock signal in exclusive OR gate G31 provides the biphase modulation. The output of exclusive OR gate G31 is amplified by transmit amplifier A2 before it is transmitted over the system cable 24.

Parity generator circuit 136 generates the parity bit at the end of the data shifted out of shift register R3. Gate G27 is enabled by the Q output of flip-flop F8 via line 144 when flip-flop F8 is preset by the ouutput of G25 at count 32. Gate 27 remains enabled until flipflop F8 is cleared by the output of gate G21 at the count of 57. The output of gate G27, in response to the data being shifted out of shift register R3, causes flipflop F9 to be toggled for each digital one" shifted out of shift register R3. The Q state of flip-flop F9 is gated to one input of exclusive OR-gate G31 via OR gate G29 by gate G30 in response to the 0 output of flip-flop F6 going low when flip-flop F6 is cleared at the count of 57 by gate G21. That is, when flip-flop F6 is cleared, the Q output of flip-flop F6 is supplied to one input of gate G30 via line 138 and inverting amplifier 146. The parity flip-flop F9 is cleared at the count of 59 by the output of gate G37 via line 148.

Referring now to FIG. 9, the lock reply message transmitted over system cable 24 from register R3 is received by input/output interface unit 34. The incoming signal is amplified by amplifier 150. The output of amplifier is applied to message data shift register R5 and to the D input of flip-flop 152. The first two bits of information transmitted over the system cable and amplified by amplifier 150 are the sync bits which may be a digital 11 10 signal in the full sync bit positions. That is, each sync bit position contains two sync bits. Upon the first clock pulse applied to the clock input CP of flip-flop 152 from the central processor 10, the 0 output of flip-flop 152 becomes a digital one. This indicates to central processor 10 that a reply message is being received from a lock unit. Since the O output of flip-flop 152 is connected to the preset input P of flipflop 152, flip-flop 152 remains set until a low input is applied to the clear terminal C. The lock reply message on the output of amplifier 150 is then clocked into shift register R5 by the data shift clock signal on line 154. Once the data shift clock pulses on line 154 cease, corresponding to the end of the lock reply message, the lock reply message is transferred into central processor 10 in parallel via twenty-eight parallel lines indicated schematically as line 156.

The central processor 10 receives the lock reply message and processes it. As discussed above, central processor 10 compares in comparator 54 the key combination received from the addressed lock unit 22 with the combination stored in memory 28 for the particular address. If the combination received from the lock address unit is identical to the stored combination for the lock unit addressed, the comparator produces a coincidence output pulse which in turn generates a lock enable signal. The lock enable signal may be a 101 code and may be generated in a manner identical to the generation of the key insert code in the lock electronics unit. In addition, the central processor may provide data information to input/output interface unit 34 in response to entries made at the keyboard entry terminal 12. This central processor data message information is transferred in parallel form into shift register R in response to a store signal appearing on line 158. After all of the information bits making up the central processor transmit data message C have been entered into shift register 5, a transmit command signal appears on line 160 from central processor 10. The transmit command signal on line 160 is a low signal which clears flip-flop 152 and enables gate 162 after being inverted by inverting amplifier 164. The information stored in shift register R5 is then serially stepped out of shift register R5 through gate 162 inresponse to data shift clock pulses appearing on line 154. This information on the output of gate 162 is amplified by amplifier 166 and transmitted over the system cable 24 to amplifier A1 of lock unit 22 as shown in FIG. 5.

The central processor data message received by lock unit 22 is processed in a similar manner to the central processor interrogate message A as described with reference to FIGS. 5-8 described above up to the count of 30. It may be noted that the central processor data message has a digital one in the I/D bit position. Therefore, at the count of 27 during the receiptof the central processor data message, the Q output of flipflop F3 is set to a one. Therefore, at the count of 29, gate G16 produces an output pulse which indicates a count of 29 with the I/D bit equal to a digital one. The output of gate G16 is applied to the store control of shift register R4 via line 168. The output of gate G16 applied to the store input control of shift register R4 causes the data stored in the shift register R1 to be transferred in parallel into shift register R4 via a plurality of parallel lines indicated as line 170.

The lock enable signal contained in bit positions 172-174 of register R4 is applied to gate G34 with the zero data bit contained in bit position 173 being inverted by inverting amplifier 176. The output of gate G34 is a digital one or a high level for a proper lock enable signal code with a key 48 inserted into key receiving means 50.

At the count of thirty with the I/D bit being equal to a digital one, the clock input C? of flip-flop F11 receives a digital one clock input signal from the output of gate G18 in FIG. 6 via line 178. In response to the inputs on the clock input CP and the input of flipflop F11, the Q output of F11 goes high. The Q output of F11 is amplified by amplifier A3 and applied to lock enable solenoid 56 which is thereby energized causing the release of lock mechanism 58. y

In addition, the signal on line 178, which may be referred to as an end of message signal, is applied to one of the inputs of NOR gate G7 which clears flip-flop F1. The clearing of flip-flop Fl clears various other circuitry in lock unit 22 placing the lock unit in condition for the receipt of the next message as discussed above.

Referring now to FIG. 10, there is shown another embodiment of the invention which is more streamlined economical version suitable for such uses as an automobile lock. That is, the embodiment shown in FIG. 10 may be readily adaptable for such uses as an automobile lock, especially where the automobile is rented or leased for periods of time. The embodiment of the invention as shown in FIG. 10 enables a rapid, convenient and economical changing of the key combination after each rental or lease.

Referring to FIG. 10, there is shown a random number select unit and a code set unit 182 for entering a new code or combination into code memory 184. These operations and the comparison operations would be controlled by the signals provided by control unit 186 In response to a key 48 being inserted between the light source 188 and the light detectors 190, a key inserted signal would be generated on line 192 which would cause the comparison of the key code combination detected by. the light detector and the code combination stored in memory 184 in comparator 194. In response to detecting an identical code between the output of the light detector 190 and the code combination stored in memory 184, comparator 194 generates a coincidence signal which is amplified by amplifier 196 to energize lock solenoid 198 to release a lock mechanism.

It will be apparent to those skilled in the art that various modifications may be made to the structure and operation of the electronic security and monitoring system within the spirit and teachings of the present invention. For example, various other types of circuits may be used to perform essentially the same function. In addition, various other means may be used for detecting the combination of the key. The signals within the system may be processed in various other manners and various other message code combinations may be used.

In view of the above, the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof and, accordingly, reference should be made to the appended claims, rather than to the foregoing specification as indicating the scope of the invention.

We claim:

1. An electronic security system for controlling access and monitoring a predetermined number of conditions at each of a plurality of controlled areas, each controlled area being provided with a door, comprismg:

a lock unit means being provided in each of said plurality of controlled areas, each lock unit means being connected to a system cable, each lock unit means being assigned a distinct predetermined address code and being provided with means for receiving address codes from said system cable, means for detecting its distinct predetermined address code, means for receiving a lock enable signal and data in response to the detection of its distinct address code by said address code detecting means, lock means for locking said door of the controlled area in which the lock unit means is located, said lock means being releasable in response to the lock enable signal, said data received in said receiving means being available for operative use in the controlled area in which the lock unit means is located, means for receiving a key provided with a combination, said key receiving means being provided with means for detecting the combination of a key inserted into said key receiving means, means for receiving controlled area data indicative of a predetermined number of conditions from operative devices located in the controlled area in which the lock unit is located, means for transmitting the detected combination of an inserted key, when a key is inserted, and controlled area data over said system cable in response to said address code detecting means detecting its predetermined address code; and

an electronic processor, means for interfacing said electronic processor with said system cable, means for generating the address code of each of said lock unit means, means for sending said address codes and data over said system cable via said interface means, said electronic processor being provided with means for storing the combination of each of said plurality of lock means and means for changing the combinations stored in said storage means, means for comparing the combination transmitted by an addressed lock means and the combination stored in said storage means for the lock means address, said comparator means being operative to generate the lock enable signal in response to the combinations being identical, and means for sending to said addressed lock unit means its address code, the lock enable signal and data via said interface means and said system cable.

2. An electronic security system in accordance with claim 1 wherein each of said key combination detector means includes a light source and a predetermined number of light detectors positioned to detect substantially transparent areas of a key inserted in said key receiving means.

3. An electronic security system in accordance with claim 1 wherein said means for changing the combination stored in said storage means includes a random number generator.

4. An electronic system, comprising:

a plurality of lock means, each of said lock means being connected to a system cable, each of said plurality of lock means being provided with means for detecting a predetermined address signal, means for receiving a key provided with a combination, said key receiving means being provided with means for detecting the combination of a key inserted into said key receiving means, means for transmitting the detected combination of an inserted key over said system cable in response to said address detecting means detecting the predetermined address signal, and lock release means operative in response to a lock enable signal; and

an electronic processor, means for interfacing said electronic processor with said system cable, said electronic processor being provided with means for storing the combination of each of said plurality of lock means and means for changing the combinations stored in said storage means, means for comparing the combination transmitted by an addressed lock means and the combination stored in said storage means for the lock means addressed, said comparator means being operative to generate the lock enable signal in response to the combinations being identical.

5. An electronic system in accordance with claim 4 wherein each of said plurality of lock means includes means for detecting a sync signal occuring at the beginning of each transmission from said electronic processor.

6. An electronic system in accordance with claim 4 wherein each said address detecting means of each of said plurality of lock means includes a storage means for temporarily storing signals transmitted over said system cable and gating means for detecting a predetermined address corresponding to the'particular lock means in which the address detecting means is located.

7. An electronic system in accordance with claim 4 wherein each said key combination detecting means of each of said plurality of lock means includes means for detecting the presence of a key.

8. Apparatus in accordance with claim 4 wherein each said key combination detecting means of each of said plurality of lock means includes a light source and a predetermined number of light detectors.

9. An electronic system in accordance with claim 4 wherein each said key combination detecting means of each of said plurality of lock means includes a predetermined number of light sources and a predetermined number of light detectors.

10. An electronic system in accordance with claim 4 wherein each said transmitting means of each of said plurality of lock means includes storage means for receiving the combination detected by said detecting means from said detecting means in parallel form and transmitting the combination on said system cable in serial form.

11. Apparatus in accordance with claim 4 wherein said interface means of said electronic processor includes a shift register, said shift register transferring combinations to said electronic processor and receiving information from said electronic processor in parallel form, said shift register transmitting information on and receiving combinations from said system cable in serial form.

12. Apparatus in accordance with claim 4 wherein said means for changing the combinations stored in said storage means includes a random number generator.

13. Apparatus, comprising:

means adapted to receive a digital signal containing a sync signal, address information and data, said sync signal occurring at the beginning of each transmission; means for detecting whether the address information corresponds to a predetermined address, said address detecting means including storage means for temporarily storing received signals and gating means for detecting the predetermined address;

means for receiving a key provided with a combination, said key receiving means being provided with means for detecting the presence of a key inserted into said key receiving means and means for detecting the combination of said inserted key;

means for providing the received data to operative devices;

means for receiving data indicative of conditions from operative means;

means adapted to transmit said detected key combination and the data indicative of conditions to a remote location;

said receive means adapted to recieve a digital signal including a lock enable signal from a remote location when said detecting means detects a predetermined combination; and

lock means, said lock means being provided with a lock release means responsive to the lock enable signal to release said lock means.

14. Apparatus in accordance with claim 13 wherein said means for detecting the combination of the inserted key includes a light source and a predetermined number of light detectors.

15. Apparatus in accordance with claim 13 wherein said key combination detecting means includes a predetermined number of light sources and a predetermined number of light detectors.

16. Apparatus in accordance with claim 13 wherein said means adapted to transmit said detected key combination and the data indicative of conditions to a remote location includes storage means for receiving the combination detected by said detecting means from said detecting means in parallel form and transmitting the combination and data indicative of conditions in serial form.

17. A system, comprising:

an electronic processor, a plurality of stations and a system cable connecting said electronic processor to each of said plurality of stations, each of said plurality of stations being provided with means for detecting a predetermined address signal sent over said system cable by said electronic processor, means for receiving a key provided with a combination, said key receiving means being provided with means for detecting the combination of a key inserted into said key receiving means, means for receiving data indicative of predetermined conditions at the station, means for transmitting the detected combination of the inserted key and the condition indicative data in serial form over said system cable to said electronic processor, lock means, said lock means including a lock release means operative in response to a lock enable signal received over said system cable from said electronic processor when the inserted key has the combination corresponding to the station addressed.

18. A system in accordance with claim 17 wherein each of said plurality of lock means includes means for detecting a sync signal occurring at the beginning of each transmission from said electronic processor.

19. A system in accordance with claim 17 wherein each said address detecting means of each of said plurality of lock means includes storage means for temporarily storing signals transmitted over said system cable and gating means for detecting a predetermined address corresponding to the particular lock means in which the address detecting means is located.

20. A system in accordance with claim 17 wherein each said key combination detecting means of each of said plurality of lock means includes means for detecting the presence of a key. 1

21. A system in accordance with claim 17 wherein each said key combination detecting means of each of said plurality of lock means includes a light source and a predetermined number of light detectors.

22. A system in accordance with claim 17 wherein each said key combination detecting means of each of said plurality of lock means includes a predetermined number of light sources and a predetermined number of light detectors.

23. A system in accordance with claim 17 wherein each said transmitting means of each of said plurality of lock means includes storage means for receiving the combination detected by said detecting means from said detecting means in parallel form and transmitting the combination on said system cable in serial form.

24. A system in accordance with claim 17 including an interface means for interfacing said electronic processor to said system cable, said electronic processor including a shift register, said shift register transferring combinations to said electronic processor and receiving information from said electronic processor in paral lel form, said shift register transmitting information on and receiving combinations from said system cable in serial form.

25. A system in accordance with claim 17 wherein each of said plurality of stations is a room and said means for receiving data indicative of predetermined conditions includes a switch, said switch having a first and second position, said switch in said first position being operative to indicate that the room has been prepared for new guests and said switch in said second position being operative to indicate that the room has not been prepared.

26. A system in accordance with claim 17 wherein each of said plurality of stations is a room and said means for receiving data indicative of predetermined conditions includes a fire detector, said fire detector being sensitive to heat, said fire detector providing an indication of fire in response to the temperature of the room exceeding a predetermined temperature.

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Clasificaciones
Clasificación de EE.UU.340/5.5
Clasificación internacionalE05B49/00, G07C9/00
Clasificación cooperativaG07C9/00904, G07C9/00571, E05B49/006, G07C9/00103
Clasificación europeaG07C9/00E7, G07C9/00B8, G07C9/00E20B, E05B49/00M4