US3895127A - Method of selectively depositing glass on semiconductor devices - Google Patents

Method of selectively depositing glass on semiconductor devices Download PDF

Info

Publication number
US3895127A
US3895127A US462492A US46249274A US3895127A US 3895127 A US3895127 A US 3895127A US 462492 A US462492 A US 462492A US 46249274 A US46249274 A US 46249274A US 3895127 A US3895127 A US 3895127A
Authority
US
United States
Prior art keywords
glass
insulating material
areas
coated
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US462492A
Inventor
Robert Benedict Comizzoli
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RCA Corp
Original Assignee
RCA Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by RCA Corp filed Critical RCA Corp
Priority to US462492A priority Critical patent/US3895127A/en
Priority to IN232/CAL/75A priority patent/IN143919B/en
Priority to SE7502450A priority patent/SE407427B/en
Priority to CA221,479A priority patent/CA1038329A/en
Priority to BR1730/75A priority patent/BR7501335A/en
Priority to FR7509253A priority patent/FR2268357B1/fr
Priority to JP50037392A priority patent/JPS5760773B2/ja
Priority to YU00771/75A priority patent/YU77175A/en
Priority to NL7503711A priority patent/NL7503711A/en
Priority to DE19752513945 priority patent/DE2513945A1/en
Priority to IT67867/75A priority patent/IT1044487B/en
Priority to GB1474375A priority patent/GB1464682A/en
Application granted granted Critical
Publication of US3895127A publication Critical patent/US3895127A/en
Priority to BE154554A priority patent/BE826941A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02142—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02142—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
    • H01L21/02145—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides the material containing aluminium, e.g. AlSiOx
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02142—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
    • H01L21/02161—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides the material containing more than one metal element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3178—Coating or filling in grooves made in the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Definitions

  • ABSTRACT A method which comprises depositing a charge of a selected polarity on the areas coated with insulating material of a semiconductor device having areas of bare semiconductor and areas coated with insulating material, immersing the charged device in a liquid composition comprising an insulating liquid and dispersed glass particles carrying a charge of selected polarity which is either the same as or opposite to the charge on the insulating material, such that glass particles deposit either on the semiconductor or on the insulating material, removing the glass-coated device from the liquid, drying and firing to fuse the glass particles on the device.
  • the glass which is used to passivate semiconductor devices must have a number of properties such as fusion temperature compatible with the semiconductor device, good adherence to the device surface, a temperature coefficient of expansion at least approximately matching that of the semiconductor, low porosity, and an absence of ingredients or contaminants that would adversely affect the electrical characteristics of the device.
  • a number ofdifferent methods have been used to deposit the glass particles.
  • One of these methods is doctor blading a glass powder slurry over the surface of a semiconductor wafer having many devices built into it by well known diffusion techniques, and then evaporating the liquid.
  • Another method is settling the glass particles out of a liquid dispersion onto the device surface.
  • the doctor blade method has several disadvantages. It usually is a hand operation requiring much labor and only one side of the wafer can be done at a time. Since it involves mechanical scraping, much wafer breakage and other damage results. In addition, the method achieves selectivity only through utilizing certain surface topography, i.e., it is limited to deposition in re Listed regions.
  • the settling method is time-consuming, wasteful of glass particles and is non-selective.
  • electrophoresis Another method which also has previously been used is electrophoresis.
  • the device poled either positive or negative
  • a current is passed through the dispersion.
  • Glass can be deposited selectively only on the conductive parts of the device surface.
  • another disadvantage of this method is that it is not satisfactory for depositing thick layers because of adherence problems.
  • the process uses conductive liquids which are capable of dissolving more contaminants than non-conductive liquids do, and therefore these liquids are more likely to be sources of device contamination.
  • the present method is an improved, electrostatic method of depositing a glass coating on selected areas of a device having areas of bare semiconductor and also areas coated with an insulating material.
  • the method comprises depositing charges of selected polarity on the areas coated with insulating material and then immersing the charged device in a liquid dispersion of glass particles which are charged either with the same polarity as or with polarity opposite to the charges on the insulating material.
  • the glass particles deposit either on the bare". uncoated areas or on the coated areas of the device depending upon polarity conditions chosen.
  • the device is then removed from the liquid and, after drying, the glass particles are fused by firing. Relatively thick, adherent coatings of glass can be applied in a selective manner.
  • FIG. I is a cross section view through part of a semi conductor wafer having many transistors separated from each other by grooves;
  • FIGS. 2, 3 and 4 illustrate successive steps in applying one embodiment of the method of the invention to the wafer of FIG. 1'
  • FIGS. 58 illustrate steps in applying an alternative embodiment of the method to a semiconductor device wafer
  • FIGS. 9-12 are section views of a different device and illustrate steps in coating the device by an embodiment of the methods of the invention.
  • FIG. 13 is an end view of suitable charging apparatus for use in the present method.
  • FIG. 14 is an elevation view of part of the apparatus of FIG. 13.
  • a slice 2 of a single crystal'semiconductor material such as silicon may have fabricated therein by well known diffusion techniques or a combination of epitaxial growth and diffusion techniques, many transistors 4.
  • Each transistor 4 has an emitter region 6 which may be of N conductivity type, for example, a base region 8 which may be ofP conductivity type, and a collector region 10, which may be of N conductivity type.
  • a layer I2 of an insulating material covers the top surface I4 of each transistor.
  • Another layer of insulating material 13 covers the bottom surface 15 of the slice.
  • the emitter region 6 and base region 8 are separated by a PN junction 16.
  • the base region 8 and the collector region 10 are separated by another PN junction 18.
  • Grooves 20 are provided in the form of a gridwork extending into the top surface 14 of the device array and below the PN junction 18 so that the grooves are on all 4 sides of each transistor 4. It is desirable to cover the exposed portions of the PN junctions with a dielectric material to reduce current leakage across the junctions and to prevent deterioration due to ambient or processing contaminants. It is much more economical to provide the necessary protective coating over the PN junctions while the devices 4 are still a part of the original slice 2 than. it is to treat each individual device after it has been separated from the slice.
  • the SIO2 covering the wafer (if this is the insulating material) is first patterned into the groove ge ometry using standard lithographic techniques. Then the silicon is etched using the SiO as the patterndefining mask. Because of etch undercutting. an overhanging shelf of SiO is formed. In depositing the glass by the method of the invention voids may be formed under the shelf which may lead to electrical degradation during further processing steps. Thus, it is advantageous to remove this overhanging Si before charging and glass deposition.
  • the removal may be accomplished in either of at least two ways.
  • An oxide etch may be used by immersing the wafer long enough to remove the overhang. In this case a fraction of the thickness of the oxide on the mesa surface is removed, but this is not harmful.
  • a 3 minute etch in buffered HF solution purchased from the Transene Corporation was sufficient to remove a 0.001 inch overhang while removing only about 3000 A. of the original l2,000 A. of SiO; on the mesa surface.
  • Another procedure is to use ultrasonic energy to remove the overhang.
  • a Branson Model 4l-4000 Ultrasonic Cleaner was used to re move the overhang in 30 seconds with water and with Freon TF in seconds.
  • the parts of the slice comprising bare" silicon which are exposed within the grooves are covered with a protective glass coating as follows.
  • the slice 2 is placed in a corona charging device which may consist of 2 parallel arrays of thin, vertically disposed wires held in an insulating frame.
  • the major surfaces of the slice should be carefully oriented so that they are parallel to the wire arrays.
  • the wires may be 1.5 mil diameter tungsten wires spaced 0.5 inch apart.
  • the distance between the parallel arrays is such that when the semiconductor slice 2 is positioned between them, the wires typically are spaced 0.220 inch from the adjacent surfaces of the slice.
  • the spacing of the wires from the surface to be charged can be used to vary the charge level on the slice, although it is usually desirable to charge the insulating region to saturation.
  • FIGS. 13 and 14 A satisfactory charging apparatus is shown in FIGS. 13 and 14.
  • the charging apparatus 58 may comprise a base plate 60 having disposed thereon two frames 62 and 64 which may be made of an insulating material such as methylmethacrylate resin.
  • the frames are accurately spaced on the base plate 60 so that they are facing each other.
  • Each of the frames 62 and 64 has a pedestal member 66 and 68 respectively, a panel 70 and 72, respectively, vertically mounted along one edge of the pedestal members 66 and 68, and a top plate 74 and 76, respectively, horizontally mounted on the tops of vertical panels 70 and 72 so that they extend parallel to the pedestal members 66 and 68.
  • each of the frames 62 and 64 is an array of wires 78 and 80, respectively.
  • Each array consists of 9 wires spaced equidistant from each other and held under tension in a vertical plane.
  • One end of each wire in the arrays is attached to one of the pedestal members 66 and 68 adjacent its outer edge.
  • the outer end of each of the wires in the arrays 78 and 80 is attached to one end of tension spring 86.
  • the other end of each tension spring 86 is attached to an adjusting screw 88.
  • the adjusting screws 88 are threadedly mounted in buss bars 92 and 94 which are set into plastic blocks 82 and 84, respectively, which extend longitudinally along the outer edges of top plates 74 and 76, respectively.
  • the wires in the arrays 78 and 80 pass over the outer edges of top plates 74 and 76, respectively.
  • the buss bars 92 and 94 are connected to a high voltage source (not shown).
  • the suspending means comprises four support posts 98, a pair of horizontal metal tracks and 102, disposed parallel to and above the top plates 74 and 76, having smooth, sloping inner surfaces 104 and 106, respectively, and a wafer holder 108 (FIG. 14).
  • the wafer holder 108 comprises a metal V-block 110 to the under side of which is fastened a pair of pivoted jaws 112 and 114.
  • the jaw 112 has a grooved finger 116 at its lower end and the jaw I I4 has similar spaced grooved fingers I18 and 120.
  • the fingers 116, 118 and 120 are arranged to receive and hold vertical the wafer 2.
  • the V-block 110 has smooth sides which slope at an angle which is the same as the angle of the sloping surfaces 104 and 106 of the tracks I00 and 102.
  • the V- block I I0 is thus designed to ride in the tracks I00 and 102 and to make electrical contact therewith.
  • the wafer holder is preferably moved back and forth along the tracks 100 and I02 at a speed of about 3 inches per second in order to charge the wafer surfaces uniformly.
  • a voltage of about 6200 volts negative is applied to the wires.
  • the atmosphere is air or nitrogen but the rel ative humidity is controlled so that it is about 30% at 25 C if silicon dioxide is the insulating material.
  • the charging voltage preferably should be as high as possible without causing arcing since this has been found to give better edge definition of charge on the slice 2 and also provides a more uniform charge.
  • the upper level of relative humidity permissible is a function of elapsed time between charging the surface of the slice and subsequent immersion in a glass dispersion. An elapsed time of one second has been used to advantage. If the time is very short, relative humidity may be higher since there will be less time for charge to leak away.
  • the wafer held in the wafer holder is thereby grounded by contact at the wafer edge and the slice is exposed to the corona discharge for about 5 to 15 seconds. As indicated in FIGS. 2, this causes a layer 22 of negatively charged gaseous ions to deposit on the insulating layer 12 which is on the top surface I4 of the device array and a similar layer of ions 24 to deposit on the insulating layer I3 disposed on the bottom surface 15 of the slice 2.
  • the sign of the discharge may be either negative or positive depending on whether the glass particles to be deposited have a negative or positive charge in the liquid and whether the glass is to be deposited on the insulator layers 12 and 13, or on the bare" exposed silicon.
  • the corona charge is negative.
  • the gaseous ions 22 and 24 from the corona discharge arrive at the surfaces of the slice 2 and deposit on the surfaces of the insulating layers 12 and 13 (FIG. 2).
  • the ions which deposit on the semiconducting surfaces are effectively neutralized. however, and do not form a surface charge on them.
  • the bare" silicon surfaces in the grooves immediately acquire a very thin layer of oxide 26 having a thickness of about 20 angstroms when exposed to air, this layer 26 is so thin that it does not act like an insulating material to ward the gaseous ions. Therefore, a charged layer is not formed within the grooves 20.
  • the oxide should be at least about 1000 angstroms thick.
  • a suitable dispersion of glass particles is preferably prepared about a day prior to the charging step.
  • Some glasses suitable for passivating semiconductor devices are No. 7723 of the Coming Glass Co., also I? 760 and [P 820 of the Innotech Co. Glass No. 7723 has the approximate composition: 30% PbO, 7% A1203, 13% B 0 and 50% SiO Glass IP 760 has the approximate composition: 45.75% PbO, 2.65% A1 0 1.60% ZnO, 10.75% B203 and 39.25% SiO Glass IP has the approximate composition: 50% PbO, 10.1% A1 0 and 39.9% SiOg. All percentages are by weight. As supplied, the 1P glasses have about 75% by weight of the glass below 12;; in size and about below 3 u in size.
  • the glass powder is dispersed in an insulating liquid containing a charging agent.
  • a suitable insulating liquid is a halogenated hydrocarbon such as Genesolve D (Allied Chemical Co.) or Freon TF (du Pont). Both of these are l,l,2-trichloro-l,2,2-trifluorethane.
  • Another suitable insulating liquid is lsopar G (Exxon Corp) This is a mixture of liquid isoparaffinic hydrocarbons and may also be termed a narrow-cut isoparaffinic hydrocarbon fraction of very high purity.
  • Genesolve D and Freon TF are preferred carrier liquids because they are denser than lsopar, evaporate rapidly, and are not flammable. When using Freon TF, the evaporation is so rapid that the wafer may be placed in the furnace at once. When using lsopar G it is necessary to allow the wafer to dry for several minutes before placing it in the furnace.
  • the charging agent may be a surfactant such as one of those given in the Table below.
  • a stock solution is prepared by l dissolving 100 g OLOA 1200 in 100 ml Freon TF and (2) adding 8 ml of this solution to 392 ml of Freon TF.
  • EXAMPLE 1 T0 deposit IP 760 glass on power transistor wafers of the mesa structure, the mesa surfaces are given a double coat of photoresist having a total thickness of 5 a. Glass is to be deposited within the grooves as described above.
  • a mixture of glass powder is prepared by adding 7 ml of the stock solution to 450 ml of Freon, then adding 4 g of glass powder and shaking 2 minutes. This is permitted to stand for at least one day to stabilize it.
  • Deposition is carried out by charging the wafer with a negative corona and immersing in a Pyrex beaker containing the above mixture for 6 seconds. The contents of the beaker are stirred at moderate speed while the glass is depositing.
  • a layer of glass 28 deposits in the grooves 20 but not on the insulating layers 12 and 13.
  • the layer of glass 28' is about 40 p. thick.
  • EXAMPLE 2 In this example, lP820 glass is deposited on thyristor wafers (not shown) having a mesa structure. Grooves are formed on both surfaces of the wafer so that there are mesa structures on both sides. The mesas are coated with about 1.2 p. of SiOz.
  • a dispersion of glass powder is made up by adding 10 ml of the stock solution to 400 ml of Freon, then adding 8 g. of glass powder and shaking for 2 minutes.
  • deposition of the glass is carried out as in Example 1 except that the charged wafers are immersed in the glass mixture for ID seconds. After deposition, the volatile material is permitted to evaporate off and the glass is fused.
  • Samples made as in this example had excellent junction coverage with a layer of fused glass about 30 p. thick. Electrical tests of the collector-base junction showed breakdown voltage in excess of 1000 V, leakage currents of about 4 p. A at room temperature and about 38 p. A at 100 C.
  • EXAMPLE 3 Sometimes it is desirable to passivate a semiconductor device with a glass that is selected because it has a temperature coefficient of expansion closely matching that of the semiconductor. Such a glass may contain boron and may require such a high fusion temperature that the doping pattern of the silicon may be affected. In such cases it is desirable to deposit the glass on a layer of SiO-; instead of directly on the silicon, to shield the silicon from the doping effect of the glass.
  • the wafer 2 has a coating 30 of 8000 A. thickness of Si02 present only in the grooves 20. This can be accomplished by conventional masking techniques.
  • the wafer also (inherently, because of exposure to air) has a very thin coating of oxide 31 onthe top mesa surface and a similar coating of oxide 33 on the bottom surface.
  • the coated wafer is then subjected to a positive corona discharge in dry air (relative humidity 27%). This lays down a layer of positive gaseous ions 32 (FIG. 6) on the SiO layer 30 withinthe grooves 20. No charge is deposited on the very thin oxide layers 31 and 33.
  • a mixture ismade up of 4.5 ml of the above described stock solution of solvent and charging agent added to 300 ml of Freon. To this solution is added 9 ...gof Corning No. 7723 glass powder and the mixture is shaken for 2 minutes to disperse the powder.
  • the charged wafer is immersed in the above disper sion for IOseconds which causesa layer of glass particles 34 todeposit only on the SiOz layers 30 (FIG. 7).
  • a layer 34' (FIG. 8). Thickness of the fused EXAMPLE '4' In this example, a layer of glass is deposited in the grooves of a mesa type diode wafer to increase the breakdown voltage of the diodes.
  • a silicon diode wafer 36 has a P type lower layer 38 and an N type upper layer 40 separated by a PN junction 41.
  • a gridwork of grooves 43 is formed in the wafer 36. The grooves extend into the P type layer 38.
  • a relatively thick layer 42 of SiOz covers the silicon in the grooves and the wafer is charged with a positive corona so that a layer of positively charged ions forms on the SiO surfaces as in Example 3.
  • the top mesa surfaces 46 acquire a very thin oxide layer 48 and the bottom surface 50 of the wafer acquires a very thin layer of oxide 52 but these thin layers do not act as charge storage layers.
  • the charged wafer isimmersed in this dispersion for 6 seconds while the mixture is stirred.
  • the wafer is then removed with a coating of glass particles 44 deposited only on the thick Si0 surfaces 42.
  • the volatile material is allowed to evaporate off and the glass is fused to form a layer 44' (FIG. 10).
  • the charging and glass deposition process is then repeated to deposit a second layer of glass particles 54 on top of the first layer of glass 44' (FIG. 11) and this second layer is fused so that the two layers form a composite layer of glass 56 (FIG. I2).
  • the glass particles carry a charge opposite to the charge on the first glass layer.
  • Breakdown voltages of up to I700 V have been measured on these diodes at room temperature.
  • Dry nitrogen as well as dry air can be used as the ambient for the corona charging step and dry nitrogen is somewhat preferable since ozone production by the corona is much less and since slightly higher voltages can be used without arcing.
  • the quantity of charging agent used in the carrier liquid mixture should be just enough to develop the same sign of charge on every glass particle if the heaviest deposit of glass is desired. Adding more than the optimum amount introduces excess ions which decrease the amount of glass that can be deposited since the excess ions neutralize the charge on the insulating regions of the wafer. However, the quantity of charging agent used can be utilized to vary the thickness of the glass deposit.
  • a suitable glass dispersion is prepared. a small amount of charging agent is added and a slice with a pattern of charges is immersed in the dispersion. If the amount of charging agent is too small, glass will deposit on both charge insulating areas and uncharged areas. Another quantity of glass dispersion is then taken and a somewhat larger amount of charging agent is added. Again, a slice with a pattern of charges on it is dipped in the dispersion and the results noted. Charging agent is added in small incremental steps to fresh portions of dispersion until the glass deposits only on either the charged areas or on the uncharged areas, depending on charge polarities. Once the proper amount of charging agent has been found for a given weight of a certain glass in Freon it is possible to approximate the charging agent required for other quantities of glass by making a linear approximation.
  • silicon dioxide and photoresists have been mentioned in the examples as suitable insulating layer materials, other insulating materials conventionally used on semiconductor devices, such as silicon nitride, may also be used. If the insulating material is organic (as in Example 1 it must be removed before fusion of the glass particles.
  • the method can also be used to simultaneously deposit glass particles on the insulator-coated areas of one side of a semiconductor slice (where the insulator is inorganic) and on the *bare" semiconductor areas on the opposite side of the slice. This can be done by depositing charges of opposite polarities on insulatorcoated areas on the opposite sides and then immersing the slice in a glass dispersion.
  • a method of selectively forming a layer of glass on either bare semiconductor areas or on areas coated with a layer of insulating material of a semiconductor device having both types of said areas comprising:
  • a liquid composition 9 comprising an insulating carrier liquid and dispersed glass particles carrying a charge of particular polarity such that the glass particles deposit selectively on either said bare exposed areas of semiconductor or on said areas coated with insulating material,
  • a gaseous corona discharge such that ions of a particular polarity deposit on said insulating material
  • immersing the charged device in a liquid composition 5 comprising an insulating carrier liquid having suspended therein a dispersion of glass particles and an ionizable agent capable of imparting a net electrical charge of particular polarity to the glass par ticles, such that the glass particles deposit selectively on either said bare exposed areas of semiconductor or on said areas coated with insulating material, removing the glass-coated device from the liquid composition, and firing the coated device at a temperature high enough to fuse said glass.
  • a method of selectively forming a layer of glass on either bare semiconductor areas or on areas coated with a layer of insulating material of a semiconductor device having both types of said areas comprising:
  • a liquid composition comprising an insulating carrier liquid and dispersed glass particles carrying a charge of a particular polarity such that the glass particles deposit whe re H Ris selectively on either said bare exposed areas of semiconductors or on said areas coated with insulating material,

Abstract

A method which comprises depositing a charge of a selected polarity on the areas coated with insulating material of a semiconductor device having areas of ''''bare'''' semiconductor and areas coated with insulating material, immersing the charged device in a liquid composition comprising an insulating liquid and dispersed glass particles carrying a charge of selected polarity which is either the same as or opposite to the charge on the insulating material, such that glass particles deposit either on the semiconductor or on the insulating material, removing the glass-coated device from the liquid, drying and firing to fuse the glass particles on the device.

Description

United States Patent 1 Comizzoli METHOD OF SELECTIVELY DEPOSITING GLASS ON SEMICONDUCTOR DEVICES [75] Inventor: Robert Benedict Comizzoli, Belle Mead, NJ.
[73] Assignee: RCA Corporation, New York, NY.
[22] Filed: Apr. 19, 1974 [21] Appl. No.: 462,492
[52] U.S. Cl. 427/39; 204/181; 252/621; 427/17 [51] Int. Cl 844d 1/18; B01k 5/00 [58] Field of Search... 252/621; 117/37 LE, 93.4 R, 117/934 A, 93.4 NC, 212, 17, 17.5, 40;
[451 July 15, 1975 12/197] Brewer et al. 204/181 2/1972 Sheldon 204/181 S. Hill [57] ABSTRACT A method which comprises depositing a charge of a selected polarity on the areas coated with insulating material of a semiconductor device having areas of bare semiconductor and areas coated with insulating material, immersing the charged device in a liquid composition comprising an insulating liquid and dispersed glass particles carrying a charge of selected polarity which is either the same as or opposite to the charge on the insulating material, such that glass particles deposit either on the semiconductor or on the insulating material, removing the glass-coated device from the liquid, drying and firing to fuse the glass particles on the device.
14 Claims, 14 Drawing Figures METHOD OF SELECTIVELY DEPOSITING GLASS ON SEMICONDUCTOR DEVICES BACKGROUND OF THE INVENTION Although silicon dioxide has been generally used for passivating the exposed surfaces of silicon semiconductor devices, especially the exposed edges of PN junctions, additional protection has been found to be desirable in many cases. The additional protection is needed to give longer protection against atmospheric moisture and other contaminants, for example. It is also desirable, however, to achieve lower surface current leakage between regions of different conductivity types such as the base and collector regions of bipolar transistors.
Added protection against contaminants and decreased current leakage has been obtained by coating or encapsulating devices with various plastics and glasses. In the case of coating or encapsulating with glass, which is often required before encapsulation with plastic, it has been found most desirable to utilize dispersions of very small particle size glass in a carrier liquid to deposit coatings of glass particles on the device surfaces, and then to heat to a temperature just high enough to fuse the glass particles to form a continuous layer.
The glass which is used to passivate semiconductor devices must have a number of properties such as fusion temperature compatible with the semiconductor device, good adherence to the device surface, a temperature coefficient of expansion at least approximately matching that of the semiconductor, low porosity, and an absence of ingredients or contaminants that would adversely affect the electrical characteristics of the device.
A number ofdifferent methods have been used to deposit the glass particles. One of these methods is doctor blading a glass powder slurry over the surface of a semiconductor wafer having many devices built into it by well known diffusion techniques, and then evaporating the liquid. Another method is settling the glass particles out of a liquid dispersion onto the device surface.
The doctor blade method has several disadvantages. It usually is a hand operation requiring much labor and only one side of the wafer can be done at a time. Since it involves mechanical scraping, much wafer breakage and other damage results. In addition, the method achieves selectivity only through utilizing certain surface topography, i.e., it is limited to deposition in re cessed regions.
The settling method is time-consuming, wasteful of glass particles and is non-selective.
Another method which also has previously been used is electrophoresis. In this method, the device (poled either positive or negative) is immersed in a dispersion of glass particles charged opposite to the device being coated and a current is passed through the dispersion. Glass can be deposited selectively only on the conductive parts of the device surface. Besides being unable to deposit glass selectively on insulating regions, another disadvantage of this method is that it is not satisfactory for depositing thick layers because of adherence problems. Further, to be selective, the process uses conductive liquids which are capable of dissolving more contaminants than non-conductive liquids do, and therefore these liquids are more likely to be sources of device contamination.
The present method is an improved, electrostatic method of depositing a glass coating on selected areas of a device having areas of bare semiconductor and also areas coated with an insulating material. The method comprises depositing charges of selected polarity on the areas coated with insulating material and then immersing the charged device in a liquid dispersion of glass particles which are charged either with the same polarity as or with polarity opposite to the charges on the insulating material. The glass particles deposit either on the bare". uncoated areas or on the coated areas of the device depending upon polarity conditions chosen. The device is then removed from the liquid and, after drying, the glass particles are fused by firing. Relatively thick, adherent coatings of glass can be applied in a selective manner.
THE DRAWINGS FIG. I is a cross section view through part of a semi conductor wafer having many transistors separated from each other by grooves;
FIGS. 2, 3 and 4 illustrate successive steps in applying one embodiment of the method of the invention to the wafer of FIG. 1',
FIGS. 58 illustrate steps in applying an alternative embodiment of the method to a semiconductor device wafer;
FIGS. 9-12 are section views of a different device and illustrate steps in coating the device by an embodiment of the methods of the invention;
FIG. 13 is an end view of suitable charging apparatus for use in the present method, and
FIG. 14 is an elevation view of part of the apparatus of FIG. 13.
DESCRIPTION OF PREFERRED EMBODIMENTS Although the present method is applicable to making a number of different types of semiconductor devices, it will be illustrated, first, in connection with making a large number of bipolar transistors on a single semiconductor crystal slice or wafer.
As shown in FIG. 1, a slice 2 of a single crystal'semiconductor material, such as silicon, may have fabricated therein by well known diffusion techniques or a combination of epitaxial growth and diffusion techniques, many transistors 4. Each transistor 4 has an emitter region 6 which may be of N conductivity type, for example, a base region 8 which may be ofP conductivity type, and a collector region 10, which may be of N conductivity type. A layer I2 of an insulating material covers the top surface I4 of each transistor. Another layer of insulating material 13 covers the bottom surface 15 of the slice. The emitter region 6 and base region 8 are separated by a PN junction 16. The base region 8 and the collector region 10 are separated by another PN junction 18. Grooves 20 are provided in the form of a gridwork extending into the top surface 14 of the device array and below the PN junction 18 so that the grooves are on all 4 sides of each transistor 4. It is desirable to cover the exposed portions of the PN junctions with a dielectric material to reduce current leakage across the junctions and to prevent deterioration due to ambient or processing contaminants. It is much more economical to provide the necessary protective coating over the PN junctions while the devices 4 are still a part of the original slice 2 than. it is to treat each individual device after it has been separated from the slice.
When grooves are etched into the silicon of a mesa type wafer, the SIO2 covering the wafer (if this is the insulating material) is first patterned into the groove ge ometry using standard lithographic techniques. Then the silicon is etched using the SiO as the patterndefining mask. Because of etch undercutting. an overhanging shelf of SiO is formed. In depositing the glass by the method of the invention voids may be formed under the shelf which may lead to electrical degradation during further processing steps. Thus, it is advantageous to remove this overhanging Si before charging and glass deposition.
The removal may be accomplished in either of at least two ways. An oxide etch may be used by immersing the wafer long enough to remove the overhang. In this case a fraction of the thickness of the oxide on the mesa surface is removed, but this is not harmful. For example, a 3 minute etch in buffered HF solution purchased from the Transene Corporation was sufficient to remove a 0.001 inch overhang while removing only about 3000 A. of the original l2,000 A. of SiO; on the mesa surface. Another procedure is to use ultrasonic energy to remove the overhang. For example, a Branson Model 4l-4000 Ultrasonic Cleaner was used to re move the overhang in 30 seconds with water and with Freon TF in seconds.
In accordance with one embodiment of the invention, the parts of the slice comprising bare" silicon which are exposed within the grooves are covered with a protective glass coating as follows. The slice 2 is placed in a corona charging device which may consist of 2 parallel arrays of thin, vertically disposed wires held in an insulating frame. The major surfaces of the slice should be carefully oriented so that they are parallel to the wire arrays. The wires may be 1.5 mil diameter tungsten wires spaced 0.5 inch apart. The distance between the parallel arrays is such that when the semiconductor slice 2 is positioned between them, the wires typically are spaced 0.220 inch from the adjacent surfaces of the slice. The spacing of the wires from the surface to be charged can be used to vary the charge level on the slice, although it is usually desirable to charge the insulating region to saturation.
In order to achieve satisfactory charging results, it is desirable to use a charging apparatus that will permit accurate parallel and equidistant positioning of the surfaces of the wafer with respect to two sets of wires in the charging apparatus. A satisfactory charging apparatus is shown in FIGS. 13 and 14.
As illustrated in FIG. 13, the charging apparatus 58 may comprise a base plate 60 having disposed thereon two frames 62 and 64 which may be made of an insulating material such as methylmethacrylate resin. The frames are accurately spaced on the base plate 60 so that they are facing each other. Each of the frames 62 and 64 has a pedestal member 66 and 68 respectively, a panel 70 and 72, respectively, vertically mounted along one edge of the pedestal members 66 and 68, and a top plate 74 and 76, respectively, horizontally mounted on the tops of vertical panels 70 and 72 so that they extend parallel to the pedestal members 66 and 68.
On each of the frames 62 and 64 is an array of wires 78 and 80, respectively. Each array consists of 9 wires spaced equidistant from each other and held under tension in a vertical plane. One end of each wire in the arrays is attached to one of the pedestal members 66 and 68 adjacent its outer edge. The outer end of each of the wires in the arrays 78 and 80 is attached to one end of tension spring 86. The other end of each tension spring 86 is attached to an adjusting screw 88. The adjusting screws 88 are threadedly mounted in buss bars 92 and 94 which are set into plastic blocks 82 and 84, respectively, which extend longitudinally along the outer edges of top plates 74 and 76, respectively.
The wires in the arrays 78 and 80 pass over the outer edges of top plates 74 and 76, respectively.
The buss bars 92 and 94 are connected to a high voltage source (not shown).
During the charging step, the wafer 2 is vertically held between the wire arrays 78 and 80 by a suspending means 96. The suspending means comprises four support posts 98, a pair of horizontal metal tracks and 102, disposed parallel to and above the top plates 74 and 76, having smooth, sloping inner surfaces 104 and 106, respectively, and a wafer holder 108 (FIG. 14).
The wafer holder 108 comprises a metal V-block 110 to the under side of which is fastened a pair of pivoted jaws 112 and 114. The jaw 112 has a grooved finger 116 at its lower end and the jaw I I4 has similar spaced grooved fingers I18 and 120. The fingers 116, 118 and 120 are arranged to receive and hold vertical the wafer 2.
The V-block 110 has smooth sides which slope at an angle which is the same as the angle of the sloping surfaces 104 and 106 of the tracks I00 and 102. The V- block I I0 is thus designed to ride in the tracks I00 and 102 and to make electrical contact therewith. The
tracks are grounded.
During the charging step, the wafer holder is preferably moved back and forth along the tracks 100 and I02 at a speed of about 3 inches per second in order to charge the wafer surfaces uniformly.
A voltage of about 6200 volts negative is applied to the wires. The atmosphere is air or nitrogen but the rel ative humidity is controlled so that it is about 30% at 25 C if silicon dioxide is the insulating material. The charging voltage preferably should be as high as possible without causing arcing since this has been found to give better edge definition of charge on the slice 2 and also provides a more uniform charge. The upper level of relative humidity permissible is a function of elapsed time between charging the surface of the slice and subsequent immersion in a glass dispersion. An elapsed time of one second has been used to advantage. If the time is very short, relative humidity may be higher since there will be less time for charge to leak away. Also, if the insulating material on which the charge is deposited is caused to be hydrophobic, relative humidity can be higher. In fact, when using Waycoat SC I80 photoresist (Philip A. Hund Chemical Corp.) for the insulating material, relative humidities of 65% and even higher can be used.
The wafer held in the wafer holder is thereby grounded by contact at the wafer edge and the slice is exposed to the corona discharge for about 5 to 15 seconds. As indicated in FIGS. 2, this causes a layer 22 of negatively charged gaseous ions to deposit on the insulating layer 12 which is on the top surface I4 of the device array and a similar layer of ions 24 to deposit on the insulating layer I3 disposed on the bottom surface 15 of the slice 2.
The sign of the discharge may be either negative or positive depending on whether the glass particles to be deposited have a negative or positive charge in the liquid and whether the glass is to be deposited on the insulator layers 12 and 13, or on the bare" exposed silicon. In the present example the corona charge is negative.
The gaseous ions 22 and 24 from the corona discharge arrive at the surfaces of the slice 2 and deposit on the surfaces of the insulating layers 12 and 13 (FIG. 2). The ions which deposit on the semiconducting surfaces are effectively neutralized. however, and do not form a surface charge on them. Although the bare" silicon surfaces in the grooves immediately acquire a very thin layer of oxide 26 having a thickness of about 20 angstroms when exposed to air, this layer 26 is so thin that it does not act like an insulating material to ward the gaseous ions. Therefore, a charged layer is not formed within the grooves 20. To hold a charge and also not be subject to having pinholes, the oxide should be at least about 1000 angstroms thick.
A suitable dispersion of glass particles is preferably prepared about a day prior to the charging step. Some glasses suitable for passivating semiconductor devices are No. 7723 of the Coming Glass Co., also I? 760 and [P 820 of the Innotech Co. Glass No. 7723 has the approximate composition: 30% PbO, 7% A1203, 13% B 0 and 50% SiO Glass IP 760 has the approximate composition: 45.75% PbO, 2.65% A1 0 1.60% ZnO, 10.75% B203 and 39.25% SiO Glass IP has the approximate composition: 50% PbO, 10.1% A1 0 and 39.9% SiOg. All percentages are by weight. As supplied, the 1P glasses have about 75% by weight of the glass below 12;; in size and about below 3 u in size.
The glass powder is dispersed in an insulating liquid containing a charging agent. A suitable insulating liquid is a halogenated hydrocarbon such as Genesolve D (Allied Chemical Co.) or Freon TF (du Pont). Both of these are l,l,2-trichloro-l,2,2-trifluorethane. Another suitable insulating liquid is lsopar G (Exxon Corp) This is a mixture of liquid isoparaffinic hydrocarbons and may also be termed a narrow-cut isoparaffinic hydrocarbon fraction of very high purity. Genesolve D and Freon TF are preferred carrier liquids because they are denser than lsopar, evaporate rapidly, and are not flammable. When using Freon TF, the evaporation is so rapid that the wafer may be placed in the furnace at once. When using lsopar G it is necessary to allow the wafer to dry for several minutes before placing it in the furnace.
The charging agent may be a surfactant such as one of those given in the Table below.
Table Sign of charge induced on Surfactant glass particles Table Continued Sign of charge induced on Surfactant glass particles Petroleum barium sulfonatc Zinc octoatc "OLOA 1200 (Chevron. lnc.) Petroleum ammonium sulfonatc N-alkylpiperizene monoalkcnyl succinimide RNHC'H CH NH, where R is polybutyl radical OLOA 1200 has the structural formula:
11 ll where H ll l C 11 I with nitrogen 2.10% by weight and alkalinity value of 43.
With certain lots oflP 820 glass it has been found advantageous to use about 5 minutes of ultrasonic agitation with power input of watts in the glass dispersion to break up agglomerates of fine particles. If this is not done the agglomerates tend to give a bumpy appearance to the deposited glass, and, more seriously, sometimes stick to regions where no glass is desired.
For use in the following examples a stock solution is prepared by l dissolving 100 g OLOA 1200 in 100 ml Freon TF and (2) adding 8 ml of this solution to 392 ml of Freon TF.
EXAMPLE 1 T0 deposit IP 760 glass on power transistor wafers of the mesa structure, the mesa surfaces are given a double coat of photoresist having a total thickness of 5 a. Glass is to be deposited within the grooves as described above.
A mixture of glass powder is prepared by adding 7 ml of the stock solution to 450 ml of Freon, then adding 4 g of glass powder and shaking 2 minutes. This is permitted to stand for at least one day to stabilize it.
Deposition is carried out by charging the wafer with a negative corona and immersing in a Pyrex beaker containing the above mixture for 6 seconds. The contents of the beaker are stirred at moderate speed while the glass is depositing.
As shown in FIG. 3, a layer of glass 28 deposits in the grooves 20 but not on the insulating layers 12 and 13.
After the glass is deposited, volatile material (including photoresist) is burned off at about 525 C and the glass is then fused to form a layer 28' (FIG. 4). After fusing, the layer of glass 28' is about 40 p. thick.
EXAMPLE 2 In this example, lP820 glass is deposited on thyristor wafers (not shown) having a mesa structure. Grooves are formed on both surfaces of the wafer so that there are mesa structures on both sides. The mesas are coated with about 1.2 p. of SiOz.
A dispersion of glass powder is made up by adding 10 ml of the stock solution to 400 ml of Freon, then adding 8 g. of glass powder and shaking for 2 minutes.
After allowing the glass dispersion to stand for one day, deposition of the glass is carried out as in Example 1 except that the charged wafers are immersed in the glass mixture for ID seconds. After deposition, the volatile material is permitted to evaporate off and the glass is fused.
Samples made as in this example had excellent junction coverage with a layer of fused glass about 30 p. thick. Electrical tests of the collector-base junction showed breakdown voltage in excess of 1000 V, leakage currents of about 4 p. A at room temperature and about 38 p. A at 100 C.
EXAMPLE 3 Sometimes it is desirable to passivate a semiconductor device with a glass that is selected because it has a temperature coefficient of expansion closely matching that of the semiconductor. Such a glass may contain boron and may require such a high fusion temperature that the doping pattern of the silicon may be affected. In such cases it is desirable to deposit the glass on a layer of SiO-; instead of directly on the silicon, to shield the silicon from the doping effect of the glass.
In this example, (FIG. 5) the wafer 2 has a coating 30 of 8000 A. thickness of Si02 present only in the grooves 20. This can be accomplished by conventional masking techniques. The wafer also (inherently, because of exposure to air) has a very thin coating of oxide 31 onthe top mesa surface and a similar coating of oxide 33 on the bottom surface. The coated wafer is then subjected to a positive corona discharge in dry air (relative humidity 27%). This lays down a layer of positive gaseous ions 32 (FIG. 6) on the SiO layer 30 withinthe grooves 20. No charge is deposited on the very thin oxide layers 31 and 33. I
A mixture ismade up of 4.5 ml of the above described stock solution of solvent and charging agent added to 300 ml of Freon. To this solution is added 9 ...gof Corning No. 7723 glass powder and the mixture is shaken for 2 minutes to disperse the powder.
The charged wafer is immersed in the above disper sion for IOseconds which causesa layer of glass particles 34 todeposit only on the SiOz layers 30 (FIG. 7).
The wafer is removed from the dispersion, the residual volatile material is burned off-and the glass is fused to form a layer 34' (FIG. 8). Thickness of the fused EXAMPLE '4' In this example, a layer of glass is deposited in the grooves of a mesa type diode wafer to increase the breakdown voltage of the diodes.
As shown in FIG. 9, a silicon diode wafer 36 has a P type lower layer 38 and an N type upper layer 40 separated by a PN junction 41. A gridwork of grooves 43 is formed in the wafer 36. The grooves extend into the P type layer 38.
A relatively thick layer 42 of SiOz covers the silicon in the grooves and the wafer is charged with a positive corona so that a layer of positively charged ions forms on the SiO surfaces as in Example 3. The top mesa surfaces 46 acquire a very thin oxide layer 48 and the bottom surface 50 of the wafer acquires a very thin layer of oxide 52 but these thin layers do not act as charge storage layers.A dispersion made up by adding ml of the stock solution of carrier and charging agent to 400 ml of Freonand then adding 6 g of IP760 glass powder and shaking for 2 minutes is used to deposit the glass.
The charged wafer isimmersed in this dispersion for 6 seconds while the mixture is stirred. The wafer is then removed with a coating of glass particles 44 deposited only on the thick Si0 surfaces 42. The volatile material is allowed to evaporate off and the glass is fused to form a layer 44' (FIG. 10). The charging and glass deposition process is then repeated to deposit a second layer of glass particles 54 on top of the first layer of glass 44' (FIG. 11) and this second layer is fused so that the two layers form a composite layer of glass 56 (FIG. I2). In the glass dispersion which is used to deposit the second layer of glass particles, the glass particles carry a charge opposite to the charge on the first glass layer.
Breakdown voltages of up to I700 V have been measured on these diodes at room temperature.
Dry nitrogen as well as dry air can be used as the ambient for the corona charging step and dry nitrogen is somewhat preferable since ozone production by the corona is much less and since slightly higher voltages can be used without arcing.
The quantity of charging agent used in the carrier liquid mixture should be just enough to develop the same sign of charge on every glass particle if the heaviest deposit of glass is desired. Adding more than the optimum amount introduces excess ions which decrease the amount of glass that can be deposited since the excess ions neutralize the charge on the insulating regions of the wafer. However, the quantity of charging agent used can be utilized to vary the thickness of the glass deposit.
In determining how much charging agent to use, a suitable glass dispersion is prepared. a small amount of charging agent is added and a slice with a pattern of charges is immersed in the dispersion. If the amount of charging agent is too small, glass will deposit on both charge insulating areas and uncharged areas. Another quantity of glass dispersion is then taken and a somewhat larger amount of charging agent is added. Again, a slice with a pattern of charges on it is dipped in the dispersion and the results noted. Charging agent is added in small incremental steps to fresh portions of dispersion until the glass deposits only on either the charged areas or on the uncharged areas, depending on charge polarities. Once the proper amount of charging agent has been found for a given weight of a certain glass in Freon it is possible to approximate the charging agent required for other quantities of glass by making a linear approximation.
Although silicon dioxide and photoresists have been mentioned in the examples as suitable insulating layer materials, other insulating materials conventionally used on semiconductor devices, such as silicon nitride, may also be used. If the insulating material is organic (as in Example 1 it must be removed before fusion of the glass particles.
The method can also be used to simultaneously deposit glass particles on the insulator-coated areas of one side of a semiconductor slice (where the insulator is inorganic) and on the *bare" semiconductor areas on the opposite side of the slice. This can be done by depositing charges of opposite polarities on insulatorcoated areas on the opposite sides and then immersing the slice in a glass dispersion.
I claim:
1. A method of selectively forming a layer of glass on either bare semiconductor areas or on areas coated with a layer of insulating material of a semiconductor device having both types of said areas, comprising:
depositing electrical charges of a particular polarity on said insulating material,
immersing the charged device in a liquid composition 9 comprising an insulating carrier liquid and dispersed glass particles carrying a charge of particular polarity such that the glass particles deposit selectively on either said bare exposed areas of semiconductor or on said areas coated with insulating material,
removing the glass-coated device from the liquid composition, drying and firing the coated device at a temperature high enough to fuse said glass.
2. A method according to claim 1 in which said charges on said insulating material have the same sign as said charges on said glass particles so that said glass particles are deposited on said bare exposed areas of semiconductor.
3. A method according to claim I in which said semiconductor is silicon and said insulating material is silicon dioxide.
4. A method according to claim 2 in which said insulating material is a photoresist.
5. A method according to claim 1 in which said insulating material is silicon nitride.
6. A method according to claim 1 in which said insulating liquid is l,l,2-trichloro-l,2,2-trifluoroethane.
7. A method according to claim 6 in which said liquid composition contains a charging agent and said charging agent is zirconium octoate.
8. A method according to claim 6 in which said liquid composition contains a charging agent and said charging agent has the structural formula:
H l0 R-C-C HHH HHl-l l l I ll l N-(c-c-N}c-c-N l 1| ll H-C-C HH HHH with nitrogen 2.10% by weight and alkalinity value of 43.
9. A method according to claim 1 in which said glass comprises about: 30% PbO, 7% Al O [3% B and 50% SlOz by weight.
10. A method according to claim 1 in which the relative humidity of the ambient to which the device is exposed is controlled to a sufficiently low value to prevent discharging of the charged surface of said insulating material between charging and immersion in the liquid composition.
11. A method according to claim 10 in which said relative humidity is about 12. A method of selectively forming a layer of glass on either bare semiconductor areas or on areas coated with an insulating material, of a semiconductor device having both types of said areas, comprising:
subjecting said device to a gaseous corona discharge such that ions of a particular polarity deposit on said insulating material, immersing the charged device in a liquid composition 5 comprising an insulating carrier liquid having suspended therein a dispersion of glass particles and an ionizable agent capable of imparting a net electrical charge of particular polarity to the glass par ticles, such that the glass particles deposit selectively on either said bare exposed areas of semiconductor or on said areas coated with insulating material, removing the glass-coated device from the liquid composition, and firing the coated device at a temperature high enough to fuse said glass.
13. A method according to claim 12 in which said gaseous ions and said charged glass particles have opposite electrical polarities such that the glass particles deposit on the insulating material.
14. A method of selectively forming a layer of glass on either bare semiconductor areas or on areas coated with a layer of insulating material of a semiconductor device having both types of said areas, comprising:
depositing charges of a particular polarity on said insulating material,
immersing the charged device in a liquid composition comprising an insulating carrier liquid and dispersed glass particles carrying a charge of a particular polarity such that the glass particles deposit whe re H Ris selectively on either said bare exposed areas of semiconductors or on said areas coated with insulating material,
removing the glass-coated device from the liquid composition, drying and firing the coated device at a temperature high enough to fuse said glass,
cooling the glass-coated device,
depositing charges of a particular polarity on the glass-coated surface,
immersing the charged device in another glass dispersion in which the glass particles carry a charge having a polarity opposite to that on the glass coating first deposited, until a layer of glass particles deposits on said glass coating,
removing the device from said dispersion, drying and firing the coated device a second time at a temper ature high enough to fuse said glass.

Claims (14)

1. A METHOD OF SELECTIVELY FORMING A LAYER OF GLASS ON EITHER BARE SEMICONDUCTOR AREAS OR ON AREAS COATED WITH A LAYER OF INSULATING MATERIAL OF A SEMICONDUCTOR DEVICE HAVING BOTH TYPES OF SAID AREAS, COMPRISING, DEPOSITING ELECTRICAL CHARGES OF A PARTICULAR POLARITY ON SAID INSULATING MATERIAL, IMMERSING THE CHARGED DEVICE IN A LIQUID COMPOSITION COMPRISING AN INSULATING CARRIER LIQUID AND DISPERSED GLASS PARTICLES CARRYING A CHARGE OF PARTICULAR POLARITY SUCH THAT THE GLASS PARTICLES DEPOSIT SELECTIVELY ON EITHER SAID BARE EXPOSED AREAS OF SEMICONDUCTOR OR ON SAID AREAS COATED WITH INSULATING MATERIAL, REMOVING THE GLASS-COATED DEVICE FROM THE LIQUID COMPOSITION, DRYING AND FIRING THE COATED DEVICE AT A TEMPERATURE HIGH ENOUGH TO FUSE SAID GLASS.
2. A METHOD ACCORDING TO CLAIM 1 IN WHICH SAID CHARGES ON SAID INSULATING MATERIAL HAVE THE SAME SIGN AS SAID CHARGES ON SAID GLASS PARTICLES SO THAT SAID GLASS PARTICLES ARE DEPOSITED ON SAID BARE EXPOSED AREAS OF SEMICONDUCTOR.
3. A METHOD ACCORDING TO CLAIM 1 IN WHICH SAID SEMICONDUCTOR IS SILTCON AND SAID INSULATING MATERIAL IS SILICON DIOXID
4. A method according to claim 2 in which said insulating material is a photoresist.
5. A method according to claim 1 in which said insulating material is silicon nitride.
6. A method according to claim 1 in which said insulating liquid is 1,1,2-trichloro-1,2,2-trifluoroethane.
7. A method according to claim 6 in which said liquid composition contains a charging agent and said charging agent is zirconium octoate.
8. A method according to claim 6 in which said liquid composition contains a charging agent and said charging agent has the structural formula:
9. A method according to claim 1 in which said glass comprises about: 30% PbO, 7% A1203, 13% B203 and 50% Si02 by weight.
10. A method according to claim 1 in which the relative humidity of the ambient to which the device is exposed is controlled to a sufficiently low value to prevent discharging of the charged surface of said insulating material between charging and immersion in the liquid composition.
11. A method according to claim 10 in which said relative humidity is about 25 - 30%.
12. A method of selectively forming a layer of glass on either bare semiconductor areas or on areas coated with an insulating material, of a semiconductor device having both types of said areas, comprising: subjecting said device to a gaseous corona discharge such that ions of a particular polarity deposit on said insulating material, immersing the charged device in a liquid composition comprising an insulating carrier liquid having suspended therein a dispersion of glass particles and an ionizable agent capable of imparting a net electrical charge of particular polarity to the glass particles, such that the glass particles deposit selectively on either said bare exposed areas of semiconductor or on said areas coated with insulating material, removing the glass-coated device from the liquid composition, and firing the coated device at a temperature high enough to fuse said glass.
13. A method according to claim 12 in which said gaseous ions and said charged glass particles have opposite electrical polarities such that the glass particles deposit on the insulating material.
14. A method of selectively forming a layer of glass on either bare semiconductor areas or on areas coated with a layer of insulating material of a semiconductor device having both types of said areas, comprising: depositing charges of a particular polarity on said insulating material, immersing the charged device in a liquid composition comprising an insulating carrier liquid and dispersed glass particles carrying a charge of a particular polarity such that the glass particles deposit selectively on either said bare exposed areas of semiconductors or on said areas coated with insulating material, removing the glass-coated device from the liquid composition, drying and firing the coated dEvice at a temperature high enough to fuse said glass, cooling the glass-coated device, depositing charges of a particular polarity on the glass-coated surface, immersing the charged device in another glass dispersion in which the glass particles carry a charge having a polarity opposite to that on the glass coating first deposited, until a layer of glass particles deposits on said glass coating, removing the device from said dispersion, drying and firing the coated device a second time at a temperature high enough to fuse said glass.
US462492A 1974-04-19 1974-04-19 Method of selectively depositing glass on semiconductor devices Expired - Lifetime US3895127A (en)

Priority Applications (13)

Application Number Priority Date Filing Date Title
US462492A US3895127A (en) 1974-04-19 1974-04-19 Method of selectively depositing glass on semiconductor devices
IN232/CAL/75A IN143919B (en) 1974-04-19 1975-02-10
SE7502450A SE407427B (en) 1974-04-19 1975-03-05 PROCEDURE FOR SELECTIVELY FORMING A LAYER OF GLASS ON A SEMICONDUCTOR DEVICE
CA221,479A CA1038329A (en) 1974-04-19 1975-03-05 Method of selectively depositing glass on semiconductor devices
BR1730/75A BR7501335A (en) 1974-04-19 1975-03-06 PROCESS OF SELECTIVE FORMATION OF A GLASS LAYER ON SEMICONDUCTORS
FR7509253A FR2268357B1 (en) 1974-04-19 1975-03-25
JP50037392A JPS5760773B2 (en) 1974-04-19 1975-03-26
YU00771/75A YU77175A (en) 1974-04-19 1975-03-27 Process for the selective forming of a glass coating on semiconductor devices
NL7503711A NL7503711A (en) 1974-04-19 1975-03-27 METHOD FOR SELECTIVE FORMING OF GLASS LAYERS.
DE19752513945 DE2513945A1 (en) 1974-04-19 1975-03-29 PROCESS FOR PASSIVATING THE SURFACES OF SEMI-CONDUCTIVE COMPONENTS
IT67867/75A IT1044487B (en) 1974-04-19 1975-04-04 PROCEDURE FOR SELECTIVE GLASS DEPOSITION ON SEMICONDUCTIVE DEVICES
GB1474375A GB1464682A (en) 1974-04-19 1975-04-10 Method of selectively depositing glass on semiconductor devices
BE154554A BE826941A (en) 1974-04-19 1975-07-16 METHOD FOR SELECTIVELY DEPOSITING A LAYER OF GLASS ON SEMICONDUCTOR DEVICES

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US462492A US3895127A (en) 1974-04-19 1974-04-19 Method of selectively depositing glass on semiconductor devices

Publications (1)

Publication Number Publication Date
US3895127A true US3895127A (en) 1975-07-15

Family

ID=23836608

Family Applications (1)

Application Number Title Priority Date Filing Date
US462492A Expired - Lifetime US3895127A (en) 1974-04-19 1974-04-19 Method of selectively depositing glass on semiconductor devices

Country Status (13)

Country Link
US (1) US3895127A (en)
JP (1) JPS5760773B2 (en)
BE (1) BE826941A (en)
BR (1) BR7501335A (en)
CA (1) CA1038329A (en)
DE (1) DE2513945A1 (en)
FR (1) FR2268357B1 (en)
GB (1) GB1464682A (en)
IN (1) IN143919B (en)
IT (1) IT1044487B (en)
NL (1) NL7503711A (en)
SE (1) SE407427B (en)
YU (1) YU77175A (en)

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2402303A1 (en) * 1977-09-03 1979-03-30 Semikron Gleichrichterbau SURFACE TREATMENT FOR STABILIZATION OF SEMICONDUCTOR BODIES
EP0013815A1 (en) * 1978-12-15 1980-08-06 Westinghouse Electric Corporation Glass-sealed multichip process
US4218493A (en) * 1977-12-02 1980-08-19 The Continental Group, Inc. Electrostatic repair coating
FR2466859A1 (en) * 1979-10-05 1981-04-10 Thomson Csf SILICON NITRIDE MASKING AND GLAZING GLASSIVATION METHOD AND SEMICONDUCTOR COMPONENTS OBTAINED
US4296370A (en) * 1979-10-11 1981-10-20 Rca Corporation Method of detecting a thin insulating film over a conductor
US4551353A (en) * 1981-12-30 1985-11-05 Unitrode Corporation Method for reducing leakage currents in semiconductor devices
US4681667A (en) * 1982-12-22 1987-07-21 Nec Corporation Method of producing electrostrictive effect element
US5268233A (en) * 1991-11-22 1993-12-07 The Lubrizol Corporation Methods of preparing sintered shapes and green shapes used therein
US5342563A (en) * 1991-11-22 1994-08-30 The Lubrizol Corporation Methods of preparing sintered shapes and green bodies used therein
WO2000072371A1 (en) * 1999-05-21 2000-11-30 Symetrix Corporation Fabrication of integrated circuit by selective deposition of precursor liquid
US20030118947A1 (en) * 2001-12-04 2003-06-26 Primaxx, Inc. System and method for selective deposition of precursor material
US6613695B2 (en) 2000-11-24 2003-09-02 Asm America, Inc. Surface preparation prior to deposition
US6780491B1 (en) * 1996-12-12 2004-08-24 Micron Technology, Inc. Microstructures including hydrophilic particles
US20050212119A1 (en) * 2001-10-02 2005-09-29 Shero Eric J Incorporation of nitrogen into high k dielectric film
US20070018272A1 (en) * 2005-06-29 2007-01-25 Henning Jason P Reduced Leakage Power Devices By Inversion Layer Surface Passivation
US20080035934A1 (en) * 2005-06-29 2008-02-14 Sheppard Scott T Passivation of Wide Band-Gap Based Semiconductor Devices with Hydrogen-Free Sputtered Nitrides
US20090215280A1 (en) * 2005-06-29 2009-08-27 Cree, Inc. Passivation of Wide Band-Gap Based Semiconductor Devices with Hydrogen-Free Sputtered Nitrides
US20100193955A1 (en) * 2009-02-02 2010-08-05 Asm America, Inc. Plasma-enhanced atomic layer deposition of conductive material over dielectric layers
US8994073B2 (en) 2012-10-04 2015-03-31 Cree, Inc. Hydrogen mitigation schemes in the passivation of advanced devices
US9812338B2 (en) 2013-03-14 2017-11-07 Cree, Inc. Encapsulation of advanced devices using novel PECVD and ALD schemes
US9991399B2 (en) 2012-10-04 2018-06-05 Cree, Inc. Passivation structure for semiconductor devices

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7500492A (en) * 1975-01-16 1976-07-20 Philips Nv PROCESS FOR THE MANUFACTURE OF SEMI-GUIDE DEVICES, IN WHICH A GLASS COVER IS APPLIED, AND SEMI-GUIDE DEVICES MANUFACTURED ACCORDING TO THIS PROCESS.
JPS5393783A (en) * 1977-01-26 1978-08-17 Nec Home Electronics Ltd Mesa type semiconductor device
IN147578B (en) * 1977-02-24 1980-04-19 Rca Corp
IN147572B (en) * 1977-02-24 1980-04-19 Rca Corp
DE3138340A1 (en) * 1981-09-26 1983-04-14 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Process for producing planar components
JPS58173745U (en) * 1982-05-17 1983-11-19 国産電機株式会社 Engine-driven generator rotation speed control device
US6945121B2 (en) 2002-12-04 2005-09-20 Kimberly, Clark Worldwide, Inc. Apparatus for simulating a dynamic force response

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2966429A (en) * 1956-08-31 1960-12-27 Gen Electric Method of and apparatus for making printed circuits
US3280019A (en) * 1963-07-03 1966-10-18 Ibm Method of selectively coating semiconductor chips
US3400000A (en) * 1965-05-17 1968-09-03 Du Pont Surface modified electrostatic enamel powders and method
US3629086A (en) * 1969-12-12 1971-12-21 Ford Motor Co Anodic deposition of ceramic frit with cationic envelope
US3642597A (en) * 1970-03-20 1972-02-15 Gen Electric Semiconductor passivating process

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5339442B2 (en) * 1972-03-02 1978-10-21
JPS551703B2 (en) * 1972-07-07 1980-01-16

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2966429A (en) * 1956-08-31 1960-12-27 Gen Electric Method of and apparatus for making printed circuits
US3280019A (en) * 1963-07-03 1966-10-18 Ibm Method of selectively coating semiconductor chips
US3400000A (en) * 1965-05-17 1968-09-03 Du Pont Surface modified electrostatic enamel powders and method
US3629086A (en) * 1969-12-12 1971-12-21 Ford Motor Co Anodic deposition of ceramic frit with cationic envelope
US3642597A (en) * 1970-03-20 1972-02-15 Gen Electric Semiconductor passivating process

Cited By (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2402303A1 (en) * 1977-09-03 1979-03-30 Semikron Gleichrichterbau SURFACE TREATMENT FOR STABILIZATION OF SEMICONDUCTOR BODIES
US4218493A (en) * 1977-12-02 1980-08-19 The Continental Group, Inc. Electrostatic repair coating
EP0013815A1 (en) * 1978-12-15 1980-08-06 Westinghouse Electric Corporation Glass-sealed multichip process
FR2466859A1 (en) * 1979-10-05 1981-04-10 Thomson Csf SILICON NITRIDE MASKING AND GLAZING GLASSIVATION METHOD AND SEMICONDUCTOR COMPONENTS OBTAINED
EP0028170A1 (en) * 1979-10-05 1981-05-06 Thomson-Csf Method of grooving and vitrification by silicon nitride masking and semiconductor components obtained
US4296370A (en) * 1979-10-11 1981-10-20 Rca Corporation Method of detecting a thin insulating film over a conductor
US4551353A (en) * 1981-12-30 1985-11-05 Unitrode Corporation Method for reducing leakage currents in semiconductor devices
US4681667A (en) * 1982-12-22 1987-07-21 Nec Corporation Method of producing electrostrictive effect element
US5585428A (en) * 1991-11-22 1996-12-17 The Lubrizol Corporation Green bodies formed from inorganic powders and a carboxylic acylating agent
US5342563A (en) * 1991-11-22 1994-08-30 The Lubrizol Corporation Methods of preparing sintered shapes and green bodies used therein
US5268233A (en) * 1991-11-22 1993-12-07 The Lubrizol Corporation Methods of preparing sintered shapes and green shapes used therein
US6780491B1 (en) * 1996-12-12 2004-08-24 Micron Technology, Inc. Microstructures including hydrophilic particles
WO2000072371A1 (en) * 1999-05-21 2000-11-30 Symetrix Corporation Fabrication of integrated circuit by selective deposition of precursor liquid
US6448190B1 (en) 1999-05-21 2002-09-10 Symetrix Corporation Method and apparatus for fabrication of integrated circuit by selective deposition of precursor liquid
US7056835B2 (en) 2000-11-24 2006-06-06 Asm America, Inc. Surface preparation prior to deposition
US7476627B2 (en) 2000-11-24 2009-01-13 Asm America, Inc. Surface preparation prior to deposition
US6613695B2 (en) 2000-11-24 2003-09-02 Asm America, Inc. Surface preparation prior to deposition
US20040121620A1 (en) * 2000-11-24 2004-06-24 Pomarede Christophe F. Surface preparation prior to deposition
US20040147101A1 (en) * 2000-11-24 2004-07-29 Pomarede Christophe F. Surface preparation prior to deposition
US20060205230A1 (en) * 2000-11-24 2006-09-14 Pomarede Christophe F Surface preparation prior to deposition
US6958277B2 (en) 2000-11-24 2005-10-25 Asm America, Inc. Surface preparation prior to deposition
US6960537B2 (en) 2001-10-02 2005-11-01 Asm America, Inc. Incorporation of nitrogen into high k dielectric film
US20050212119A1 (en) * 2001-10-02 2005-09-29 Shero Eric J Incorporation of nitrogen into high k dielectric film
US7569284B2 (en) 2001-10-02 2009-08-04 Asm America, Inc. Incorporation of nitrogen into high k dielectric film
US7405453B2 (en) 2001-10-02 2008-07-29 Asm America, Inc. Incorporation of nitrogen into high k dielectric film
US20080286589A1 (en) * 2001-10-02 2008-11-20 Asm America, Inc. Incorporation of nitrogen into high k dielectric film
US20030118947A1 (en) * 2001-12-04 2003-06-26 Primaxx, Inc. System and method for selective deposition of precursor material
US7696584B2 (en) * 2005-06-29 2010-04-13 Cree, Inc. Reduced leakage power devices by inversion layer surface passivation
US20080035934A1 (en) * 2005-06-29 2008-02-14 Sheppard Scott T Passivation of Wide Band-Gap Based Semiconductor Devices with Hydrogen-Free Sputtered Nitrides
US20090215280A1 (en) * 2005-06-29 2009-08-27 Cree, Inc. Passivation of Wide Band-Gap Based Semiconductor Devices with Hydrogen-Free Sputtered Nitrides
US20070018272A1 (en) * 2005-06-29 2007-01-25 Henning Jason P Reduced Leakage Power Devices By Inversion Layer Surface Passivation
US7855401B2 (en) 2005-06-29 2010-12-21 Cree, Inc. Passivation of wide band-gap based semiconductor devices with hydrogen-free sputtered nitrides
US7858460B2 (en) 2005-06-29 2010-12-28 Cree, Inc. Passivation of wide band-gap based semiconductor devices with hydrogen-free sputtered nitrides
US20100193955A1 (en) * 2009-02-02 2010-08-05 Asm America, Inc. Plasma-enhanced atomic layer deposition of conductive material over dielectric layers
US8557702B2 (en) 2009-02-02 2013-10-15 Asm America, Inc. Plasma-enhanced atomic layers deposition of conductive material over dielectric layers
US9466574B2 (en) 2009-02-02 2016-10-11 Asm America, Inc. Plasma-enhanced atomic layer deposition of conductive material over dielectric layers
US8994073B2 (en) 2012-10-04 2015-03-31 Cree, Inc. Hydrogen mitigation schemes in the passivation of advanced devices
US9991399B2 (en) 2012-10-04 2018-06-05 Cree, Inc. Passivation structure for semiconductor devices
USRE49167E1 (en) 2012-10-04 2022-08-09 Wolfspeed, Inc. Passivation structure for semiconductor devices
US9812338B2 (en) 2013-03-14 2017-11-07 Cree, Inc. Encapsulation of advanced devices using novel PECVD and ALD schemes

Also Published As

Publication number Publication date
IT1044487B (en) 1980-03-20
SE7502450L (en) 1975-10-20
GB1464682A (en) 1977-02-16
NL7503711A (en) 1975-10-21
JPS5760773B2 (en) 1982-12-21
SE407427B (en) 1979-03-26
JPS50137684A (en) 1975-10-31
YU77175A (en) 1983-04-27
FR2268357A1 (en) 1975-11-14
FR2268357B1 (en) 1979-03-09
DE2513945A1 (en) 1975-10-30
IN143919B (en) 1978-02-25
BE826941A (en) 1975-07-16
CA1038329A (en) 1978-09-12
BR7501335A (en) 1976-03-09

Similar Documents

Publication Publication Date Title
US3895127A (en) Method of selectively depositing glass on semiconductor devices
Comizzoli Uses of corona discharges in the semiconductor industry
US4326165A (en) Corona charging for testing reliability of insulator-covered semiconductor devices
Lampe et al. TdI18: Process integration of the ferroelectric memory FETs (FEMFETs) for ndro ferram
Ohmi et al. Static charge removal with IPA solution
Voorthuyzen et al. Research and development of miniaturized electrets
US3421056A (en) Thin window drifted silicon,charged particle detector
US4168432A (en) Method of testing radiation hardness of a semiconductor device
JPH06232243A (en) Electrostatic chuck
Worthing D‐C Dielectric Breakdown of Amorphous Silicon Dioxide Films at Room Temperature
US6352589B1 (en) Apparatus for spin-coating semiconductor substrate and method of doing the same
EP0398806A3 (en) Method of fabricating a semiconductor device
JPS55154743A (en) Semiconductor device and method of fabricating the same
KR800000439B1 (en) Method of selectively depositing glass on semiconductor devices
JPS6114660B2 (en)
JPH03204924A (en) Specimen holder
Lifshitz et al. Water‐Related Charge Motion in Dielectrics
US20010009700A1 (en) Procedure and apparatus for transferring of addition to the surface of a movable material web
Cheng et al. Surface flashover of water repellant insulators under moist conditions
Comizzoli Nondestructive, Reverse Decoration of Defects in IC Passivation Overcoats
JPH06350078A (en) Semiconductor device and manufacture thereof
Comizzoli Corona Discharge--Electrostatic Method for Deposition of Powdered Passivation Glass on Semiconductor Devices
Nakhmanson et al. The conduction channels on MIS and MIM structure splits
JPH0216749A (en) Wafer holder for electron beam exposure device
Makky et al. Island stage of InP anodization