Búsqueda Imágenes Maps Play YouTube Noticias Gmail Drive Más »
Iniciar sesión
Usuarios de lectores de pantalla: deben hacer clic en este enlace para utilizar el modo de accesibilidad. Este modo tiene las mismas funciones esenciales pero funciona mejor con el lector.


  1. Búsqueda avanzada de patentes
Número de publicaciónUS3927688 A
Tipo de publicaciónConcesión
Fecha de publicación23 Dic 1975
Fecha de presentación4 Nov 1974
Fecha de prioridad4 Nov 1974
Número de publicaciónUS 3927688 A, US 3927688A, US-A-3927688, US3927688 A, US3927688A
InventoresCohn Alfred, Reynolds James S
Cesionario originalCohn Alfred
Exportar citaBiBTeX, EndNote, RefMan
Enlaces externos: USPTO, Cesión de USPTO, Espacenet
Electronic coin counter
US 3927688 A
An improved electronic signal counting and totalizing system driven by pulses emanating from coin registering switches and adapted to electronically store and count-in the signals separately, in sequence, with improved efficiency despite signal aberrations; the system operates to index a permanent non-volatile totalizer (mechanical counting state), as well as an electronic "clearing" arrangement whereby the signals are negated and the circuit reset for a following pulse. This circuit arrangement features integrated circuit implementation with pulse recognition and reset circuitry comprised of relatively reliable, noise-immune sub-circuits which are nonetheless relatively simple and inexpensive - especially as implemented with "cos/mos" integrated circuit modules for gating, oscillating, counting and pulse generation functions.
Previous page
Next page
Reclamaciones  disponible en
Descripción  (El texto procesado por OCR puede contener errores)

United States Patent [1 1 Cohn et al.

[ Dec. 23, 1975 ELECTRONIC COIN COUNTER [75] Inventors: Alfred Cohn, Culver City; James S.

Reynolds, Canoga Park, both of Calif.

[73] Assignee: Alfred Cohn, Culver City, Calif.

[22] Filed: Nov. 4, 1974 [21] Appl. No.: 520,308

Primary Examiner-Stanley l-l. Tollberg Attorney, Agent, or Firm-Marvin H. Kleinberg [5 7] ABSTRACT An improved electronic signal counting and totalizing system driven by pulses emanating from coin registering switches and adapted to electronically store and count-in the signals separately, in sequence, with improved efficiency despite signal aberrations; the system operates to index a permanent non-volatile totalizer (mechanical counting state), as well as an electronic clearing arrangement whereby the signals are negated and the circuit reset for a following pulse. This circuit arrangement features integrated circuit implementation with pulse recognition and reset circuitry comprised of relatively reliable, noise-immune sub-circuits which are nonetheless relatively simple and inexpensive especially as implemented with cos/mos integrated circuit modules for gating, oscillating, counting and pulse generation functions.

20 Claims, 9 Drawing Figures US. Patent Dec. 23, 1975 Sheet2of4 3,927,688

US. Patent Dec. 23, 1975 Sheet 4 of4 3,927,688


ELECTRONIC COIN COUNTER FIELD OF THE INVENTION The present invention relates to electro-mechanical accounting devices for vending -mechines and thelike and particularly to combined permanent accumulator means and associated electrical driving circuits therefor. It is especially adapted for the counting of digital pulses representing deposit of coins or like tokens of different denominations and more especially to operate with relatively standard'c'ircli'it modules and components, and/or interface with relatively conventional coin-operated mechanisms and associated power supplies to activate relatively conventional mechanical counter means; and particularly to do this with reason able efficiency and low cost means which are nonetheless of high reliability and which are immune to typical noise pulses and difficulties assocciated with pulse transients, power interruption and other abnormalities such as occur during start-up and shut down.

BACKGROUND OF INVENTION Workers in the art of detecting and counting pulses received from token register units (e.g. coin injection and/or currency injection switch means, such as for a coin-operated record player'machine) are familiar with such problems as over-extended input pulses (e. g. from a hung" switch), noise pulse, and transient pulse conditions, like the sharp, brief high voltage spikes generated when power supply abnormalities or interruptions occur (e.g. during machine start-up and shutdown). Present conventional mechanisms and arrangements for detecting and counting such pulses(such as conventional solenoid-operated ratchet coin counters) are all too subject to error and malfunction from such causes.

The present invention comprises anelectronic detection and counting circuit which is an improvement over conventional equipment for better handling such pulses and avoiding such problems, as well as providing other improvement features. An embodiment system converts signals generated from a vending machine coin entry stage into transactional signals stored and processed in electronic (buffer) memory, and pulsegenerating units. These are arranged'in turn to drive accumulator storage means such as a mechanical counter which provides a permanent non-volatile talley of all revenue received. I I

Such a combination of electrical signal processing means and non-volatile accumulator means is much needed in the present state of the art. For instance, such non-volatile accumulators; which-are not affected by interruption or loss of electrical power or other signal abnormalities (as electronic means typically are), are needed as income totalizers to verify the correct, complete revenue received in a vending machine principally as a check onthe honesty and/or accuracy of the attendant servicing the machine. At-present, some operators try to do this by simply monitoring the flow of merchandise through a vending machine, but this is often unsatisfactory for two reasons: some machines. such as coin-operated phonographs or gaming machines, have no such merchandise through-put"; Others do. but present a temptation to the attendant to stock the machine (at least in part) with his own merchandise and return revenue to his principal only on the principals merchandise.

OBJ ECTS Thus, it is an object of the present invention to meet at least some of the foregoing needs and drawbacks in the present state of the art and provide at least some of the foregoing features of novelty and advantage. A related object is to do so by providing non-volatile accumulator means for tallying vending machine revenue combined with electronic signal buffer storage and processing means for indexing the accumulator means in a reliable, compact, reasonably inexpensive fashion. A further object is to provide this using an electromechanical counter as an accumulator, driven by an electronic pulsing stage which also drives any electronic clearing stage and in turn is driven by an electronic signal processing and buffered-memory stage. Yet a further object is to provide the foregoing implemented in integrated circuit modules.

Yetanother object is to provide the above accumulator andelectronic driving means in the form of an electronic signal processor driving an electronic countregister together with associated pulsing means and digital servo arrangement to drive the accumulator as well a reset the count-register.

I Yet a further object is to provide this using .electromechanical counter means as an income totalizer driven by electronic transaction registering circuits responding to coin entry in a coin-operated vending machine. I

Stillanother related object is to provide the foregoing as a non-volatile income totalizer for use with vending machines having multi-denomination input signals (e. g. from different denomination tokens, such as coins and bills) as well as cancellation capability.

Yet another object is to provide the foregoing using an electronic register and associated digital servo means with a gate-controlled multivibrator stage to drive the accumulator and reset the register.

- Still a further object is to provide such an accumulator together with an electronic transaction registering circuit means adapted for buffer memory for gated count-pulse issuance and for an associated circuit clearing function.

' Still a further object is to provide this using an electronic transaction totalizer providing input to an electricalaccumulator means and controlled and reset in digital servo fashion.

Still other objects and advantages will become apparent to those skilled in the art upon review of the following description of preferred embodiments of the invention; namely, those skilled in the art to make and use same may consider the following in company with the appended drawings, wherein like numerals refer to like elements.


DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 indicates, in block diagram form, the general arrangement of the subject embodiments involving a multi-input (pulse storage) stage I; a pulsing (gate, pulse generating) stage II; a mechanical counter stage MC and a clearing (sequencing, reset) stage III in a novel combination.

More particularly, the various coin (deposit) registering signals (pulses P-l) are arranged (as further described below in a particular embodiment) to each be applied to a respective memory circuit in stage I. Thus, memory circuits -M, -M, -M, 50-M and 100-M indicate, respectively coin reception and associated pulse generation at the S-cent. lO-cent, 25-cent. SO-cent and $1 coin injunction slots. as well known in the art (and/or as hereinafter described). The "5-cent" memory circuit S-M is typical (the other circuits being substantially the same); wherein a "S-cent deposited pulse is adapted to be appropriately shaped and stored (by capacitor C-3) until registered by indexing of the mechanical counter stage MC. This input pulse is adapted to cause issuance of an appropriate number of counts to stage MC, being controlled by a summing gate SG coupled to drive an associated oscillator unit OS as further described below.

More particularly, the stored (memory circuit) signals are applied to a "NOR gate" 80 which inverts them to, in turn, initiate oscillator OS to function. Thus, for each oscillator output pulse, mechanical counter unit MC is advanced to register an appropriate number of total coinage counts (for example, a S-cent count representing the counting pulse output initiated by a signal from stage S-M; or a IO-cent" count registered in response to a signal from stage l0-M. and so forth). Oscillator OS will run as long as any of the inputs to gate SG remains high" and will terminate when all are dissipated. Each oscillator output pulse will also simultaneously, and synchronously. advance an associated electronic counter stage EC an appropriate amount. Upon completing the respective OSC output series and correspondingly advancing EC (e.g. one unit for each S-cents worth of coins) the corresponding EC output (indicated as "l, 2, 5. l0 and 11"representing, respectively, S-cent, IO-cent, 25-cent, 50-cent and $1 denominations registered in EC) will go high" and then initiate clear; discharging the associated memory circuit. The EC counting output reflecting this state is applied, via an associated clear line, through an inverter l and a diode D to discharge the capacitor at the associated memory stage. Thus, for instance, an oscillator output to EC reflecting a S-cent deposit will produce an output (output 1) along clear lines 5-C. 5-C' through clearance" inverter I and diode D to effectively discharge capacitor C3 and thus clear memory circuit 5-M as further described below. This output signal clearing memory will disable summing gage SG (no other input remaining at 80) such that its output will thereupon shift (high) to disable oscillator OS and so terminate the counting output and stop indexing the mechanical and electronic counter means.

This clear function will, in turn, act to cause Reset of the counting system, via Reset multivibrator R. For instance, in the case of a 5-cent deposit, a clear pulse along lines S-C. S-C will also apply a signal to activate a reset ouptut from reset multivibrator R. serving to 4 restore electronic counter EC to its "zero" state in preparation for beginning the next count.

Now. the mechanical counter stage MC will carry a "Total Count" incremented by the denomination of each deposited coin"(represented by an associated input pulse received by the coin injection mechanism as known in the art but not shown in detail here). Details are explained elsewhere. but the "S-cent deposit" will be understood to generate an appropriate signal to activate an associated input means "I-SW". as seen in FIG. l-A (e.g. close a switch) to couple the associated (+5VDC) input pulse to memory unit S-M. Here. the counter MC is preferably a type which is advanced one count unit for each 5-cent value deposited for instance a 35-cent deposit would be represented by a count of 7 units at MC. Counter MC can. of course. be otherwise converted to indicate dollars and cents directly, or to any other suitable code as known in the art. The use of the mechanical counter stage MC as a "totalizer" is necessary (as seen below) to prevent a loss of count when AC power is interrupted or other difficulties are encountered and so provides a non-volatile" memory function.

An interesting feature of the subject improved electronic counting arrangement is that if the arrangement registers simultaneous coin deposits to the memory circuits, it will nonetheless sequence these. to correctly count each input in turn. starting with the lowest denomination and finishing with the highest. That is. if 5-cent and IO-cent pulses were received relatively simultaneously at memory stages S-M. l0-M, respectively. the system would operate to register the 5-cent denomination first at counter MC and then pick up the lO-cent count to register this automatically. clearing the input memory stages successively in order of denomination. As will be appreciated by those skilled in this art, to perform this and other functions described herein with the simple circuitry of the subject design is a rather surprising and advantageous achievement.

DETAILS OF CIRCUIT EMBODIMENTS INPUT. MEMORY Details of the arrangement in FIG. 1 generally described above will now be given. FIG. 2 shows a schematic circuit diagram of the generalized arrangement of FIG. 1. Here, it will be appreciated that. according to one feature, the S-cent, lO-cent. 25-cent and SO-cent memory circuits are all similar (with the $1 circuit being varied somewhat as described further below in connection with FIG. 3) and that except for storage capacitors (C9. C10, C11 and C12), the component values may preferably be identical and perform the same function. Of course. it is presumed (as further described below) that the input pulses representing the several coin denominations will preferably be substantially identical nominal 5-volt pulses of about 2 milleseconds duration (up to about 30 milleseconds is possible, with an infinitely-long pulse being accommodated as further described below). The coin received" pulse will be applied to charge the respective capacitor e.g. capacitor C9 is charged upon applica: tion of a S-cent received signal to associated memory stage S-M.

Thus, in exemplary memory circuit S-M the input pulse is capacitively coupled via limiting capacitor C1 to associated memory capacitor C9. C1 serves to clip" an extended input pulse, assuring that only a single pulse." charge is fed through. If. for instance the "nickel slot" switch (see FIG. 4) gets hung-up and applies a long, extended input pulse, then only a single input pulse (rather than several) will be registered in memory S-M. This limiting capacitor also serves, during clear mode, to assure that memory capacitor C9 may be discharged. The signal is further coupled through isolating stage Rl-CS which serves to decouple the memory circuit from the input circuit and to filter-out certain brief transient noise pulses (those too brief to survive this R/C delay).

The input is then coupled through a timing resistor R9 and a clamping diode CR-l to storage capacitor C9. Capacitor C9, together with R9, comprises an R-C delay circuit having a time constant which establishes a minimum time period required for charging the capacitor C9. The junction between C5 and R9 is coupled to ground through resistor R5 for discharging the circuit in case of a very long input pulse and to establish a zero voltage reference (or quiescent level) from which C9 may be charged.

Diode CR-l is back-biased to assure that the charge will remain locked-up on capacitor C9 for the memory cycle until cleared. The junction between CR-l and C9 is coupled to ground through an isolating resistor R13 of high enough impedance to assure that capacitor C9 will not be discharged except over an extremely long time period (an RIB-C9 time constant of approximately 2 seconds is suitable here) long enough to complete the count and terminate the memory cycle by eventually discharging C9 when the counter circuit, etc. is disabled, leaving a charge at C9 for an overlyextended period. The foregoing digitized, multiline input is applied in parallel to trigger counting pulses until cleared.

DOLLAR INPUT FIG. 3 shows the input-memory circuit for registering $1. It is modified somewhat from the input circuits shown in FIG. 2 and described above. Here, the input circuit array operates similarly to apply an input pulse from pin 9 to storage capacitor C-l3. It is thereafter applied to a first multivibrator stage MV-A and then, in turn, to a second multivibrator stage MV-B. This input is capacitively coupled, filtered and clamped as before.

It will be understood that the first multivibrator stage MV-A is initiated by application of a $1 deposit pulse, stored at capacitor G13, and provides a relatively long (e.g. 1 second) pulse output from initial amplifier Za. This pulse initiates multivibrator stage MV-B, being coupled thereto via an isolating diode CR'-2 and a capacitor C'5. Inverter will produce an inverted output applied to initiate its complementary inverter Z11 which, after a suitable delay, will produce an inverted output of sufficient duration and magnitude to simulate" a SO-cent pulse applied to summing gate SG.

Note that (FIG. 3) the first single-shot multivibrator MV-A is capacitively coupled to the second one-shot vibrator MV-B and arranged so that the first output is separated enough (preferably about 1 second) from the second output so that the first may be registered, cleared and reset before the second is emitted both appearing, successively, as 50-cent inputs at terminal 12 of summing gate SG.

Vibrator MV-B is conventionally connected to be self-resetting" so as to terminate its output and reset itself for a following initiation this second initiation occurs through prolongation of the pulse applied from initial inverter 20 to emit a second 50-cent pulse in the manner of the first after a suitable delay. This delay approximates the time for counting and clearing the first SO-cent pulse from multivibrator MV-B. MV-B is finally reset and cleared, with reset being assured by the inverted output from complementary stages Zb in the first multivibrator MV-A, applied via diode CR3 and coupling capacitor C6 to stage Zc, as known in the art.

PULSE STAGE A coin pulse applied from one or several memory circuits is applied as an input to summing gate Sg which provides an enabling output (inverted polarity) to initiate counting pulses from oscillator stage OSC as further described below. Gate SG preferably comprises a digital integrated circuit (monolithic silicon) in the form of a known cos/mos, NOR gate (positive logic as in FIG. 5) functioning so that one or more +5 volt inputs causes a transition in its output, from about +'5 VDC down to about 0 volts DC. This activates oscillator OSC, coupled via clamping diode CR-12, which results in going high and disabling OSC when all inputs (on SG) have disappeared. Gate SG also functions to amplify in the manner of an astable multivibrator with a high impedance and low output impedance.

Workers in the art will recognize that such cos/mos modules (or complementary mos circuits P and N complementary transistors on a single chip) have several known advantages for such an application. But a particular advantage herein is the high input impedance, permitting relatively long extended input pulses, as well as very good noise immunity (i.e., a narrow voltage-switching window, with very low incidence of switching jitter; that is, having a very narrow transition voltage margin between two definite switching states). For instance, in this case the preferred embodiment exhibits a zero state, from 0 to about 2.7 volts DC and a one" state from 2.9 to 5+ volts DC, with a very narrow indeterminate state from about 2.8 to 2.9 volts DC a narrow margin that gives little indeterminate switching or jitter. Other advantages exist for such cos/mos logic as used here and elsewhere in this circuit: it can serve many functions, for instance, to gate, to amplify, to switch and to provide signal generation functions. This is opposed, for example, to TTL logic (which tends to draw current continuously) and unlike n-mos/p-mos logic which have relatively high transistor density and require a supplemental power supply. Workers will be especially impressed by the advantage of noise immunity and of high input impedance for obvious reasons.

Oscillator stage OSC in FIGS. 1 and 2 will be seen as free-running to effectively convert (until terminated) the monolithic output from gate into an appropriate series of suitably-long, shaped, amplified clock pulses" to activate both the mechanical and electronic counter stages MC, EC, respectively; and it will continue to do so according to a feature hereof. until terminated by removal of all enabling input signals to SG and consequent reversion to its high output. In particular, it will be understood that the output from multivibrator OSC is adapted, when coupled properly to a mechanical counter, to count-in value-pulses" (i.e., representing coin denomination), the OSC output pulses being sufficiently extended to activate counter MC, yet cut-off quickly enough to allow the counter solenoid to execute its characteristically-slow springreturn in preparation for a following count.

Thus, as seen more specifically in integrated circuit form in FIG. 6 (monolithic silicon cos/mos NAND gates using positive logic), this OSC stage essentially comprises a pair of complementary first and second inverter-amplifier stages Z3, Z3, respectively, functioning when properly initiated as an astable multivibrator with a time constant determined by an appropriate RC circuit (R25, C19 as known in the art). More particularly, a negative-going output of proper magnitude from gate 56 is coupled through latching diode CR12 to the input of first inverter Z3. It will induce a positivegoing output from Z3 adapted to initiate second inverter stage Z3 which, in turn, produces a negative-going output to be coupled to initiate the mechanical and electronic counter stages.

As will be further described, and as understood in the art, these counter stages are thus indexed by a series of periodic clock pulses of proper voltage polarity, magnitude, shape (square) and width. It is a particularly important feature of this arrangement that these pulses are kept brief enough to allow initiation of the counter solenoid SOL (of mechanical counter MC) and then disabled for a period sufficient to allow spring-restoration. In this particular case, output pulses from OSC are preferably on the order of 25 to 30 milliseconds long, with an 80 millisecond relaxation time separation, and thus adapted to issue every 1/13 second continuing to issue as described below until gate SG is disabled by the clear output from electronic counter EC. Thus, the time constant established by RC delay circuit R25, C19, will operate to provide such a train of brief output pulses with relatively long time separation the brief pulse to pull-in the solenoid and the long one to allow (spring) return. Diode CR 12 serves to disable the oscillator and maintain it latched in that condition, despite current leakage, etc., until enabled (SG output transition).

. MECHANICAL COUNTER Oscillator stage OSC is coupled operatively to advance mechanical counter stage MC through a switching transistor network. More particularly, the output from stage Z3 is coupled through a suitable RC chaping filter circuit (R26, C24) to the base of an appropriately-energized switching transistor Q1 for enablement thereof; the output from Q1 is emitter-follower coupled to the base of a complementary switching transistor Q2 for enablement thereof. This switch network provides a brief switching pulse down through the counter solenoid SOL responsive to receiving a clock pulse, thereby pulling the counter arm sufficient to trip the mechanical counter wheel and increment it one unit, as well known in the art. This counter preferably comprises a known solenoid-operated ratchet type (requiring about 30 volts DC to actuate it) which serves to advance its counter wheel one unit for each output pulse from oscillator OSC. Thus, in the case of a S-cent input pulse to associated memory 5-M, this is coupled to gate SG to start oscillator OSC. OSC, in turn, applies a single output pulse to advance the counter solenoid SOL which advances the wheel one unit (a S-cent value) and similarly increment electronic counter stage EC. Before any further pulses issue from OSC, counter EC having incremented to throw its 1 output high (along clear line) will clear the S-cent capacitor C-9 and so disable its input to SG, thus disabling OSC before a second output pulse can issue.

8 A diode CR17 clamps the solenoid SOI. so that no high voltage spikes can be transmitted and applied to transistor O2 to possibly damage it. A load resistor R34 is coupled in series with coil SOL to the power supply (24 VAC) via isolating diode CRIS which is configured and valued to dissipate solenoid current relatively quickly, allowing SOL to be quickly returned. A capacitor C25 is inserted in parallel across the counter energizing circuit to ground as a means of storage and leveling of input AC power. For instance, if input power is switched-on at a time (typically very brief) coinciding with the low voltage portion of the AC power cycle, enough power will have been stored in capacitor C25 to smooth out this phase variation and supply sufficient interim charge to the solenoid to activate it.

ELECTRONIC CLEARING STAGE Electronic clearing stage EC is, as mentioned, also coupled and adapted to be appropriately incremented (preferably in 5-cent increments) by the output clock pulses from oscillator stage OSC. As seen, for instance, more particularly in the schematic logic diagram of FIG. 7 and associated timing diagram FIG. 8, stage EC comprises a S-stage Johnson decade counter and output decoder adapted to be advanced one count for each positive (clock) signal input transition. A reset signal is adapted to clear counter EC and reset it to its initial (zero) stage. Such a decade counter configuration permits high speed operation and spike free" decoded outputs with anti-lock gating to assure proper counter sequence. The 10 decoded outputs are normally low and go high only during prescribed respective time-windows, remaining high only until the clock cycle is finished.

As workers in the art will appreciate, the oscillator output from stage OSC thus serves to clock the operation of counter EC. As further described below, any one of the respective outputs from counter EC will be applied along a respective clear line via inverter I and associated diode D (see FIG. 1) to an associated memory line to discharge the pulse-storing capacitor in the associated memory stage and disable its input to SG and OSC also applying a reset pulse through stage R to effect reset of counter EC, and doing so before the next output pulse issues from OS (to properly terminate OS output on clearing the last remaining input to SG). Thus, the counter is self-resetting according to another novel feature hereof. For instance, when a S-cent input pulse is applied to memory stage S-M to enable gate SG and oscillator OSC, the oscillator output advances electronic counter stage EC to its 5-cent output (terminal 2, which will then go true or high, this being applied in turn along an associated clear line to clear memory 5-M through associated inverter gate Z4 and clear diode CR-7. This EC output not only discharges capacitor C9 and disables gate SG (to terminate oscillator output) but also, according to this feature, is applied through an appropriate portion of reset stage R to reset counter EC. This brings all EC output conditions to a low state, with the zero state then going high. Of course, other electronic clearing-sequencing means may be used, but the subject type as indicated in FIG, 8 and FIG. 9 is preferred because it has the unique ability to correctly count simultaneous inputs.

Counter EC is adapted to not only clear input memory, but also sequence counting in prescribed order (here, the order of lowest input denomination, this being the temporal order of EC incrementing). Suppose a S-cent and IO-cent input arrive relatively simultaneously and the l-cent input gets through gate SG first to start a chain of pulse s'froin OSC. Theyfirst start to advance counter EC whereupon its S-cent output will come high and serve to disable and discharge memory S-M well as reset EC. Here, the pulse stage (SG- OS) will just continue to operate, with the l0-cent input pulse remaining on. gate SG;'oscillator OSC will continue to issue another S-cent output pulse, followed by a second -cent pulse (to MC and EC) until EC output No. 4 terminates OSC by discharging memory l0-M and thus removing all input from gate SG, causing it to revert high (output).

RESET Turning to reset state R. it will be seen as comprising essentially a reset multivibrator 'MV-l, preferably of the type indicated before as oscillator ()SC (FIG. 6) and adapted to apply a suitable reset pulse to reset terminal of counter EC when energized by the output from an associated swithcing gate Z2. Gate Z2 is preferably of the type indicated at FIG. 5 for gate 80 mentioned above and is coupled toMV-l through an RC storage network (R-23, C18). Appropriate inputs are provided from each memory line (e'.g. S-Lm, FIG. 2) to gate Z'2 through a respective inverter gate Zl and RC difi'erentiating network to enable gate Z2. The Z2 output is applied to storage capacitor C18 which holds the input high' long enough to initiate MV-l.

Thus, for instance, for a -cent input pulse with the 25-cent charge in assoiciate'd storage capacitor Cll, cnablement of gate SG and oscillator OSC will apply a series of (five) clock pulses to the counter stages, so electronic counter EC will be advanced sufficient to' bring its 25-cent output high (terminal 1 going high). This EC output is applied and inverted through Z4 diode CR9 to discharge capacitor Cl 1 and disable gate SG and oscillator OSC thus terminating the pulse count at a total of five, while alsoapplying a reset pulse to stage R: This reset pulse is applied through an associated inverter 21 to produce a positive-going pulse, differentiated by network Cl6/R2l to produce a pulse which can enable gate Z2 to produce a negative-going output pulse of limited duration. This output, in turn, initiates stage Z3 of multivibrator MV-l (a one-shot monostable multivibrator) which, in turn, issues a positive-going output pulse (preferably about 5 volts DC and 0.] millisecond duration) to reset EC to zero state at terminal 15. More particularly, when the trailing edge of the negative-going pulse discharging memory capacitor C II is received at inverter Zl it'will generate a positive-going pulse, the leading edge of which will be differentiated by the RC network andapplied to immediately enable Z2 to reset counter EC.

In this manner and according to a novel feature, reset stage R assures that with the completion of a counting sequence after counter ECclears associated memory and terminates the counting oscillator sequence, counter EC may be automatically reset so that the next memory pulse input begin {its counting sequence anew. In this fashion it is assured that individual memory pulses are counted separately and in order (of increasing denomination). For instance, a ZS-cent pulse would not be confused with two lO-cent and one S-cent pulse, since the first would constitute a single counting sequence and the second three such sequences! The significance and value of this will be evident to workers in the art.

In summary, clearing stage EC, together with reset stage R, serves to clear memory, and finally terminate counting, while also sequencing counting operations and separating them so that only the proper number are issued to advance the mechanical counter. This is a novel feature and it is implemented with particularly convenient and reliable integrated circuit (COS/MOS) means as workers in the art will appreciate. Note that the memory discharge and reset also occur very quickly, within the 1/13 second counting cycle (one count) of the subject system, according to an advantageous feature hereof.

Reset stage R also includes a restore sub-circuit portion R-S essentially comprising a storage capacitor C22 connected between a suitable positive voltage supply and a pair of oppositely poled diodes CR13, CR14 coupled to ground. C22 is also coupled through diode CR18 to the multivibrator oscillator stage OSC. The principal function of this restore circuit is for periods of power anomalies when the power is first turned-on or when power is interrupted even temporarily. Such cases are all too frequent and this circuit will function to restore the electronic counter EC to its zero state (that is, with a high, or 5-volt pulse, a teminal 15) at these times, so counting may be resumed.

That is, after power interruption, it is essential to have the counter EC start back at zero. Circuit RS will assure this after a prescribed minimum interruption time, as well as serve to disable the oscillator OSC until a new input is received.

The circuit has a time constant such that the counter EC may be maintained in reset mode for about 3 seconds to allow for brief power abnormalities such as occur during start-up with the subject counter arrangement, and/or with other operating conditions such as during ignition of a fluorescent light system on the power line (machine may be acting abnormally during start-up). The circuit thus provides an immunity to such noise and power abnormalities. Restore capacitor C22 is additionally coupled to oscillator OSC to inhibit its operation during such power-off periods, when counter EC is being reset, so that during these times mechanical counter MC will not be operated (i.e., not until EC is ready to be operated too and thus track" the counts into MC so as to finally terminate it properly).

Thus, if the voltage level input at +V drops, diode CR14 will tend to maintain the charge in restore capacitor C22, and the time constant established by C22 with R28 (preferably about 3 seconds) will be such as to override normal transient power abnormalities, while the power applied through diode CR13 will reset EC at terminal 15 after this delay period (maintain it at its high zero value).

COIN INJECTION MECHANISM Workers in the art will be generally familiar with typical coin injection mechanisms apt to be used with the subject invention for instance, when the invention serves as a coin counter supplement to an existing coinoperated mechanism arranged to accept a plurality of different denomination coins each coin being injected down a separate coin chute (slot) to trigger a respective coin received switch as known in the art. Such a coin injection and switching arrangement is indicated by way of example in FIG. 4 where a S-cent coin is shown dropping down a chute to close an associated latch and send a signal (25 volts DC or AC is typical) down a preexisting line MC of the machine. This line MC is indicated as being adapted to include a reed switch RS arranged such that a coin received current pulse down line MC will, in turn, activate an associated 5-cent counting pulse here shown as being conducted from a +5-volt DC source to capacitor C1 of memory circuit S-M. Workers will visualize other like means for generating such counting pulses.

SUMMARY To summarize the operation of the foregoing embodiment in FIGS. 1 and 2, the injection of a S-cent coin will trip the preexisting latch and, via the reed switch, provide a 5-volt pulse applied to memory stage 5-M (FIG. 2) where it is stored as a count pulse at storage capacitor C9; and, applied to summing gate 50, it will cause a transition and in turn activate oscillator stage OSC to emit one pulse. This pulse will advance mechanical counter stage MC by one unit and likewise increment electronic counter stage EC by one unit, whereupon the associated EC output will be suitably coupled back as a clear pulse to discharge capacitor C9 and disable gate 50 and oscillator OSC. This clear pulse will also be applied to activate reset stage R, triggering summing gate Z2 to apply an output to energize reset multivibrator MV-l which resets counter EC, thus applying the appropriate reset voltage to terminal 15 thereof.

For instance, if 5-cent and lO-cent inputs hit 80 simultaneously, the system will count the lower denomination signal first (5-cent) because no matter which one is taken first to stimulate oscillator OSC, once the 5-cent output on terminal 2 of counter EC is applied back to terminal 11 on gate SG, the capacitor C9 of the S-cent memory will be cleared first. Counter EC thus, itself, establishes a herarchy of clearing order from low denomination to high. Once the 5-M memory is thus cleared, the l-M memory will of course still be fully valid, and impress its charge on gate 50. thereby stimulating oscillator OSC to emit two pulses counting down counter EC with a clearing output from associated EC terminal 4 (passing terminal 2 with no effect since -M has already been cleared) to then clear capacitor C10 of memory l0-M and terminate the oscillator OSC finally.

Other operative factors of the subject embodiment will be understood by those skilled in the art as novel and advantageous as well as being feasible for implementation with some or all of the arrangements modified within the scope of the appended claims. In any event, it will be seen as novel and advantageous to provide such features, alone or together. as: coupling a coin reception pulse to a mechanical counter stage through an electronic counter circuit to clear and sequence counting input; providing capacitive input pulse storage for each of the coin received pulses and gating them through a common summing gate to operate a count-issuing oscillator. with the oscillator being electronically controlled to limit its output to a mechanical counter representing the value of the total in received coin denominations: or arranging the electronic counter and memory to count-in these pulses in order of increasing denomination (or any order accord ing to the electronic counter's order and associated coupling to the memory stages associated). This system is especially and further novel in also providing a reset 12 arrangement adapted to reset the electronic counter means after each such memory-clearance thereby. Further novelty and significance will be seen in the particular associated circuit features impelemented as gating, pulse generating and amplifying-inverting modules of COS/MOS digital integrated circuit units.

As workers in the art will contemplate. other electronic and mechanical components may be used with the claimed concepts. For instance. other analogous counters, pulse generators, gating means and the like may be used and, where appropriate, ultimate elements substituted.

What is claimed is:

1. An electronic counting circuit for receiving a plu rality of like input signals on a plurality of different respective input terminals, each terminal and associated signal representing a different coin denomination, the circuit comprising in combination therewith:

a plurality of input storage means, one provided coupled to each respective said terminal for storing input signals received at said respective terminal;

mechanical counter means;

free-running pulse generating means coupled in common to be energized by said storage means, said pulse generator being responsive to signals stored in said storage means for issuing output counting pulses until the signals stored in said storage means are cleared therefrom by applied clearing signals. each counting pulse representing the lowest coin denomination or a multiple thereof. said pulse generating means applying said output counting pulses to said counter to advance said mechanical counter means accordingly; and

electronic clearing means including a digital counting circuit having a prescribed number of counting states and associated output terminals which are successively driven to produce predetermined output signals in accordance with the counting state of said counting means. said terminals each being coupled to a respective one of said storage means through a prescribed coupling circuit; said counting circuit being coupled to said pulse generating means for receiving said counting pulses. said counting circuit being incremented thereby to responsively sequence itself through said counting states to successively apply said predetermined output signals to said respective storage means as clearing signals thereto whereby a clear signal is successively impressed. in turn, upon each of said associated storage means for clearing the storage means to reflect receipt of associated counting pulses corresponding to the coin denomination represented by the storage means.

2. The combination as recited in claim 1 wherein said storage means comprises capacitive storage circuit means. one representing each associated coin denomination; plus an associated filtering circuit for discriminating pulse length and maintaing said charge.

3. The combination as recited in claim 1 as adapted to interface with electromechanical coin-registering apparatus including a plurality of coin-receiving slots and associated latches adapted to receive and automat ically indicate the reception of respective coins. said latches being coupled to, in turn. provide an associated input pulse on a respective terminal coupled thereto.

4. The combination as recited in claim 3 wherein each said terminal associated with each latch in nonohmically coupled to said receiving signal line so as to l3 present a coin-received signal of prescribed value upon said terminal and associated storage circuit.

5. The combination as recited in claim 4 wherein said plurality of slots, latches, input terminals and storage circuits are provided to indicate 5'-cent, l0-cent, 25- cent and 50-cent coin denominations; and wherein there is further provided a $1.00 input latch means and associated input terminal, together with associated storage circuit means comprising capacitive storage means, associated filter circuit means and a pair of multivibrator stages arranged in series-and adapted to issue a pair of pulse simulating successive SO-cent signals. v

6. The combination as recited in claim 2 wherein said pulse generating means includesNORwsumminggate means together with astable multivibrator: means cou pled to be initiated by said summing gate and, in turn, coupled through a switching circuit .to said-mechanical counter means. I

7. The combination recited in claim 6-wherein said mechanical counter comprises a solenoid-operated ratchet including a spring-returnsolenoid.coupled to be energized by said multivibrator through a transistor switching-isolation circuit; said multivibrator being adapted to. provide relatively brief output counting pulses separated by a relatively extended intermediate delay period adapted to allow recovery'of said Solenoid. I v

8. The combination as recited in claim 7 wherein said summing gate and said oscillator comprise cos/mos integrated circuit modules, said summing gate compris ing a high input impedance/low output impedance multivibrator.

9. The combination as recited in claim 2 wherein said clearing means includes a digital multi-stage decade electronic counter circuit including output terminals coupled to discharge and clear respective storage capacitor means; and adapted, when activated, to thereby dissipate the input signal therein and terminate said oscillator and associated counting pulses, to thereby sequence the clearance and counting of input pulses in prescribed order.

10. The combination as recited in claim 9 wherein said output terminals are arranged to become activated in order of increasing denomination and are coupled to respective storage means through a respective inverter stage.

ll. The combination as recited in claim 10 wherein said decade counter circuit comprises an integrated circuit module with decoded output terminals arranged to become energized only for the duration of each clock cycle, said count pulses being coupled thereto to establish said clock cycle.

12. The combination as recited in claim 8 wherein said clearing means also comprises a reset circuit arrangement connected in common between all of said storage means and the reset terminal of said counting circuit and adapted, upon clearance of said storage capacitor, to reset said counting circuit to its zero state" when the capacitor is discharged.

13. The combination as recited in claim 12 wherein said reset means comprises gating means connected in common to said storage means and pulse generator means coupled between said counting circuit and said gating means and adapted to issue a prescribed reset pulse upon enablement of said gating means.

14. The combination as recited in claim 13 wherein said gating means comprises a summing gate in inte- 14 grated circuit cos/mos form and said pulse means comprises an integrated single-shot multivibrator circuit.

15. The combination as recited in claim 13 wherein said reset means further includes capacitive restore circuit means adapted to reset said counting circuit to zero state upon interruption of electrical power beyond a prescribed minimum time period.

16. An electronic circuitfor counting the total value of coins therein introduced over an extended period of time encompassing many coin operated vending transactions, comprising:

a. an input means settable to a predetermined state in response to the introduction of a coin of predetermined denomination;

b. a pulse generator connected to the input means and responsive to the input means when it is in said predetermined state for generating electrical pulses;

c. a non-volatile mechanical counter connected to the pulse generator and responsive to each pulse of the pulse generator for advancing one digit for each pulse, said non-volatile counter mechanically maintaining without electrical power requirement its attained count after completion of every coin introduction to continually maintain a cumulative count representative of the cumulative total of all pulses-produced by the pulse generator; and d. a feedback means interconnected between the pulse generator and the input means and responsiveto a predetermined number of pulses of the pulse generator for resetting the input means whereby the pulse generator ceases the generation of pulses and the input means is made available to register the introduction of a subsequent coin.

17. An electronic circuit as in claim 16 wherein the input means is a memory circuit having a storage capacitor and the feedback means is a self-resetting nonmechanical switch operable for momentarily connecting the storage capacitor to a predetermined discharge potential to discharge said capacitor.

18. An electronic circuit as in claim 16 wherein the input means comprises;

a. a plurality of memory circuits, each such memory circuit having a storage capacitor and each such memory circuit devoted exclusively to the introduction of coins of a single denomination; and

b. a summing device having an input connected to each memory circuit and having a single output.

19. An electronic circuit for counting coins therein introduced, comprising:

a. an input means settable to a predetermined state in response to the introduction of a coin, said input means comprisinga plurality of memory-circuits, each such memory circuit having a storage capacitor and each such memory circuit devoted exclusively to the introduction of coins of a single denomination, and further comprising a summing device having an input connected to each memory circuit and having a single output;

b. a pulse generator connected to the input means and responsive to the input means when it is in said predetermined state for generating electrical pulses;

c. a mechanical counter connected to the pulse generator and responsive to each pulse of the pulse generator for advancing one digit for each pulse; and

d. a feedback means interconnected between the pulse generator and the input means and responsive to the pulses of the pulse generator for resetting the input means, whereby the pulse generator 16 coin operated vending transactions, each of a plurality of difierent denomination coins accepted by the device being represented by the momentary appearance of a respectively corresponding input signal on a respecceases the generation of pulses and the input means 5 tlvely corresponding terminal of a plurality of input is made available to register the introduction of a terminals, said income totalizer comprising: subsequent coin, said feedback means being a selfan electronic counting and clearing circuit which is resetting, non-mechanical switch operable for mocoupled to each of the plurality of input terminals mentarily connecting a selected storage capacitor to receive the corresponding input signals, said to a predetermined discharge potential to diselectronic counting and clearing circuit including charge such capacitor, said feedback means coman electronic register normally in an initial countprising a resettable counter having a multiplicity of ing state and responsive to each of said input sigelements, one such element being associated with nals for setting to a corresponding state representaeach memory circuit and each such element repretive of the denomination of the corresponding coin, sentingacount proportional to the coin denominasaid electronic counting and clearing circuit furtion of the memory circuit with which it is associther including means responsive to the input signals ated and each such element responsively providing and the counting state of said register for produca momentary discharge path for the storage capaciing a number of electrical output pulses representator of the memory circuit with which it is associ- 20 tive of the denomination of the corresponding coin ated when the count it represents corresponds to and for clearing said register to its initial state; the number of pulses of the pulse generator and a non-volatile mechanical output counter responsive further including a reset device interconnecting the to each of said output pulses for advancing a prederesettable counter and the output of the summing termined increment, said non-volatile mechanical device and responsive to the discharge of any of the counter mechanically maintaining its cumulative storage capacitors for resetting all the elements to attained count after every coin acceptance and a zero count. throughout electrical power stoppages to continu- 20. A coin income totalizer for continually maintainally maintain a cumulative count representative of ing a count representative of the cumulative total of the the cumulative total of all of said electrical output value of all coins accepted by a coin operated device pulses. over an extended period of time encompassing many

Citas de patentes
Patente citada Fecha de presentación Fecha de publicación Solicitante Título
US3182121 *22 Jun 19614 May 1965Paramount Picture CorpSubscription-television receiver having rate set by program selector
US3307671 *12 Abr 19657 Mar 1967H R Electronics CoCoin controlled means
US3815717 *10 Oct 197211 Jun 1974Arkorp IncElectronic coin changer control circuit
Citada por
Patente citante Fecha de presentación Fecha de publicación Solicitante Título
US4306219 *26 Mar 198015 Dic 1981Micro-Magnetic Industries, Inc.Vending machine acquisition system
US5109972 *24 Jul 19895 May 1992Duncan Industries Parking Control Systems Corp.Coin operated timing mechanism
US5477952 *11 Mar 199326 Dic 1995Compuline, Inc.Retrofittable universal secure activity-reporting electronic coin tracker for coin-operated machines, particularly for detecting embezzlement of monies collected by video games
Clasificación de EE.UU.453/58, 194/216
Clasificación internacionalG07F9/08, G07F5/22, G07F5/20
Clasificación cooperativaG07F5/22, G07F9/08
Clasificación europeaG07F9/08, G07F5/22