US4089992A - Method for depositing continuous pinhole free silicon nitride films and products produced thereby - Google Patents
Method for depositing continuous pinhole free silicon nitride films and products produced thereby Download PDFInfo
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- US4089992A US4089992A US05/718,720 US71872076A US4089992A US 4089992 A US4089992 A US 4089992A US 71872076 A US71872076 A US 71872076A US 4089992 A US4089992 A US 4089992A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/34—Nitrides
- C23C16/345—Silicon nitride
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/318—Inorganic layers composed of nitrides
- H01L21/3185—Inorganic layers composed of nitrides of siliconnitrides
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/061—Gettering-armorphous layers
Definitions
- the present invention relates to a method for depositing silicon nitride. More specifically, the invention is concerned with the deposition of pinhole-free films of silicon nitride which are especially useful as diffusant masks on semiconductors and other high temperature materials.
- diffusant mask refers not only to a barrier which will prevent the diffusion of substance into a body, but also to a barrier which will prevent the out-diffusion of volatile materials from a body on which it is coated.
- Diffusant masks of silicon dioxide have been widely used and are generally acceptable. However, where highly active doping agents are employed, such as boron, or where relatively thin diffusant masking layers are utilized, problems have arisen due to the permeability of the silicon dioxide and other conventional diffusant masks to the doping agent.
- the primary objective of the present invention is to provide a method for depositing diffusant masks which are impermeable to volatile materials or materials which are volatilized at high temperatures.
- a further object of the invention is to provide a method for depositing thin diffusant masks which are entirely free from pinholes so that impurities are not diffused through the mask.
- Collateral objects of the invention are to provide bodies coated with diffusant masks which resist the diffusion of semiconductor doping impurities into the body as well as the out-diffusion of impurities from the body.
- pinhole-free silicon nitride films may be produced by reacting silicon tetrahydride (SiH 4 ) hereafter called silane, with any nitrogen containing compound which upon decomposition produces nascent nitrogen, such as ammonia, in the presence of any carrier gas that is inert to the reactants, such as for example H 2 , N 2 , A, He, Xe and Kr.
- SiH 4 silicon tetrahydride
- This invention also contemplates substrates coated with silicon nitride diffusant masks produced in accordance with the invention.
- FIG. 1 is a schematic side-sectional view of a horizontal reactor and system for carrying out the film deposition technique of the present invention
- FIG. 2 is a somewhat schematic side-sectional, edge view of a semiconductor device undergoing vapor diffusion through a mask of silicon nitride deposited in accordance with the invention
- FIG. 3 is a perspective view of a susceptor plate having a series of semiconductor wafers positioned on its surface
- FIG. 4 is a side-sectional view along line A-A' of FIG. 3.
- Substrate 10 such as a body of semiconductor or susceptor material to be provided with a diffusant mask, is positioned on susceptor 11 in reaction chamber 14.
- the reactor 14 is in the form of a tube surrounded by a cooling jacket 15 which is provided with inlet 16 and outlet 17 for circulating a suitable cooling fluid. Cooling of the reactor walls inhibits extraneous decomposition of the reaction mixture.
- Susceptor 11 is heated by any suitable means, preferably by coupling with RF power source 12 through coil 13.
- Ports 18 and 19 are provided at opposite ends of the reactor tube for admission of the reactant mixture and removal of gaseous reaction products.
- the reactor is flushed with gas and RF power source is actuated to heat substrate 10 to a temperature above about 500° C and preferably in the range of from about 700° to 1100° C.
- a mixture of the reactants is then introduced into the reactor through port 18.
- a slight positive pressure of reactant mixture input is maintained so that the mixture sweeps continuously over the substrate surface and exits through port 19.
- the reaction mixture is proportioned so that the nitrogen containing compound which upon decomposition produces nascent nitrogen, such as ammonia, or elemental nitrogen is at least present in stoichiometric amount for the formation of silicon nitride (Si 3 N 4 ) by reaction with silane.
- the carrier gas for the reaction inert to the reactants is present in sufficient excess to inhibit the reaction rate.
- the ratio of the silane to ammonia by volume may therefore range from about 3:4 (stoichiometric) to 1:300 or more.
- an inert carrier gas flow rate of at least several liters per minute, preferably 8-20 l/min. provides a satisfactory excess of inert carrier gas. With increased diameter of reactor the flow rate is increased proportionately.
- the excess of such carrier gas is very important. It retards and controls the reaction and serves as a carrier, so that a good gas flow pattern is obtained.
- the gas flow pattern contributes to the formation of a uniform film.
- a silicon substrate is heated to a temperature ranging from 750° to 1100° C., in a reactor as shown in FIG. 1.
- a 1:40 mixture of silane and ammonia is mixed with hydrogen and flowed over the substrate.
- the flow rate of the hydrogen in the mixture is about 4 l/min.
- a film of silicon nitride is deposited from the reaction mixture.
- a film having a thickness of several hundred angstroms may be built up in about 15 minutes of such deposition.
- all conditions were the same except that the hydrogen flow rate was increased to 10 l/min. By increasing this flow more consistent wafer to wafer thickness was obtained in the same deposition run.
- N 2 was substituted for the H 2 carrier gas.
- the reaction was loaded and the system pumped down to 10% pressure.
- the system was filled with N 2 .
- the exhaust was opened and N 2 flow was adjusted to 20 l/min.
- RF power was turned on. Temperature raised to 800°-900° C. Both NH 3 and SiH 4 gas streams introduced and caused to react. Following 15 minutes of reaction and deposition the flow of the reactants was terminated.
- the RF power was turned off, the reactor was unloaded and permitted to cool. A film thickness and silicon nitride again of the order of several hundred angstroms was grown.
- deposition rates of from 100 to 400 angstroms per minute are achieved and pinhole-free, uniform films of silicon nitride having a thickness of from 0.1 to 2.0 microns have been successfully grown on silicon, silicon dioxide, graphite and other substrates.
- the resistivity of such films is in the range of 10 10 - 10 14 ohms per centimeter and the dielectric constant of such films is in the range of from 6 to 8.
- Regions of the semiconductor or other substrate coated by the silicon nitride film may be defined by application of a suitable mask which remains in place during the deposition. After the deposition has been completed, the mask is removed and, as shown in FIG. 2, the assembly may be subjected to a diffusion doping procedure. For example, boron or other semiconductor impurity may be diffused (arrows) into a body of semiconductor material 20 at a temperature of about 1200° for about a half an hour. Due to the pinhole-free condition of the silicon nitride film, the diffusion zone 21 is restricted to the zone beneath the unmasked surface of the semiconductor body. Silicon nitride film 22 entirely prevents diffusion into the underlying portions of semiconductor body 20. The silicon nitride diffusant mask may be removed by slow dissolution in concentrated HF or by reverse sputtering.
- the silicon nitride has masked all the diffusants that have been tried.
- the diffusion conditions, the junction depth and the surface concentration as measured in the unmasked region and the thickness of silicon nitride film used for mask appear in the following Table.
- the above data show that the silicon nitride masks not only the common diffusants such as boron, phosphorus and arsenic, but also gallium and oxygen for which silicon dioxide fails.
- the film thicknesses listed above are by no means the minimum thicknesses required for adequate masking. In other words, there is no indication that the films cannot be thinner than 1200° A for masking boron and phosphorus diffusion.
- the minimum film thickness required to mask most common dopants in silicon and germanium is about an order of magnitude smaller than silicon dioxide.
- Silicon dioxide masks are usually over 2,000 angstroms thick, but the present silicon nitride films are effective at thicknesses of only about 200 angstroms.
- Silicon nitride can be deposited to a sufficient thickness on silicon at 800° C for about 10 to 15 min. for effective masking for most common dopants for silicon.
- For equivalent masking with silicon dioxide it requires 300 min. of steam oxidation at the same temperature (800° C). Sharpness of definition is primarily a function of film thickness and since the film thickness required for silicon nitride is much thinner than for silicon dioxide for equivalent masking effect, the nitride mask will have sharper definition than oxide.
- the present invention has application in the production of improved susceptors, as are used in epitaxial deposition and in systems of the type illustrated in FIG. 1.
- a susceptor as is generally recognized in the art, is a material capable of coupling with RF power to generate heat by induction.
- the susceptor is then inductively heated to the temperature required for the particular deposition.
- the substrates may be a series of silicon semiconductor wafers on which an epitaxial growth of addition silicon is to be made.
- the main susceptor body 40 is provided with an encapsulating film 41 of silicon nitride deposited as described above.
- an encapsulating film 41 of silicon nitride deposited as described above.
Abstract
A substrate article coated with a pinhole free film of silicon nitride produced by reacting silane with a nitrogen containing compound which upon decomposition produces nascent nitrogen and sufficient amounts of a carrier gas that is inert to the reactants and heating said substrate to a temperature above about 500° C to cause the deposition of silicon nitride film on said substrate.
Description
This application is a continuation of copending application Ser. No. 142,013 entitled "Method for Depositing Continuous Pin Hole Free Silicon Nitride Films and Products Produced Thereby" filed May 10, 1971, now abandoned, which in turn is a continuation of copending application Ser. No. 629,338 filed Feb. 8, 1967, now abandoned, which in turn is a continuation-in-part to patent application Ser. No. 494,790, entitled "A Method for Depositing Continuous Pinhole Free Silicon Nitride Films and Products Produced Thereby," filed Oct. 11, 1965, now abandoned.
The present invention relates to a method for depositing silicon nitride. More specifically, the invention is concerned with the deposition of pinhole-free films of silicon nitride which are especially useful as diffusant masks on semiconductors and other high temperature materials. As used in the present context, the expression "diffusant mask" refers not only to a barrier which will prevent the diffusion of substance into a body, but also to a barrier which will prevent the out-diffusion of volatile materials from a body on which it is coated.
In the manufacture of semiconductor devices, such as transistors, it is a conventional practice to dope bodies of semiconductor material with various impurities to impart a desired conductivity to a selected zone within the body. One method for carrying out the doping operation is to diffuse an impurity in the vapor state through the surface of the semiconductor body. In order to restrict the zone which is doped and which therefore has its conductivity altered, it is conventional to mask those portions of the surface of the semiconductor body where doping by vapor diffusion is not desired.
Diffusant masks of silicon dioxide have been widely used and are generally acceptable. However, where highly active doping agents are employed, such as boron, or where relatively thin diffusant masking layers are utilized, problems have arisen due to the permeability of the silicon dioxide and other conventional diffusant masks to the doping agent.
Another problem of diffusion arises in the manufacture of various semiconductor devices by techniques such as epitaxial growth. Such procedures involve the induction heating of a susceptor on which the substrate is placed. Despite attempts to eliminate impurities from high temperature susceptor materials, such as graphite, further out-diffusion of impurities is generally experienced. These impurities contaminate the deposited film and make it impossible to control the properties of the deposit within close tolerances.
Therefore, the primary objective of the present invention is to provide a method for depositing diffusant masks which are impermeable to volatile materials or materials which are volatilized at high temperatures. A further object of the invention is to provide a method for depositing thin diffusant masks which are entirely free from pinholes so that impurities are not diffused through the mask. Collateral objects of the invention are to provide bodies coated with diffusant masks which resist the diffusion of semiconductor doping impurities into the body as well as the out-diffusion of impurities from the body.
According to the present invention, it has been discovered that excellent diffusant masks may be provided by the pyrolytic deposition of silicon nitride (Si3 N4) films. The art has previously recognized that such films may be produced by sputtering. However, none of the prior procedures has provided pinhole-free films which are absolutely necessary to the proper functioning of the film as a diffusant mask.
It has now been found that pinhole-free silicon nitride films, particularly suited for use as diffusant masks, may be produced by reacting silicon tetrahydride (SiH4) hereafter called silane, with any nitrogen containing compound which upon decomposition produces nascent nitrogen, such as ammonia, in the presence of any carrier gas that is inert to the reactants, such as for example H2, N2, A, He, Xe and Kr.
This invention also contemplates substrates coated with silicon nitride diffusant masks produced in accordance with the invention.
The present invention will more fully be appreciated in the light of the following detailed description considered with reference to the accompanying drawing.
In the drawing:
FIG. 1 is a schematic side-sectional view of a horizontal reactor and system for carrying out the film deposition technique of the present invention,
FIG. 2 is a somewhat schematic side-sectional, edge view of a semiconductor device undergoing vapor diffusion through a mask of silicon nitride deposited in accordance with the invention,
FIG. 3 is a perspective view of a susceptor plate having a series of semiconductor wafers positioned on its surface, and
FIG. 4 is a side-sectional view along line A-A' of FIG. 3.
Referring to FIG. 1 of the drawing, there is illustrated a typical system for carrying out the present invention. Substrate 10, such as a body of semiconductor or susceptor material to be provided with a diffusant mask, is positioned on susceptor 11 in reaction chamber 14.
The reactor 14 is in the form of a tube surrounded by a cooling jacket 15 which is provided with inlet 16 and outlet 17 for circulating a suitable cooling fluid. Cooling of the reactor walls inhibits extraneous decomposition of the reaction mixture.
Susceptor 11 is heated by any suitable means, preferably by coupling with RF power source 12 through coil 13.
In operation, the reactor is flushed with gas and RF power source is actuated to heat substrate 10 to a temperature above about 500° C and preferably in the range of from about 700° to 1100° C.
A mixture of the reactants is then introduced into the reactor through port 18. A slight positive pressure of reactant mixture input is maintained so that the mixture sweeps continuously over the substrate surface and exits through port 19.
The reaction mixture is proportioned so that the nitrogen containing compound which upon decomposition produces nascent nitrogen, such as ammonia, or elemental nitrogen is at least present in stoichiometric amount for the formation of silicon nitride (Si3 N4) by reaction with silane. The carrier gas for the reaction inert to the reactants is present in sufficient excess to inhibit the reaction rate.
The ratio of the silane to ammonia by volume may therefore range from about 3:4 (stoichiometric) to 1:300 or more. In a tubular quartz reactor having a diameter of about 5 cm, an inert carrier gas flow rate of at least several liters per minute, preferably 8-20 l/min. provides a satisfactory excess of inert carrier gas. With increased diameter of reactor the flow rate is increased proportionately.
The excess of such carrier gas is very important. It retards and controls the reaction and serves as a carrier, so that a good gas flow pattern is obtained. The gas flow pattern contributes to the formation of a uniform film.
It has been found that the presence of an excess of carrier gas in the reactant mixture causes the deposition of silicon nitride to take place selectively at the region of maximum temperature in the reactor, namely the substrate itself, and results in a pinhole-free film.
In a first example, a silicon substrate is heated to a temperature ranging from 750° to 1100° C., in a reactor as shown in FIG. 1. A 1:40 mixture of silane and ammonia is mixed with hydrogen and flowed over the substrate. The flow rate of the hydrogen in the mixture is about 4 l/min. On contact with the substrate a film of silicon nitride is deposited from the reaction mixture. A film having a thickness of several hundred angstroms may be built up in about 15 minutes of such deposition. In a second example, all conditions were the same except that the hydrogen flow rate was increased to 10 l/min. By increasing this flow more consistent wafer to wafer thickness was obtained in the same deposition run.
In a third example, N2 was substituted for the H2 carrier gas. The reaction was loaded and the system pumped down to 10% pressure. The system was filled with N2. The exhaust was opened and N2 flow was adjusted to 20 l/min. RF power was turned on. Temperature raised to 800°-900° C. Both NH3 and SiH4 gas streams introduced and caused to react. Following 15 minutes of reaction and deposition the flow of the reactants was terminated. The RF power was turned off, the reactor was unloaded and permitted to cool. A film thickness and silicon nitride again of the order of several hundred angstroms was grown.
According to this procedure, deposition rates of from 100 to 400 angstroms per minute are achieved and pinhole-free, uniform films of silicon nitride having a thickness of from 0.1 to 2.0 microns have been successfully grown on silicon, silicon dioxide, graphite and other substrates. The resistivity of such films is in the range of 1010 - 1014 ohms per centimeter and the dielectric constant of such films is in the range of from 6 to 8.
Comparing the properties of the resulting silicon nitride films with those of conventional silicon dioxide films, it has been found that a silicon nitride film having a thickness of 800 angstroms will mask boron diffusion at 1200° C. for 30 minutes. This is a substantial improvement over the masking ability of a silicon dioxide film of like thickness. In addition, a film of silicon nitride deposited in this manner is etched by concentrated hydrofluoric acid at the rate of only 100 angstroms per minute which is a factor 100 times slower than the etching rate of silicon dioxide by the same etchant.
Regions of the semiconductor or other substrate coated by the silicon nitride film may be defined by application of a suitable mask which remains in place during the deposition. After the deposition has been completed, the mask is removed and, as shown in FIG. 2, the assembly may be subjected to a diffusion doping procedure. For example, boron or other semiconductor impurity may be diffused (arrows) into a body of semiconductor material 20 at a temperature of about 1200° for about a half an hour. Due to the pinhole-free condition of the silicon nitride film, the diffusion zone 21 is restricted to the zone beneath the unmasked surface of the semiconductor body. Silicon nitride film 22 entirely prevents diffusion into the underlying portions of semiconductor body 20. The silicon nitride diffusant mask may be removed by slow dissolution in concentrated HF or by reverse sputtering.
Silicon and germanium wafers partly masked with silicon nitride film, as shown in FIG. 2, have been subjected to impurity diffusions. The silicon nitride has masked all the diffusants that have been tried. The diffusion conditions, the junction depth and the surface concentration as measured in the unmasked region and the thickness of silicon nitride film used for mask appear in the following Table.
TABLE ______________________________________ Si.sub.3 N.sub.4 Diffusion Co Thick- Dif- Temp(° C)/ xj(u) (atoms/cm Sub- ness fu- Time (min) w/out w/out strate (A°) sant Deposit Drive-in mask mask ______________________________________ Si 1200 B 980/30 1200/30 2.07 7×10.sup.19 Si 1200 P 1100/10 1100/20 1.8 1×10.sup.21 Si 150 As 1200/120 1.44 1.4×10.sup.20 Si 250 Ga 1100/90 3.2 4×10.sup.19 Si 250 0 1150/20 0.5 -- Ge 250 Ga 800/120 0.92 1×10.sup.19 ______________________________________
The above data show that the silicon nitride masks not only the common diffusants such as boron, phosphorus and arsenic, but also gallium and oxygen for which silicon dioxide fails. The film thicknesses listed above are by no means the minimum thicknesses required for adequate masking. In other words, there is no indication that the films cannot be thinner than 1200° A for masking boron and phosphorus diffusion.
The minimum film thickness required to mask most common dopants in silicon and germanium is about an order of magnitude smaller than silicon dioxide. Silicon dioxide masks are usually over 2,000 angstroms thick, but the present silicon nitride films are effective at thicknesses of only about 200 angstroms. Silicon nitride can be deposited to a sufficient thickness on silicon at 800° C for about 10 to 15 min. for effective masking for most common dopants for silicon. For equivalent masking with silicon dioxide, it requires 300 min. of steam oxidation at the same temperature (800° C). Sharpness of definition is primarily a function of film thickness and since the film thickness required for silicon nitride is much thinner than for silicon dioxide for equivalent masking effect, the nitride mask will have sharper definition than oxide.
As shown in FIG. 3, the present invention has application in the production of improved susceptors, as are used in epitaxial deposition and in systems of the type illustrated in FIG. 1. A susceptor as is generally recognized in the art, is a material capable of coupling with RF power to generate heat by induction.
In use, the susceptor 30, in the form of a rectangular plate or other shape, supports one or more substrates 31. The susceptor is then inductively heated to the temperature required for the particular deposition. For example, the substrates may be a series of silicon semiconductor wafers on which an epitaxial growth of addition silicon is to be made.
According to the present invention, and referring now to FIG. 4, the main susceptor body 40 is provided with an encapsulating film 41 of silicon nitride deposited as described above. Thus, when the susceptor is heated during epitaxial deposition the out-diffusion of impurities is barred by film 41 and contamination of substrate 31 is avoided.
It will be apparent to those skilled in the art that various modifications may be made in the process and products illustratively described herein, without departing from the spirit or scope of the invention as expressed in the following claims.
Claims (7)
1. A process for depositing a pin-hole free film of silicon nitride of substantially uniform thickness comprising the steps of:
A. placing a substrate in a reaction zone,
B. introducing into said zone a mixture consisting essentially of silane, a gaseous nitrogen containing compound which upon decomposition introduces nascent nitrogen wherein the ratio of said silane to said nitrogen compound is from about 3:4 to about 1:300 by volume, and a carrier gas inert to the reactants, wherein said carrier gas is present in an amount sufficient to retard the reaction of said silane and nitrogen compound in said reaction zone, and
C. heating said substrate to a temperature of from 700°-1100° C to bring about the deposition of a pinhole-free film of silicon nitride of substantially uniform thickness of 0.1-2 microns on the surface of said substrate, wherein the deposition rate is from about 100 to about 400 Angstroms per minute.
2. The process of claim 1 wherein said substrate is a body of semiconductor material and said film of silicon nitride has a thickness of from about 200 to about 1200 Angstroms.
3. The process of claim 1 wherein said nitrogen compound is ammonia.
4. The process of claim 1 wherein the carrier gas is selected from H2, N2, A, He, Xe and Kr.
5. The process of claim 1 further comprising masking said substrate so that part of the surface of said substrate is covered by said silicon nitride film and part is exposed, and diffusing a semiconductor impurity into said substrate through said exposed part.
6. The process of claim 1 wherein said nitrogen containing compound is ammonia, the ratio of said silane to said ammonia is 1:40, by volume, and the carrier gas is hydrogen, the flow rate of said hydrogen being about 1/minute.
7. The process of claim 1 wherein said film is a diffusant mask which is substantially impermeable to volatile materials.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US05/718,720 US4089992A (en) | 1965-10-11 | 1976-08-30 | Method for depositing continuous pinhole free silicon nitride films and products produced thereby |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US49479065A | 1965-10-11 | 1965-10-11 | |
US62933867A | 1967-02-08 | 1967-02-08 | |
US05/718,720 US4089992A (en) | 1965-10-11 | 1976-08-30 | Method for depositing continuous pinhole free silicon nitride films and products produced thereby |
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EP0005491A1 (en) * | 1978-05-24 | 1979-11-28 | Hughes Aircraft Company | Process for the preparation of low temperature silicon nitride films by photochemical vapor deposition |
US4273805A (en) * | 1978-06-19 | 1981-06-16 | Rca Corporation | Passivating composite for a semiconductor device comprising a silicon nitride (Si1 3N4) layer and phosphosilicate glass (PSG) layer |
US4289797A (en) * | 1979-10-11 | 1981-09-15 | Western Electric Co., Incorporated | Method of depositing uniform films of Six Ny or Six Oy in a plasma reactor |
US4389967A (en) * | 1979-05-11 | 1983-06-28 | Fujitsu Limited | Boat for carrying semiconductor substrates |
US4419809A (en) * | 1981-12-30 | 1983-12-13 | International Business Machines Corporation | Fabrication process of sub-micrometer channel length MOSFETs |
US4419810A (en) * | 1981-12-30 | 1983-12-13 | International Business Machines Corporation | Self-aligned field effect transistor process |
US4492008A (en) * | 1983-08-04 | 1985-01-08 | International Business Machines Corporation | Methods for making high performance lateral bipolar transistors |
US4501777A (en) * | 1982-09-22 | 1985-02-26 | The United States Of America As Represented By The Secretary Of The Army | Method of sealing of ceramic wall structures |
US4546536A (en) * | 1983-08-04 | 1985-10-15 | International Business Machines Corporation | Fabrication methods for high performance lateral bipolar transistors |
US4565157A (en) * | 1983-03-29 | 1986-01-21 | Genus, Inc. | Method and apparatus for deposition of tungsten silicides |
US4573256A (en) * | 1983-08-26 | 1986-03-04 | International Business Machines Corporation | Method for making a high performance transistor integrated circuit |
USRE32351E (en) * | 1978-06-19 | 1987-02-17 | Rca Corporation | Method of manufacturing a passivating composite comprising a silicon nitride (SI1 3N4) layer and a phosphosilicate glass (PSG) layer for a semiconductor device layer |
US4668973A (en) * | 1978-06-19 | 1987-05-26 | Rca Corporation | Semiconductor device passivated with phosphosilicate glass over silicon nitride |
US4709655A (en) * | 1985-12-03 | 1987-12-01 | Varian Associates, Inc. | Chemical vapor deposition apparatus |
US4758528A (en) * | 1980-07-08 | 1988-07-19 | International Business Machines Corporation | Self-aligned metal process for integrated circuit metallization |
US4796562A (en) * | 1985-12-03 | 1989-01-10 | Varian Associates, Inc. | Rapid thermal cvd apparatus |
US4808273A (en) * | 1988-05-10 | 1989-02-28 | Avantek, Inc. | Method of forming completely metallized via holes in semiconductors |
US4842699A (en) * | 1988-05-10 | 1989-06-27 | Avantek, Inc. | Method of selective via-hole and heat sink plating using a metal mask |
EP0334791A1 (en) * | 1988-03-24 | 1989-09-27 | Union Explosivos Rio Tinto, S.A. | Process for the preparation of silicon nitride |
US4920908A (en) * | 1983-03-29 | 1990-05-01 | Genus, Inc. | Method and apparatus for deposition of tungsten silicides |
US4978639A (en) * | 1989-01-10 | 1990-12-18 | Avantek, Inc. | Method for the simultaneous formation of via-holes and wraparound plating on semiconductor chips |
US5013692A (en) * | 1988-12-08 | 1991-05-07 | Sharp Kabushiki Kaisha | Process for preparing a silicon nitride insulating film for semiconductor memory device |
US5877095A (en) * | 1994-09-30 | 1999-03-02 | Nippondenso Co., Ltd. | Method of fabricating a semiconductor device having a silicon nitride film made of silane, ammonia and nitrogen |
US6566281B1 (en) * | 1997-10-15 | 2003-05-20 | International Business Machines Corporation | Nitrogen-rich barrier layer and structures formed |
US20030186486A1 (en) * | 2002-03-28 | 2003-10-02 | Swan Johanna M. | Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme |
US20030183943A1 (en) * | 2002-03-28 | 2003-10-02 | Swan Johanna M. | Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme |
US20040255868A1 (en) * | 2002-05-17 | 2004-12-23 | Amrhein Fred | Plasma etch resistant coating and process |
US6848177B2 (en) | 2002-03-28 | 2005-02-01 | Intel Corporation | Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme |
US20050272266A1 (en) * | 2000-12-28 | 2005-12-08 | Tadahiro Ohmi | Semiconductor device and its manufacturing method |
US20060021633A1 (en) * | 2004-07-27 | 2006-02-02 | Applied Materials, Inc. | Closed loop clean gas control |
US7033650B2 (en) * | 1999-09-29 | 2006-04-25 | Electrovac, Fabrikation, Elektrotechnischer Spezialartikel, Gesellschaft Mbh | Method of producing a nanotube layer on a substrate |
US20060160314A1 (en) * | 2005-01-15 | 2006-07-20 | Applied Materials, Inc. | Substrate having silicon germanium material and stressed silicon nitride layer |
US20060264063A1 (en) * | 2005-05-23 | 2006-11-23 | Applied Materials, Inc. | Deposition of tensile and compressive stressed materials for semiconductors |
US20110223765A1 (en) * | 2010-03-15 | 2011-09-15 | Applied Materials, Inc. | Silicon nitride passivation layer for covering high aspect ratio features |
US20130162995A1 (en) * | 2011-12-27 | 2013-06-27 | Intermolecular, Inc. | Layer Thickness Measurement |
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EP0005491A1 (en) * | 1978-05-24 | 1979-11-28 | Hughes Aircraft Company | Process for the preparation of low temperature silicon nitride films by photochemical vapor deposition |
US4273805A (en) * | 1978-06-19 | 1981-06-16 | Rca Corporation | Passivating composite for a semiconductor device comprising a silicon nitride (Si1 3N4) layer and phosphosilicate glass (PSG) layer |
US4668973A (en) * | 1978-06-19 | 1987-05-26 | Rca Corporation | Semiconductor device passivated with phosphosilicate glass over silicon nitride |
USRE32351E (en) * | 1978-06-19 | 1987-02-17 | Rca Corporation | Method of manufacturing a passivating composite comprising a silicon nitride (SI1 3N4) layer and a phosphosilicate glass (PSG) layer for a semiconductor device layer |
US4389967A (en) * | 1979-05-11 | 1983-06-28 | Fujitsu Limited | Boat for carrying semiconductor substrates |
US4289797A (en) * | 1979-10-11 | 1981-09-15 | Western Electric Co., Incorporated | Method of depositing uniform films of Six Ny or Six Oy in a plasma reactor |
US4758528A (en) * | 1980-07-08 | 1988-07-19 | International Business Machines Corporation | Self-aligned metal process for integrated circuit metallization |
US4419809A (en) * | 1981-12-30 | 1983-12-13 | International Business Machines Corporation | Fabrication process of sub-micrometer channel length MOSFETs |
US4419810A (en) * | 1981-12-30 | 1983-12-13 | International Business Machines Corporation | Self-aligned field effect transistor process |
US4501777A (en) * | 1982-09-22 | 1985-02-26 | The United States Of America As Represented By The Secretary Of The Army | Method of sealing of ceramic wall structures |
US4565157A (en) * | 1983-03-29 | 1986-01-21 | Genus, Inc. | Method and apparatus for deposition of tungsten silicides |
US4920908A (en) * | 1983-03-29 | 1990-05-01 | Genus, Inc. | Method and apparatus for deposition of tungsten silicides |
US4546536A (en) * | 1983-08-04 | 1985-10-15 | International Business Machines Corporation | Fabrication methods for high performance lateral bipolar transistors |
US4492008A (en) * | 1983-08-04 | 1985-01-08 | International Business Machines Corporation | Methods for making high performance lateral bipolar transistors |
US4573256A (en) * | 1983-08-26 | 1986-03-04 | International Business Machines Corporation | Method for making a high performance transistor integrated circuit |
US4796562A (en) * | 1985-12-03 | 1989-01-10 | Varian Associates, Inc. | Rapid thermal cvd apparatus |
US4709655A (en) * | 1985-12-03 | 1987-12-01 | Varian Associates, Inc. | Chemical vapor deposition apparatus |
EP0334791A1 (en) * | 1988-03-24 | 1989-09-27 | Union Explosivos Rio Tinto, S.A. | Process for the preparation of silicon nitride |
US4808273A (en) * | 1988-05-10 | 1989-02-28 | Avantek, Inc. | Method of forming completely metallized via holes in semiconductors |
US4842699A (en) * | 1988-05-10 | 1989-06-27 | Avantek, Inc. | Method of selective via-hole and heat sink plating using a metal mask |
US5013692A (en) * | 1988-12-08 | 1991-05-07 | Sharp Kabushiki Kaisha | Process for preparing a silicon nitride insulating film for semiconductor memory device |
US4978639A (en) * | 1989-01-10 | 1990-12-18 | Avantek, Inc. | Method for the simultaneous formation of via-holes and wraparound plating on semiconductor chips |
US5877095A (en) * | 1994-09-30 | 1999-03-02 | Nippondenso Co., Ltd. | Method of fabricating a semiconductor device having a silicon nitride film made of silane, ammonia and nitrogen |
US6566281B1 (en) * | 1997-10-15 | 2003-05-20 | International Business Machines Corporation | Nitrogen-rich barrier layer and structures formed |
US7033650B2 (en) * | 1999-09-29 | 2006-04-25 | Electrovac, Fabrikation, Elektrotechnischer Spezialartikel, Gesellschaft Mbh | Method of producing a nanotube layer on a substrate |
US20050272266A1 (en) * | 2000-12-28 | 2005-12-08 | Tadahiro Ohmi | Semiconductor device and its manufacturing method |
US6848177B2 (en) | 2002-03-28 | 2005-02-01 | Intel Corporation | Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme |
US7112887B2 (en) | 2002-03-28 | 2006-09-26 | Intel Corporation | Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme |
US20050090042A1 (en) * | 2002-03-28 | 2005-04-28 | Swan Johanna M. | Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme |
US6908845B2 (en) | 2002-03-28 | 2005-06-21 | Intel Corporation | Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme |
US20030183943A1 (en) * | 2002-03-28 | 2003-10-02 | Swan Johanna M. | Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme |
US20030186486A1 (en) * | 2002-03-28 | 2003-10-02 | Swan Johanna M. | Integrated circuit die and an electronic assembly having a three-dimensional interconnection scheme |
US20040255868A1 (en) * | 2002-05-17 | 2004-12-23 | Amrhein Fred | Plasma etch resistant coating and process |
US20060021633A1 (en) * | 2004-07-27 | 2006-02-02 | Applied Materials, Inc. | Closed loop clean gas control |
US7563680B2 (en) | 2005-01-15 | 2009-07-21 | Applied Materials, Inc. | Substrate having silicon germanium material and stressed silicon nitride layer |
US7323391B2 (en) | 2005-01-15 | 2008-01-29 | Applied Materials, Inc. | Substrate having silicon germanium material and stressed silicon nitride layer |
US20080096356A1 (en) * | 2005-01-15 | 2008-04-24 | Reza Arghavani | Substrate Having Silicon Germanium Material and Stressed Silicon Nitride Layer |
US20060160314A1 (en) * | 2005-01-15 | 2006-07-20 | Applied Materials, Inc. | Substrate having silicon germanium material and stressed silicon nitride layer |
US20060264063A1 (en) * | 2005-05-23 | 2006-11-23 | Applied Materials, Inc. | Deposition of tensile and compressive stressed materials for semiconductors |
US7247582B2 (en) | 2005-05-23 | 2007-07-24 | Applied Materials, Inc. | Deposition of tensile and compressive stressed materials |
US20110223765A1 (en) * | 2010-03-15 | 2011-09-15 | Applied Materials, Inc. | Silicon nitride passivation layer for covering high aspect ratio features |
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US20130162995A1 (en) * | 2011-12-27 | 2013-06-27 | Intermolecular, Inc. | Layer Thickness Measurement |
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