|Número de publicación||US4272880 A|
|Tipo de publicación||Concesión|
|Número de solicitud||US 06/031,826|
|Fecha de publicación||16 Jun 1981|
|Fecha de presentación||20 Abr 1979|
|Fecha de prioridad||20 Abr 1979|
|Número de publicación||031826, 06031826, US 4272880 A, US 4272880A, US-A-4272880, US4272880 A, US4272880A|
|Inventores||Richard D. Pashley|
|Cesionario original||Intel Corporation|
|Exportar cita||BiBTeX, EndNote, RefMan|
|Citas de patentes (4), Citada por (155), Clasificaciones (32), Eventos legales (1)|
|Enlaces externos: USPTO, Cesión de USPTO, Espacenet|
1. Field of the Invention
The invention relates to MOS and SOS processing.
2. Prior Art
A continuing effort is occuring in the semiconductor industry to provide higher density integrated circuits. Numerous processes have been developed to provide these higher densities. Multilayer integrated circuit processing employing two and three layers of polysilicon with overlying metalization is used in some cases to increase circuit densities. V-notch MOS transistors are another example of a structure which is employed, in part, to increase circuit densities.
It has been known that some "transistor action" can be obtained in polysilicon as opposed to conventional monocrystalline silicon. Recent developments in laser annealing have shown that larger crystal grains may be formed in a polysilicon layer. In the present invention, this knowledge is used to provide transistors in a polysilicon layer.
The invented process employs unique alignment techniques, enabling multi-layer transistors to be fabricated. Alignment with buried members, such as a gate, is achieved with the present invention.
A process for fabricating two MOS transistors having a common gate region is described. A gate region is formed insulated from a substrate. This gate region has an oxide member disposed above the gate region and a silicon nitride member disposed above the oxide member. The substrate is doped in alignment with the gate region to form first source and drain regions of a first MOS transistor. An oxide layer is then formed on the substrate; the silicon nitride member prevents substantial oxide formation on the gate region during this oxide formation step. Next the oxide layer and silicon nitride member are doped and then the silicon nitride member is removed. A polysilicon layer is formed over the oxide layer and the oxide member. Dopant from the oxide layer is diffused into the polysilicon layer to form second source and drain regions of a second MOS transistor in the polysilicon layer in alignment with the common gate region. In this manner, two MOS transistors are formed in vertical alignment with one another.
FIG. 1 is a cross-sectional elevation view of a substrate with overlying layers of silicon, oxide, polysilicon, oxide, and a masking layer.
FIG. 2 illustrates the substrate of FIG. 1 after a silicon nitride layer is formed and after an additional masking step.
FIG. 3 illustrates the substrate of FIG. 2 after several etching steps.
FIG. 4 illustrates the substrate of FIG. 3 during an ion implantation step used to form first source and drain regions in the silicon layer.
FIG. 5 illustrates the substrate of FIG. 4 after a thick oxide layer is grown on the substrate.
FIG. 6 illustrates the substrate of FIG. 5 during an ion implantation step used to implant the upper surface of the thick oxide layer.
FIG. 7 illustrates the substrate of FIG. 6 after the removal of the silicon nitride masking members and after a masking and etching step used to define a window for a buried contact.
FIG. 8 illustrates the substrate of FIG. 7 after a second layer of polysilicon is formed on the substrate and during the ion implantation of this second layer of polysilicon.
FIG. 9 illustrates the substrate of FIG. 8 after the dopant from the thick oxide layer has been diffused into the second polysilicon layer and after patterns have been defined in the second layer of polysilicon. A laser annealing step is also illustrated in this FIGURE.
FIG. 10 is a plan view of the transistor fabricated with the steps of FIGS. 1 through 9.
FIG. 11 is a circuit diagram of the transistor of FIG. 10.
FIGS. 12 through 16 illustrate alternate processing.
FIG. 12 illustrates the substrate of FIG. 5 after the silicon nitride members have been removed and after a window is formed through the thick oxide layer for a buried contact.
FIG. 13 illustrates the substrate of FIG. 2 after a second layer of polysilicon has been formed on the substrate and during the doping of this layer.
FIG. 14 illustrates the substrate of FIG. 13 after patterns have been defined in the second layer of polysilicon.
FIG. 15 illustrates the substrate of FIG. 14 after a photoresist layer has been formed over the substrate and during the exposure of this photoresist layer to radiation directed through the substrate.
FIG. 16 illustrates the substrate of FIG. 15 after development of the photoresist layer and during the ion implantation of the second layer of polysilicon to form second source and drain regions in this layer.
A metal-oxide-semiconductor (MOS) process suitable for use in silicon-on-sapphire (SOS) processing is disclosed. In the following description, numerous well-known processing steps are not set forth in detail in order not to obscure the present invention in unnecessary detail. In other instances, specific details such as specific conductivity types and dopants, layer thicknesses, etc. are set forth to provide a thorough understanding of the present invention. However, it will be obvious to one skilled in the art that these specific details need not be employed to practice the present invention.
FIGS. 1 through 9 describe various processing steps which result in the fabrication of an inverter which includes an n-channel and a p-channel field-effect transistor, commonly referred to as complementary MOS transistors (CMOS). The specific circuit fabricated with the steps shown in FIGS. 1 through 9 is illustrated in FIG. 11. In general, the n-channel transistor 55 is fabricated in a monocrystalline silicon layer or substrate. The transistors 54 and 55 have a common gate 24a which is fabricated from a first level of polysilicon. The p-channel transistor 55 is fabricated in a second level of polysilicon. A buried contact region is employed to interconnect the source region of transistor 54 and the drain region of transistor 55. An output line 52 for the inverter is shown in FIGS. 9 and 11. Simultaneously with the fabrication of the inverter of FIG. 11, a "via" contact (poly-to-poly contact) is formed to couple the gate 24a to a polysilicon line defined from the second level of polysilicon. This via contact is shown to demonstrate the flexibility of the described process.
FIGS. 12 through 16 show alternate processing where alignment is obtained by projecting light (or other radiation) through a transparent substrate such as a sapphire substrate to expose a radiation sensitive layer such as a photoresist layer.
While in the following description the processing for the CMOS inverter of FIG. 11 is described, it will be obvious to one skilled in the art that other circuit devices may be fabricated employing the process.
For the processing steps described in FIGS. 1 through 9, the transistors may be fabricated on a monocrystalline silicon substrate or on a sapphire substrate which includes an epitaxial silicon layer. In FIG. 1, a sapphire (AL2 O3) crystalline substrate 20 which may be, for example, 20 mils thick, is illustrated. An epitaxial silicon layer 22 is formed on the upper surface of the substrate 20 in a well-known manner. In the presently preferred embodiment, this silicon layer is approximately 1 micron thick, since in subsequent processing an oxide layer is grown from this silicon. In the presently preferred embodiment where an n-channel transistor is fabricated in the epitaxial layer 22, this layer is doped with a p-type dopant; the layer is ion-implanted with boron to obtain a dopant concentration of 1-5×1012 /cm2.
Well-known processing steps are next employed to define areas on the substrate at which active devices are fabricated. These processing steps include the formation of field oxides 26 and the channel stops 27 which are heavily doped with a p-type dopant. These channel stops reduce leakage currents as is well-known in the art. These "front-end" processing steps are described in U.S. Pat. No. 4,033,026. A first oxide layer (SiO2) is also grown from the silicon layer 22. This oxide layer 23, in the presently preferred embodiment, is between 400 A to 1,000 A thick and is used to form a gate oxide to separate the gate from the silicon layer 22. A polycrystalline silicon (polysilicon) layer is then formed over the first oxide layer 23. The polysilicon layer 24, in the presently preferred embodiment, is approximately 5,000 A thick and is heavily doped with an n-type dopant.
A second oxide layer 25 is formed over the polysilicon layer 24 employing chemical vapor deposition techniques or thermal oxidation in the presently preferred embodiment. This oxide layer, which is between 400 A to 1,000 A thick is used to form the gate oxide for the p-channel transistor. As shown in FIG. 1, a photoresist layer 28 is next formed over the oxide layer 25, then masked and etched to define a window 29. This window is formed at the site of the via (poly-to-poly) contact. The underlying oxide layer 25 is etched at the location of the window 29.
Following the removal of the photoresist layer 29 of FIG. 1, a silicon nitride (Si3 N4) layer 30 is deposited over the oxide layer 25. This layer may be between 400 to 1,000 A thick. Note that the silicon nitride layer 30 contacts the polysilicon layer 24 at the site of the via contact.
By employing ordinary masking techniques, a masking member 33 is defined on the upper surface of the silicon nitride layer 30. The member 33 is used to define the gate of the transistors of FIG. 11; in the presently preferred embodiment this member is 2-3 microns wide. Simultaneous with the fabrication of the masking member 33, a masking member 34 is defined over the silicon nitride layer 30 at the site of the via contact.
Now, ordinary etching steps are employed to etch the silicon nitride layer 30, oxide layer 25 and polysilicon layer 24. After the masks 33 and 34 are removed, the resultant structure is shown in FIG. 3. A silicon nitride member 30a, formed from layer 30, is disposed above the polysilicon gate 24a which gate was formed from the polysilicon layer 24. A gate oxide member 25a formed from layer 25 is disposed between the silicon nitride member 30a and gate 24a. A silicon nitride member 30b is in direct contact with a polysilicon member 24b for the via contact. (Briefly referring to FIG. 10, the masking step defining the masking members 33 and 34 actually defines a generally U-shaped single masking member which results in the polysilicon structure shown in FIG. 10 by the "x'ed" line. One end of this polysilicon member includes the gate 24a, the other end, member 24b, interconnected by the polysilicon line 57.)
Next, as shown in FIG. 4 by the lines 36, the substrate is subjected to ion implantation to form the source and drain regions for the n-channel device. Specifically, regions 22a and 22c separated by the channel region 22b are formed. In the presently preferred embodiment, this ion implantation occurs through the oxide layer 23 in alignment with gate 24a. An arsenic dopant is presently preferred, doping the source and drain regions to a level of approximately 4×1015 /cm2. (Referring briefly to FIG. 10, in the plan view this ion implantation step forms the T-shaped doped region shown by the solid line ad labeled "EPI doping", with no doping beneath gate 24a.)
Now a thick oxide layer 38 is grown from the epitaxial layer 22. This layer may be 4,000±2,000 A thick. As best shown in FIG. 5, the silicon nitride members 30a and 30b prevent the growth of this oxide on the polysilicon in contact with them. Thus, the thickness of the oxide between the member 30a and the gate 24a, shown as the second gate oxide 25a, remains substantially constant; similarly, no oxide develops on the upper surface of the polysilicon member 24b. It should be noted that since the oxide beneath the gate 24a is covered by the gate, this oxide does not significantly thicken.
Next, as shown in FIG. 6 by lines 40, the substrate is again subjected to ion implantation with a p-type dopant. For this particular processing step, a readily diffusable dopant is employed. In the presently preferred embodiment, gallium is implanted at an energy level of approximately 20 Kev to provide a dopant concentration of approximately 1×1015 /cm2. The dopant, at this point in the processing, does not diffuse deeply into the oxide layer 38 and is shown at the surface of oxide layer 38 and along the upper surfaces of the silicon nitride member 30a and 30b by the "x's" 41.
As shown in FIG. 7, the silicon nitride members 30a and 30b are removed employing readily known etchants. An ordinary masking and etching step is employed to define the window 45 which extends through the oxide layer 28 exposing the underlying region 22c. This window is formed for a buried contact.
A second layer of polysilicon, shown as layer 48 in FIG. 8, is now formed over the oxide layer 38. This layer is approximately 5,000 A thick, in the presently preferred embodiment. Note this polysilicon layer forms a contact 48 which contacts the region 22c at the surface 49. As shown in FIG. 8 by lines 50, this layer of polysilicon is then subjected to ion implantation to dope the polysilicon with an n-type dopant. In the presently preferred embodiment, arsenic or phosphorus is employed to dope the layer 48 to a dopant concentration level of approximately 1×1015 /cm2.
Now an ordinary masking and etching step is employed to define members from the second layer of polysilicon. Referring briefly to FIG. 10, this masking and etching step defines the members shown by the broken line, specifically the T-shaped structure and a line 48d. Note that the line 48d is in direct contact with the first layer polysilicon member 24b, thus providing a via contact.
Next the substrate is subjected to a carefully controlled driver step. In the presently preferred embodiment, the substrate is heated to a temperature of approximately 1,000° C. to cause the gallium residing in the upper surface of the oxide layer 38 to diffuse. The time and temperature is controlled to cause the gallium to diffuse into the overlying second level polysilicon layer 48. However, this driver step does not continue sufficiently long to cause the gallium dopant to affect the doping levels in the epitaxial layer 22. This diffusion of the gallium forms the p+ region 48a and the p+ region 48c. Note that since the silicon nitride member 30a was removed (see FIGS. 6 and 7), there is no gallium dopant above the gate 24a to change the conductivity type of the n-type region 48b.
Thus, by doping the upper surface of the oxide layer 38 and by subsequently removing the silicon nitride member, the regions 48a and 48c are formed in alignment with the underlying buried gate 24a.
To enhance the characteristics of the transistor or transistors fabricated in the second layer of polysilicon, the polysilicon may be laser annealed. This annealing produces larger crystalline grains, thereby providing more of the characteristics associated with transistors fabricated in a monocrystalline silicon layer. This laser annealing is shown in FIG. 9 by the lines 63. For a discussion of this technique, see "CW Laser Anneal of Polycrystalline Silicon: Crystalline Structure, Electrical Properties" by Gerzberg, Gibbons, Magee, Penz and Hong, Applied Physics Letters, Volume 33, No. 8, Oct. 15, 1978.
In the presently preferred embodiment, as shown in the FIGURES, a gate oxide is formed from the second oxide layer 25 which separates the gate 24a from the silicon nitride member 30a, for example, see FIG. 4. For some processes it may be desirable to eliminate the oxide layer 25, thus forming the silicon nitride member 30a directly on the polysilicon gate 24a. For these processes, the step shown in FIG. 6 of implanting the gallium proceeds in the same manner as described above. However, instead of removing the entire silicon nitride member 30a as shown in FIG. 7, only a portion of the member 30a is removed by etching. For example, if the silicon nitride member 30a is 1,000 A thick, 500 A of this member may be etched away, leaving silicon nitride insulation between the gate 24a and the second layer polysilicon. Note that in removing at least a portion of the silicon nitride member 30a, the gallium dopant is removed, thus providing the alignment of the source and drain regions 48c and 48a of FIG. 9 with the underlying buried gate 24a.
It is apparent from FIGS. 9 and 10 that the inverter requires much less substrate area than prior art inverters. Thus, the described process is useful for providing high density integrated circuits. Moreover, because both pairs of source and drain regions are in alignment with the common gate, good performance is obtained.
In the alternate processing shown in FIGS. 12 through 16, like steps and like structure to that shown in FIGS. 1 through 9 are shown with the same numerals, however with the addition of a "0" to the numerals. The processing for this alternate embodiment is the same as described above in conjunction with FIGS. 1 through 5. The gallium implant shown in FIG. 6 is not employed; rather, the silicon nitride members 30a and 30b of FIG. 5 are removed.
Referring now to FIG. 12, a window 450 is formed in the oxide layer 380 for the buried contact.
Next, as shown in FIG. 13, a second layer of polysilicon 480 is formed over the substrate. This layer may have the same thickness as layer 48. Then, ion implantation of an n-type dopant such as arsenic is employed to lightly dope the layer 480. A concentration level of 1-5×1012 /cm2 is employed in the presently preferred embodiment.
Now, as shown in FIG. 14, with an ordinary masking and etching step, the desired members in the second layer of polysilicon are defined. These members correspond to the second layer polysilicon patterns shown, for example, in FIG. 10.
In FIG. 15, the substrate is shown after a photoresist layer 58 is formed over the substrate and over the second layer of polysilicon. To define these regions, the photoresist layer 58 is exposed to light or other radiation by projecting the light 60 through the underside of the substrate 200. For this reason, the substrate 200 must be relatively transparent or translucent, as is the case with a sapphire substrate. The intensity of this light is selected such that the photoresist is exposed except above the gate 240a. That is, the additional silicon present in the gate 240a prevents the light from reaching the photoresist directly above the gate 240a. (Note that while it appears in FIG. 15 that there is additional polysilicon from the layer 480 which extends into the well and contacts the area 490, this additional silicon is not actually present in practice. In practice, the layer 480 has a relative uniform thickness even at the regions of the buried contacts. While this uniform thickness would appear in a drawing done to scale, a scaled drawing has not been used since it is not practical for explaining the invention.)
As shown in FIG. 16, after the photoresist layer is developed, a masking member 58a is formed in alignment with the underlying buried gate 240a. Now the substrate is subjected to ion implantation 61 to dope regions 480a and 480c and define regions 480b. These regions are formed in alignment with the masking member 58a, and hence, are in alignment with the underlying gate 240a. A boron dopant is employed to form the heavily doped p-type regions 480a and 480c.
The entire substrate may now be subjected to laser annealing as shown by lines 630, to provide larger crystalline grains in the polysilicon layer. The resultant structure is identical to the structure of FIGS. 9 and 10.
It will be apparent to one skilled in the art that some of the above-described steps may be performed in different orders with the same result. For example, the laser annealing may be performed prior to the masking and etching step used to define patterns in the second layer of polysilicon. Also in some cases, rather than employing ion implantation to dope regions, other well-known doping techniques may be employed. It will also be obvious to one skilled in the art that both the transistors 54 and 55 of FIG. 11 may be of the same conductivity type, that is, both n-channel or p-channel devices. Numerous other integrated circuit structures other than the described inverter may be fabricated with the disclosed process by employing the described buried contact and via contact and with overlying metal layers.
Thus, an MOS process has been disclosed which is particularly useful for SOS structures. The process permits the alignment between a buried member such as a gate and overlying members or regions such as source and drain regions.
|Patente citada||Fecha de presentación||Fecha de publicación||Solicitante||Título|
|US3585088 *||18 Oct 1968||15 Jun 1971||Ibm||Methods of producing single crystals on supporting substrates|
|US3639813 *||14 Abr 1970||1 Feb 1972||Nippon Electric Co||Complementary enhancement and depletion mosfets with common gate and channel region, the depletion mosfet also being a jfet|
|US4033026 *||16 Dic 1975||5 Jul 1977||Intel Corporation||High density/high speed MOS process and device|
|US4174217 *||2 Ago 1974||13 Nov 1979||Rca Corporation||Method for making semiconductor structure|
|Patente citante||Fecha de presentación||Fecha de publicación||Solicitante||Título|
|US4327477 *||17 Jul 1980||4 May 1982||Hughes Aircraft Co.||Electron beam annealing of metal step coverage|
|US4332077 *||16 Jul 1981||1 Jun 1982||Rca Corporation||Method of making electrically programmable control gate injected floating gate solid state memory transistor|
|US4339285 *||28 Jul 1980||13 Jul 1982||Rca Corporation||Method for fabricating adjacent conducting and insulating regions in a film by laser irradiation|
|US4341009 *||5 Dic 1980||27 Jul 1982||International Business Machines Corporation||Method for making an electrical contact to a silicon substrate through a relatively thin layer of silicon dioxide on the surface of the substrate|
|US4341569 *||8 Jul 1980||27 Jul 1982||Hughes Aircraft Company||Semiconductor on insulator laser process|
|US4375993 *||8 Abr 1981||8 Mar 1983||Fujitsu Limited||Method of producing a semiconductor device by simultaneous multiple laser annealing|
|US4377902 *||3 Sep 1980||29 Mar 1983||Vlsi Technology Research Association||Method of manufacturing semiconductor device using laser beam crystallized poly/amorphous layer|
|US4412375 *||10 Jun 1982||1 Nov 1983||Intel Corporation||Method for fabricating CMOS devices with guardband|
|US4455567 *||27 Nov 1981||19 Jun 1984||Hughes Aircraft Company||Polycrystalline semiconductor resistor having a noise reducing field plate|
|US4467518 *||7 Feb 1983||28 Ago 1984||Ibm Corporation||Process for fabrication of stacked, complementary MOS field effect transistor circuits|
|US4475955 *||6 Dic 1982||9 Oct 1984||Harris Corporation||Method for forming integrated circuits bearing polysilicon of reduced resistance|
|US4476475 *||19 Nov 1982||9 Oct 1984||Northern Telecom Limited||Stacked MOS transistor|
|US4494300 *||30 Jun 1981||22 Ene 1985||International Business Machines, Inc.||Process for forming transistors using silicon ribbons as substrates|
|US4504743 *||30 Nov 1981||12 Mar 1985||Fujitsu Limited||Semiconductor resistor element|
|US4523370 *||5 Dic 1983||18 Jun 1985||Ncr Corporation||Process for fabricating a bipolar transistor with a thin base and an abrupt base-collector junction|
|US4524377 *||14 Feb 1984||18 Jun 1985||Nec Corporation||Integrated circuit|
|US4554572 *||17 Jun 1983||19 Nov 1985||Texas Instruments Incorporated||Self-aligned stacked CMOS|
|US4555721 *||4 Nov 1983||26 Nov 1985||International Business Machines Corporation||Structure of stacked, complementary MOS field effect transistor circuits|
|US4570175 *||16 Jun 1983||11 Feb 1986||Hitachi, Ltd.||Three-dimensional semiconductor device with thin film monocrystalline member contacting substrate at a plurality of locations|
|US4571609 *||3 Abr 1984||18 Feb 1986||Tokyo Shibaura Denki Kabushiki Kaisha||Stacked MOS device with means to prevent substrate floating|
|US4581620 *||29 Jun 1981||8 Abr 1986||Shunpei Yamazaki||Semiconductor device of non-single crystal structure|
|US4603341 *||8 Sep 1983||29 Jul 1986||International Business Machines Corporation||Stacked double dense read only memory|
|US4603468 *||28 Sep 1984||5 Ago 1986||Texas Instruments Incorporated||Method for source/drain self-alignment in stacked CMOS|
|US4713678 *||13 Nov 1986||15 Dic 1987||Texas Instruments Incorporated||dRAM cell and method|
|US4748485 *||9 Jun 1987||31 May 1988||Hughes Aircraft Company||Opposed dual-gate hybrid structure for three-dimensional integrated circuits|
|US4772568 *||29 May 1987||20 Sep 1988||General Electric Company||Method of making integrated circuit with pair of MOS field effect transistors sharing a common source/drain region|
|US4792837 *||26 Feb 1986||20 Dic 1988||Ge Solid State Patents, Inc.||Orthogonal bipolar transistor|
|US4803528 *||20 May 1982||7 Feb 1989||General Electric Company||Insulating film having electrically conducting portions|
|US4814841 *||30 Ene 1987||21 Mar 1989||Kabushiki Kaisha Toshiba||Semiconductor device|
|US4823180 *||28 Oct 1982||18 Abr 1989||Siemens Aktiengesellschaft||Photo-transistor in MOS thin-film technology and method for production and operation thereof|
|US4868140 *||27 Jun 1988||19 Sep 1989||Canon Kabushiki Kaisha||Semiconductor device and method of manufacturing the same|
|US4876582 *||2 May 1983||24 Oct 1989||Ncr Corporation||Crystallized silicon-on-insulator nonvolatile memory device|
|US4959700 *||3 Feb 1988||25 Sep 1990||Semiconductor Energy Laboratory Co., Ltd.||Insulated gate field effect transistor and its manufacturing method|
|US4980732 *||17 Oct 1988||25 Dic 1990||Nec Corporation||Semiconductor device having an improved thin film transistor|
|US4999691 *||22 Dic 1989||12 Mar 1991||General Electric Company||Integrated circuit with stacked MOS field effect transistors|
|US5091334 *||5 Mar 1990||25 Feb 1992||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device|
|US5189500 *||20 Sep 1990||23 Feb 1993||Mitsubishi Denki Kabushiki Kaisha||Multi-layer type semiconductor device with semiconductor element layers stacked in opposite directions and manufacturing method thereof|
|US5262350 *||1 Jul 1992||16 Nov 1993||Semiconductor Energy Laboratory Co., Ltd.||Forming a non single crystal semiconductor layer by using an electric current|
|US5308778 *||11 Ene 1993||3 May 1994||Motorola, Inc.||Method of formation of transistor and logic gates|
|US5313077 *||30 Abr 1993||17 May 1994||Semiconductor Energy Laboratory Co., Ltd.||Insulated gate field effect transistor and its manufacturing method|
|US5315132 *||8 Dic 1992||24 May 1994||Semiconductor Energy Laboratory Co., Ltd.||Insulated gate field effect transistor|
|US5324678 *||30 Nov 1992||28 Jun 1994||Mitsubishi Denki Kabushiki Kaisha||Method of forming a multi-layer type semiconductor device with semiconductor element layers stacked in opposite directions|
|US5358887 *||26 Nov 1993||25 Oct 1994||United Microelectronics Corporation||Ulsi mask ROM structure and method of manufacture|
|US5396083 *||23 Jun 1993||7 Mar 1995||Goldstar Co., Ltd.||Thin film transistor and method of making the same|
|US5440150 *||13 Sep 1994||8 Ago 1995||Iowa State University Research Foundation, Inc.||Non-crystalline silicon active device for large-scale digital and analog networks|
|US5460995 *||15 Jun 1994||24 Oct 1995||Nec Corporation||Fully CMOS-type SRAM device and method for fabricating the same|
|US5543636 *||7 Jun 1995||6 Ago 1996||Semiconductor Energy Laboratory Co., Ltd.||Insulated gate field effect transistor|
|US5563440 *||22 Ago 1994||8 Oct 1996||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device and method for forming the same|
|US5574295 *||9 Ago 1995||12 Nov 1996||Kulite Semiconductor Products||Dielectrically isolated SiC mosfet|
|US5583368 *||11 Ago 1994||10 Dic 1996||International Business Machines Corporation||Stacked devices|
|US5604137 *||2 Jun 1995||18 Feb 1997||Semiconductor Energy Laboratory Co., Ltd.||Method for forming a multilayer integrated circuit|
|US5607877 *||6 Oct 1994||4 Mar 1997||Fujitsu Limited||Projection-electrode fabrication method|
|US5612563 *||25 Ene 1994||18 Mar 1997||Motorola Inc.||Vertically stacked vertical transistors used to form vertical logic gate structures|
|US5684320 *||3 Jul 1995||4 Nov 1997||Fujitsu Limited||Semiconductor device having transistor pair|
|US5859443 *||6 Jun 1995||12 Ene 1999||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device|
|US5898204 *||16 Ago 1995||27 Abr 1999||Canon Kabushiki Kaisha||Thin-film transistor, and its semiconductor device, active matrix board, and LCD device|
|US6185122||22 Dic 1999||6 Feb 2001||Matrix Semiconductor, Inc.||Vertically stacked field programmable nonvolatile memory and method of fabrication|
|US6221701||16 Oct 1997||24 Abr 2001||Semiconductor Energy Laboratory Co., Ltd.||Insulated gate field effect transistor and its manufacturing method|
|US6331468 *||11 May 1998||18 Dic 2001||Lsi Logic Corporation||Formation of integrated circuit structure using one or more silicon layers for implantation and out-diffusion in formation of defect-free source/drain regions and also for subsequent formation of silicon nitride spacers|
|US6351406||15 Nov 2000||26 Feb 2002||Matrix Semiconductor, Inc.||Vertically stacked field programmable nonvolatile memory and method of fabrication|
|US6355941||11 Ene 1995||12 Mar 2002||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device|
|US6385074||22 Dic 2000||7 May 2002||Matrix Semiconductor, Inc.||Integrated circuit structure including three-dimensional memory array|
|US6420215||21 Mar 2001||16 Jul 2002||Matrix Semiconductor, Inc.||Three-dimensional memory array and method of fabrication|
|US6424581||14 Ago 2000||23 Jul 2002||Matrix Semiconductor, Inc.||Write-once memory array controller, system, and method|
|US6429484 *||7 Ago 2000||6 Ago 2002||Advanced Micro Devices, Inc.||Multiple active layer structure and a method of making such a structure|
|US6483736||24 Ago 2001||19 Nov 2002||Matrix Semiconductor, Inc.||Vertically stacked field programmable nonvolatile memory and method of fabrication|
|US6515888||13 Ago 2001||4 Feb 2003||Matrix Semiconductor, Inc.||Low cost three-dimensional memory array|
|US6525953||13 Ago 2001||25 Feb 2003||Matrix Semiconductor, Inc.||Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication|
|US6545891||14 Ago 2000||8 Abr 2003||Matrix Semiconductor, Inc.||Modular memory device|
|US6545898||29 Jun 2001||8 Abr 2003||Silicon Valley Bank||Method and apparatus for writing memory arrays using external source of high programming voltage|
|US6580124||14 Ago 2000||17 Jun 2003||Matrix Semiconductor Inc.||Multigate semiconductor device with vertical channel current and method of fabrication|
|US6593624||25 Sep 2001||15 Jul 2003||Matrix Semiconductor, Inc.||Thin film transistors with vertically offset drain regions|
|US6600196 *||16 Ene 2001||29 Jul 2003||International Business Machines Corporation||Thin film transistor, and manufacturing method thereof|
|US6624485||5 Nov 2001||23 Sep 2003||Matrix Semiconductor, Inc.||Three-dimensional, mask-programmed read only memory|
|US6631085||29 Jun 2001||7 Oct 2003||Matrix Semiconductor, Inc.||Three-dimensional memory array incorporating serial chain diode stack|
|US6633509||5 Dic 2002||14 Oct 2003||Matrix Semiconductor, Inc.||Partial selection of passive element memory cell sub-arrays for write operations|
|US6635520||28 Sep 1999||21 Oct 2003||Semiconductor Energy Laboratory Co., Ltd.||Operation method of semiconductor devices|
|US6653712||22 May 2002||25 Nov 2003||Matrix Semiconductor, Inc.||Three-dimensional memory array and method of fabrication|
|US6658438||14 Ago 2000||2 Dic 2003||Matrix Semiconductor, Inc.||Method for deleting stored digital data from write-once memory device|
|US6660574||22 Dic 1993||9 Dic 2003||Semiconductor Energy Laboratory Co., Ltd.||Method of forming a semiconductor device including recombination center neutralizer|
|US6661730||22 Dic 2000||9 Dic 2003||Matrix Semiconductor, Inc.||Partial selection of passive element memory cell sub-arrays for write operation|
|US6677204||26 Sep 2002||13 Ene 2004||Matrix Semiconductor, Inc.||Multigate semiconductor device with vertical channel current and method of fabrication|
|US6680486||6 Oct 1997||20 Ene 2004||Semiconductor Energy Laboratory Co., Ltd.||Insulated gate field effect transistor and its manufacturing method|
|US6689644||22 Abr 2002||10 Feb 2004||Matrix Semiconductor, Inc.||Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication|
|US6709935||26 Mar 2001||23 Mar 2004||Advanced Micro Devices, Inc.||Method of locally forming a silicon/geranium channel layer|
|US6711043||27 Jun 2002||23 Mar 2004||Matrix Semiconductor, Inc.||Three-dimensional memory cache system|
|US6734499||28 Sep 1999||11 May 2004||Semiconductor Energy Laboratory Co., Ltd.||Operation method of semiconductor devices|
|US6737675||27 Jun 2002||18 May 2004||Matrix Semiconductor, Inc.||High density 3D rail stack arrays|
|US6743680||22 Jun 2000||1 Jun 2004||Advanced Micro Devices, Inc.||Process for manufacturing transistors having silicon/germanium channel regions|
|US6754102||24 Sep 2002||22 Jun 2004||Matrix Semiconductor, Inc.||Method for programming a three-dimensional memory array incorporating serial chain diode stack|
|US6765813||27 Jun 2002||20 Jul 2004||Matrix Semiconductor, Inc.||Integrated systems using vertically-stacked three-dimensional memory cells|
|US6767816||24 Sep 2002||27 Jul 2004||Matrix Semiconductor, Inc.||Method for making a three-dimensional memory array incorporating serial chain diode stack|
|US6780711||23 Sep 2002||24 Ago 2004||Matrix Semiconductor, Inc||Vertically stacked field programmable nonvolatile memory and method of fabrication|
|US6784517||24 Sep 2002||31 Ago 2004||Matrix Semiconductor, Inc.||Three-dimensional memory array incorporating serial chain diode stack|
|US6841813||26 Oct 2001||11 Ene 2005||Matrix Semiconductor, Inc.||TFT mask ROM and method for making same|
|US6853049||13 Mar 2002||8 Feb 2005||Matrix Semiconductor, Inc.||Silicide-silicon oxide-semiconductor antifuse device and method of making|
|US6867992||13 Ene 2003||15 Mar 2005||Matrix Semiconductor, Inc.||Modular memory device|
|US6881994||13 Ago 2001||19 Abr 2005||Matrix Semiconductor, Inc.||Monolithic three dimensional array of charge storage devices containing a planarized surface|
|US6888750||13 Ago 2001||3 May 2005||Matrix Semiconductor, Inc.||Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication|
|US6897514||5 Feb 2002||24 May 2005||Matrix Semiconductor, Inc.||Two mask floating gate EEPROM and method of making|
|US6900463||8 Sep 1992||31 May 2005||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device|
|US6940109||18 Feb 2004||6 Sep 2005||Matrix Semiconductor, Inc.||High density 3d rail stack arrays and method of making|
|US6992349||20 May 2004||31 Ene 2006||Matrix Semiconductor, Inc.||Rail stack array of charge storage devices and method of making same|
|US7129538||10 May 2004||31 Oct 2006||Sandisk 3D Llc||Dense arrays and charge storage devices|
|US7157314||24 Ago 2001||2 Ene 2007||Sandisk Corporation||Vertically stacked field programmable nonvolatile memory and method of fabrication|
|US7160761||19 Sep 2002||9 Ene 2007||Sandisk 3D Llc||Vertically stacked field programmable nonvolatile memory and method of fabrication|
|US7174351||29 Sep 2003||6 Feb 2007||Sandisk 3D Llc||Method for deleting stored digital data from write-once memory device|
|US7177183||30 Sep 2003||13 Feb 2007||Sandisk 3D Llc||Multiple twin cell non-volatile memory array and logic block structure and method therefor|
|US7190602||9 Feb 2004||13 Mar 2007||Sandisk 3D Llc||Integrated circuit incorporating three-dimensional memory array with dual opposing decoder arrangement|
|US7217644 *||21 Jul 2004||15 May 2007||Intel Corporation||Method of manufacturing MOS devices with reduced fringing capacitance|
|US7250646||18 Oct 2004||31 Jul 2007||Sandisk 3D, Llc.||TFT mask ROM and method for making same|
|US7265000||14 Feb 2006||4 Sep 2007||Sandisk 3D Llc||Vertically stacked field programmable nonvolatile memory and method of fabrication|
|US7283403||12 Nov 2004||16 Oct 2007||Sandisk 3D Llc||Memory device and method for simultaneously programming and/or reading memory cells on different levels|
|US7319053||14 Feb 2006||15 Ene 2008||Sandisk 3D Llc||Vertically stacked field programmable nonvolatile memory and method of fabrication|
|US7435634 *||5 Abr 2006||14 Oct 2008||Samsung Electronics Co., Ltd.||Methods of forming semiconductor devices having stacked transistors|
|US7476601 *||12 Ago 2005||13 Ene 2009||A U Optronics Corp.||Semiconductor structure having multilayer of polysilicon and display panel applied with the same|
|US7525137||12 Jul 2006||28 Abr 2009||Sandisk Corporation||TFT mask ROM and method for making same|
|US7526739||13 Jul 2006||28 Abr 2009||R3 Logic, Inc.||Methods and systems for computer aided design of 3D integrated circuits|
|US7615436||20 May 2004||10 Nov 2009||Sandisk 3D Llc||Two mask floating gate EEPROM and method of making|
|US7655509||13 Sep 2007||2 Feb 2010||Sandisk 3D Llc||Silicide-silicon oxide-semiconductor antifuse device and method of making|
|US7741644 *||8 Feb 2007||22 Jun 2010||Samsung Electronics Co., Ltd.||Semiconductor device having stacked transistors|
|US7816189||26 Oct 2007||19 Oct 2010||Sandisk 3D Llc||Vertically stacked field programmable nonvolatile memory and method of fabrication|
|US7825455||23 Ene 2009||2 Nov 2010||Sandisk 3D Llc||Three terminal nonvolatile memory device with vertical gated diode|
|US7915095||13 Ene 2010||29 Mar 2011||Sandisk 3D Llc||Silicide-silicon oxide-semiconductor antifuse device and method of making|
|US7915163 *||22 Jun 2009||29 Mar 2011||Sandisk 3D Llc||Method for forming doped polysilicon via connecting polysilicon layers|
|US7915164||29 Mar 2011||Sandisk 3D Llc||Method for forming doped polysilicon via connecting polysilicon layers|
|US7928008 *||18 Ene 2008||19 Abr 2011||Terasemicon Corporation||Method for fabricating semiconductor device|
|US7936024||4 Sep 2008||3 May 2011||Samsung Electronics Co., Ltd.||Semiconductor devices having stacked structures|
|US7978492||16 Mar 2010||12 Jul 2011||Sandisk 3D Llc||Integrated circuit incorporating decoders disposed beneath memory arrays|
|US7994511||9 Dic 2008||9 Ago 2011||Au Optronics Corp.||Semiconductor structure having multilayer of polysilicon and display panel applied with the same|
|US8032857||18 Sep 2008||4 Oct 2011||R3 Logic, Inc.||Methods and systems for computer aided design of 3D integrated circuits|
|US8208282||7 Oct 2010||26 Jun 2012||Sandisk 3D Llc||Vertically stacked field programmable nonvolatile memory and method of fabrication|
|US8209649||7 Ago 2009||26 Jun 2012||R3 Logic, Inc||Methods and systems for computer aided design of 3D integrated circuits|
|US8266560||26 Ago 2011||11 Sep 2012||R3 Logic, Inc.||Methods and systems for computer aided design of 3D integrated circuits|
|US8503215||19 Jun 2012||6 Ago 2013||Sandisk 3D Llc||Vertically stacked field programmable nonvolatile memory and method of fabrication|
|US8575719||30 Jun 2003||5 Nov 2013||Sandisk 3D Llc||Silicon nitride antifuse for use in diode-antifuse memory arrays|
|US8650516||14 Ago 2012||11 Feb 2014||Lisa G. McIlrath||Methods and systems for computer aided design of 3D integrated circuits|
|US8823076||27 Mar 2014||2 Sep 2014||Sandisk 3D Llc||Dense arrays and charge storage devices|
|US8853765||27 Mar 2014||7 Oct 2014||Sandisk 3D Llc||Dense arrays and charge storage devices|
|US8897056||29 Jul 2013||25 Nov 2014||Sandisk 3D Llc||Pillar-shaped nonvolatile memory and method of fabrication|
|US8981457||10 May 2012||17 Mar 2015||Sandisk 3D Llc||Dense arrays and charge storage devices|
|US20010055838 *||13 Ago 2001||27 Dic 2001||Matrix Semiconductor Inc.||Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication|
|US20020142546 *||5 Feb 2002||3 Oct 2002||Matrix Semiconductor, Inc.||Two mask floating gate EEPROM and method of making|
|US20040098416 *||29 Sep 2003||20 May 2004||Moore Christopher S.||Method for deleting stored digital data from write-once memory device|
|US20040207001 *||20 May 2004||21 Oct 2004||Matrix Semiconductor, Inc.||Two mask floating gate EEPROM and method of making|
|US20040214379 *||20 May 2004||28 Oct 2004||Matrix Semiconductor, Inc.||Rail stack array of charge storage devices and method of making same|
|US20040256673 *||21 Jul 2004||23 Dic 2004||Brian Doyle||MOS devices with reduced fringing capacitance|
|US20050063220 *||12 Nov 2004||24 Mar 2005||Johnson Mark G.||Memory device and method for simultaneously programming and/or reading memory cells on different levels|
|US20050070060 *||18 Oct 2004||31 Mar 2005||Matrix Semiconductor, Inc.||TFT mask ROM and method for making same|
|US20050112804 *||12 Nov 2004||26 May 2005||Matrix Semiconductor, Inc.||Silicide-silicon oxide-semiconductor antifuse device and method of making|
|US20140061810 *||22 Ago 2013||6 Mar 2014||Renesas Electronics Corporation||Semiconductor device and manufacturing method thereof|
|USRE34658 *||27 Ene 1992||12 Jul 1994||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor device of non-single crystal-structure|
|EP0073487A2 *||26 Ago 1982||9 Mar 1983||Kabushiki Kaisha Toshiba||Method for manufacturing three-dimensional semiconductor device|
|WO1987005440A1 *||12 Feb 1987||11 Sep 1987||Ncr Co||Fabrication process for stacked mos devices|
|WO1991011027A1 *||16 Ene 1991||25 Jul 1991||Univ Iowa State Res Found Inc||Non-crystalline silicon active device for large-scale digital and analog networks|
|Clasificación de EE.UU.||438/153, 257/369, 257/E21.704, 257/E21.614, 257/351, 257/E21.347, 438/308, 257/354, 148/DIG.91, 438/279, 257/E27.111, 257/E27.026, 257/E21.027|
|Clasificación internacional||H01L27/12, H01L21/86, H01L21/027, H01L21/268, H01L21/822, H01L27/06|
|Clasificación cooperativa||Y10S148/091, H01L21/0274, H01L21/268, H01L27/12, H01L27/0688, H01L21/86, H01L21/8221|
|Clasificación europea||H01L27/12, H01L21/268, H01L21/86, H01L21/027B6B, H01L21/822B, H01L27/06E|