US4654112A - Oxide etch - Google Patents
Oxide etch Download PDFInfo
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- US4654112A US4654112A US06/655,004 US65500484A US4654112A US 4654112 A US4654112 A US 4654112A US 65500484 A US65500484 A US 65500484A US 4654112 A US4654112 A US 4654112A
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- Prior art keywords
- oxygen
- plasma
- dielectric
- silicon
- nitrogen trifluoride
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- C—CHEMISTRY; METALLURGY
- C03—GLASS; MINERAL OR SLAG WOOL
- C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
- C03C15/00—Surface treatment of glass, not in the form of fibres or filaments, by etching
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/36—Imagewise removal not covered by groups G03F7/30 - G03F7/34, e.g. using gas streams, using plasma
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/942—Masking
- Y10S438/945—Special, e.g. metal
Definitions
- the present invention relates to an etch for fabrication of integrated circuits
- the present invention relates to selective etching of silicon oxides in integrated circuit fabrication processes.
- silicon oxides preferentially with respect to silicon in integrated circuit fabrication.
- an interlevel dielectric such as phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG) to a level comprising silicon (e.g. to moat or to polysilicon)
- PSG phosphosilicate glass
- BPSG borophosphosilicate glass
- a fluorine deficient plasma is used.
- a fluorine to carbon atomic ratio of about 2 to 1 is used, together with a small fraction (e.g. 5% or less mole percent) of oxygen. If too much oxygen is used, it scavenges the carbon as carbon monoxide, and etching proceeds in a fluorine-rich regime, wherein both silicon and silicon dioxide are etched.
- chemistry such as CHF3 plus O2 could be used, with the CF3 flowed at a rate much larger than that of the O2, according to the prior art.
- the present invention does not fit the prescription of the prior art at all, since (1) nitrogen trifluoride is used as the primary fluorine source (and preferably no carbon-bearing species is included at all); (2) the atomic composition of the etch gas mixture includes more oxygen than fluorine, and, in the presently preferred embodiment, oxygen is flowed at 10 times the rate of the nitrogen trifluoride.
- NF3 has been tried in many different plasma etch applications over the years, but no prior art suggests that a gas mixture which is mostly oxygen, with a little NF3 added, will etch oxide preferentially with respect to silicon.
- the prior art oxide-over-silicon preferential etches have inherent problems with residues. That is, there is always the problem of depositing polymeric residue in exposed areas, and the exact mass flow ratios and process chemistry and conditions must be painstakingly adjusted to get them within the narrow windows required for good selectivity without residue deposition.
- the oxide etch taught by the present invention does not leave residues, which is a tremendous advantage over the prior art.
- the nitrogen trifluoride plus oxygen chemistry turns out to have surprising advantages. In particular, it provides astonishing selectivity of oxide over silicon, contrary to the teachings of the prior art. See, for example: Donnelly, V. M., Flamm, D. L., Dautremont-Smith, W. C., and Werder, D. J., J. Appl. Phys., 55, 242 (1984).
- this chemistry gives 12 to 1 selectivity to etch phosphosilicate glass preferentially with respect to monocrystalline silicon. It gives 13 to 1 selectivity to etch PSG preferentially with respect to P-type polysilicon. It gives 2.2 to 1 selectivity of plasma oxide over silicon.
- the present invention is most particularly advantageous, as the above selectivities show, when the oxide to be etched is PSG or BPSG.
- a process for etching silicon oxides in integrated circuit structures comprising:
- FIG. 1 shows a sample structure where a contact hole is being cut using a cantilever-etch-mask process which uses the process of the present invention.
- the present invention will be described with reference to a cantilever-etch-mask process, wherein the oxide etch of the present invention is used to undercut an organic spacer layer under a patterned polysilicon hard mask and also etch a PSG layer under the organic spacer layer, but it will be recognized by those skilled in the art that the present invention can also be applied in the context of a wide variety of other integrated circuit fabrication processes.
- oxide 10 A sample embodiment of the present invention will now be described, where the object is to cut a contact hole in one micron of phosphosilicate glass overlying a 1000 Angstrom thick layer of plasma enhanced CVD oxide.
- This composite multi-level oxide structure is shown as oxide 10 in FIG. 1.
- AZ 1400-31 resist is spun on and baked at 180 degrees C., to form the spacer layer 12.
- about 5000 Angstroms of plasma enhanced CVD silicon is deposited atop the spacer layer 12.
- a top photoresist layer is deposited, exposed, developed, and post baked. (Note that it is preferable to eliminate the hot plate pre-bake step, prior to lithographic processing, lest the spacer resist should "bubble" underneath the PECVD Si layer.
- This top resist layer can be quite thin, since good planarity will have been provided by the layers 12 and 14.
- This thin top resist layer can be, for example 6000 Angstroms of a resist such AZ 1400-17.
- An anisotropic silicon etch is now used to cut the silicon hard mask layer 14 in accordance with the mask as defined in the top photoresist layer.
- the etch used at this step can be any conventional etch, such as, for example, one incorporating freon-12 chemistry.
- the key etching step of the present invention begins.
- the slices are now placed in a reactive ion etch reactor.
- a reactive ion etch reactor For example, an AME 8110 reactor is used, with power applied at 1000 watts at 13.56 megahertz.
- the gas mixture flowed includes oxygen at 100 SCCM and nitrogen trifluoride at 10 SCCM, for a total pressure of 100 microns (i.e. 100 milliTorr).
- the etching temperature is cooled to preferably a little cooler than ambient, e.g. 15 C. This cooling is not critical, but does assist in miminizes gross outgassing from the resist.
- This power density in an AME 8110 reactor translates to approximately 150 milliwatts per square centimeter.
- An alternative way of figuring power densities so as to transfer processes among different reactors is power per unit volume, and the volume of the amp 8110 reactor is approximately 150 liters, so that the power per volume in the plasma is roughly 61/2 watts per liter.
- this is a somewhat low pressure etching regime.
- the anode and cathode areas are unequal, so that this reactor is operated in what is commonly known as the RIE (reactive ion etching mode) regime.
- This etch is performed as a timed etch, e.g. for 75 minutes to process 24 slices in the above configuration. End point detection is not possible, since the area fraction of silicon exposed by the etch is such a small fraction of the total area, and since the silicon hard mask is exposed to the plasma in any case.
- This etch is preferably performed to achieve 30 percent over etch of the contact hole in the multi-layer 10. However, although this etch is merely a timed etch and not an end point-detecting etch, the timing has been found to be relatively insensitive.
- contact holes were etched simultaneously to moat (i.e. to the silicon substrate) and to an upper polysilicon layer, so that the upper polysilicon contact area was covered by approximately one micron less resist than was the moat area.
- the etch was timed to etch the moat area optimally, so that the polysilicon contact was greatly over etched.
- no difference in the contact size was visible.
- the presently preferred embodiment uses a total pressure of 100 microns, but this can be widely varied, over a range of at least 30 microns to 500 microns, or even more widely.
- the total pressure will typically be chosen to accomodate the anisotropy requirements of the particular process in which the present invention is incorporated.
- the present invention will provide adequate anisotropy for many processes.
- the silicon hard mask 14 will be etched, or at least pitted.
- adequate MLO etching cannot be achieved: a pure oxygen plasma will not cut oxide rapidly.
- the preferred range of nitrogen trifluoride admixture in the etching recipe is at least 2 SCCM, but must be less than the flow rate of oxygen used.
- the nitrogen trifluoride not only provides a fluorine source for anisotropic oxide etching, but also appears to assist in removal of residues.
- residues will be deposited if the nitrogen trifluoride is reduced to zero, but will not be deposited if even a few sccm of NF3 are flowed.
- NF3 as the sole fluorine-bearing species
- other embodiments may also include admixtures of fluorocarbon species or other fluorine-bearing species, as long as NF3 is present and the atomic fraction of oxygen in the whole mixture is greater than that of fluorine (and preferably at least four times greater than that of fluorine).
- the preferred flow of oxygen is 100 SCCM, but this can be in the range of 10 to 1000 SCCM. However, oxygen flow rates in the range of 30 to 200 SCCM are particularly preferred.
- the area power density is preferably 0.15 watts per square centimeter, but may be varied as much as a order of magnitude or more each way, as long as sufficient cooling power is provided.
- the nitrogen trifluoride plus oxygen chemistry turns out to have surprising advantages. In particular, it provides astonishing selectivity of oxide over silicon, contrary to the teachings of the prior art. See, for example: Donnelly, V. M., Flamm, D. L., Dangemont-Smith, W. C., and Werder, D. J., J. Appl. Phys., 55, 242 (1984).
- this chemistry gives 12 to 1 selectivity to etch phosphosilicate glass preferentially with respect to monocrystalline silicon. It gives 13 to 1 selectivity to etch PSG preferentially with respect to P-type polysilicon. It gives about 11 to 1 selectivity of PSG over undoped polysilicon. It also gives 5.6 to 1 selectivity of PSG over plasma oxide.
- the present invention is particularly advantageous for etching PSG or BPSG selectively with respect to silicon-bearing materials (crystalline silicon, or polysilicon, or metal silicides).
- etch chemistry A notable characteristic of this etch chemistry is that it will attack organic materials, such as photoresist, rapidly. This is disadvantageous in many applications, and requires use of a hardmask process in most applications. However, this very characteristic is advantageous for etching sloped oxide profiles utilizing the cantilever lithographic concept.
- a polysilicon hardmask is process-compatible with many processes, and the most preferred embodiments of the invention use a polysilicon hardmask.
- such a polysilicon hardmask is preferably combined with a planarizing layer underlying it, as in the principal preferred embodiment discussed above.
- the composition of the spacer layer 12 can be selected from a wide variety of planarizing polymers. However, it should be noted that poly(methyl methacrylate) is not very suitable for this layer. Novolac-type photoresist is much more suitable. In general, it is believed that photoresist comprising stable aromatic groups, which AZ does and which PMMA does not have, are more suitable.
- the present invention provides a new class of chemistries for etching silicon oxides preferentially with respect to silicon or silicides.
Abstract
A new process for plasma etching silicon oxides in integrated circuit structures. A chemistry comprising both oxygen and nitrogen trifluoride is used, with oxygen the dominant component. This provides excellent selectivity to silicon. This etch chemistry also erodes photoresist rapidly, so that it is typically used in combination with a hard-masking process. One particular application of this invention is in a cantilever-etch-mask contact profiling process.
Description
The present invention relates to an etch for fabrication of integrated circuits
In particular, the present invention relates to selective etching of silicon oxides in integrated circuit fabrication processes.
It is very frequently necessary to etch silicon oxides preferentially with respect to silicon in integrated circuit fabrication. For example, when a contact is being cut through an interlevel dielectric such as phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG) to a level comprising silicon (e.g. to moat or to polysilicon), the etch must be selective in this respect.
Conventionally, to etch oxide preferentially with respect to silicon, a fluorine deficient plasma is used. Typically a fluorine to carbon atomic ratio of about 2 to 1 is used, together with a small fraction (e.g. 5% or less mole percent) of oxygen. If too much oxygen is used, it scavenges the carbon as carbon monoxide, and etching proceeds in a fluorine-rich regime, wherein both silicon and silicon dioxide are etched. Thus, chemistry such as CHF3 plus O2 could be used, with the CF3 flowed at a rate much larger than that of the O2, according to the prior art.
However, the present invention does not fit the prescription of the prior art at all, since (1) nitrogen trifluoride is used as the primary fluorine source (and preferably no carbon-bearing species is included at all); (2) the atomic composition of the etch gas mixture includes more oxygen than fluorine, and, in the presently preferred embodiment, oxygen is flowed at 10 times the rate of the nitrogen trifluoride. NF3 has been tried in many different plasma etch applications over the years, but no prior art suggests that a gas mixture which is mostly oxygen, with a little NF3 added, will etch oxide preferentially with respect to silicon.
Moreover, the prior art oxide-over-silicon preferential etches have inherent problems with residues. That is, there is always the problem of depositing polymeric residue in exposed areas, and the exact mass flow ratios and process chemistry and conditions must be painstakingly adjusted to get them within the narrow windows required for good selectivity without residue deposition. The oxide etch taught by the present invention does not leave residues, which is a tremendous advantage over the prior art.
This is particularly advantageous in contact etching, where deposition of residues at the bottom of the contact hole will not only degrade the contact resistance, but will introduce greater random variation in this parameter, i.e. will degrade process control.
This is also advantageous in the direct moat isolation processes, wherein the field oxide, instead of being grown in a pattern, is grown (or deposited) everywhere and then etched in a pattern. In this technology the oxide etch which clears the field oxide will contact the naked surface of the moat, so that any residue deposition may cause gate oxide defects.
Thus it is an object of the present invention to provide an etchant for etching silicon oxides preferentially with respect to silicon.
It is a further object of the present invention to provide an etchant, for etching silicon oxides preferentially with respect to silicon, which does not deposit residues.
Thus it is an object of the present invention to provide an etchant for etching silicon oxides preferentially with respect to metal silicides.
It is a further object of the present invention to provide an etchant, for etching silicon oxides preferentially with respect to silicides, which does not deposit residues.
The nitrogen trifluoride plus oxygen chemistry turns out to have surprising advantages. In particular, it provides astonishing selectivity of oxide over silicon, contrary to the teachings of the prior art. See, for example: Donnelly, V. M., Flamm, D. L., Dautremont-Smith, W. C., and Werder, D. J., J. Appl. Phys., 55, 242 (1984). For example, this chemistry gives 12 to 1 selectivity to etch phosphosilicate glass preferentially with respect to monocrystalline silicon. It gives 13 to 1 selectivity to etch PSG preferentially with respect to P-type polysilicon. It gives 2.2 to 1 selectivity of plasma oxide over silicon.
Thus, the nitrogen trifluoride plus oxygen chemistry taught by the present invention, which is inherently very resistant to residue deposition, has substantial advantages in this respect.
A notable characteristic of this etch chemistry is that it will attack organic materials, such as photoresist, rapidly. This is disadvantageous in many applications, and requires use of a hardmask process in most applications.
The present invention is most particularly advantageous, as the above selectivities show, when the oxide to be etched is PSG or BPSG.
According to the present invention there is provided:
A process for etching silicon oxides in integrated circuit structures, comprising:
providing a partially fabricated integrated circuit structure having at the surface thereof a dielectric comprising silicon oxides;
partially covering said dielectric with a patterned hardmask;
exposing said integrated circuit structure to a plasma in a gas comprising both oxygen and nitrogen trifluoride, the input gas to said plasma comprising more oxygen than nitrogen trifluoride.
The present invention will be described with reference to the accompanying drawings in which:
FIG. 1 shows a sample structure where a contact hole is being cut using a cantilever-etch-mask process which uses the process of the present invention.
The present invention will be described with reference to a cantilever-etch-mask process, wherein the oxide etch of the present invention is used to undercut an organic spacer layer under a patterned polysilicon hard mask and also etch a PSG layer under the organic spacer layer, but it will be recognized by those skilled in the art that the present invention can also be applied in the context of a wide variety of other integrated circuit fabrication processes.
A sample embodiment of the present invention will now be described, where the object is to cut a contact hole in one micron of phosphosilicate glass overlying a 1000 Angstrom thick layer of plasma enhanced CVD oxide. This composite multi-level oxide structure is shown as oxide 10 in FIG. 1.
Next, in the presently preferred embodiment, about 3 microns of AZ 1400-31 resist is spun on and baked at 180 degrees C., to form the spacer layer 12. Next, about 5000 Angstroms of plasma enhanced CVD silicon is deposited atop the spacer layer 12. Next, a top photoresist layer is deposited, exposed, developed, and post baked. (Note that it is preferable to eliminate the hot plate pre-bake step, prior to lithographic processing, lest the spacer resist should "bubble" underneath the PECVD Si layer. This top resist layer can be quite thin, since good planarity will have been provided by the layers 12 and 14. This thin top resist layer can be, for example 6000 Angstroms of a resist such AZ 1400-17.
An anisotropic silicon etch is now used to cut the silicon hard mask layer 14 in accordance with the mask as defined in the top photoresist layer. The etch used at this step can be any conventional etch, such as, for example, one incorporating freon-12 chemistry.
Next, the key etching step of the present invention begins. In the sample embodiment, the slices are now placed in a reactive ion etch reactor. For example, an AME 8110 reactor is used, with power applied at 1000 watts at 13.56 megahertz. The gas mixture flowed includes oxygen at 100 SCCM and nitrogen trifluoride at 10 SCCM, for a total pressure of 100 microns (i.e. 100 milliTorr). The etching temperature is cooled to preferably a little cooler than ambient, e.g. 15 C. This cooling is not critical, but does assist in miminizes gross outgassing from the resist.
This power density in an AME 8110 reactor translates to approximately 150 milliwatts per square centimeter. An alternative way of figuring power densities so as to transfer processes among different reactors is power per unit volume, and the volume of the amp 8110 reactor is approximately 150 liters, so that the power per volume in the plasma is roughly 61/2 watts per liter.
As will be noted, this is a somewhat low pressure etching regime. Moreover, the anode and cathode areas are unequal, so that this reactor is operated in what is commonly known as the RIE (reactive ion etching mode) regime.
This etch is performed as a timed etch, e.g. for 75 minutes to process 24 slices in the above configuration. End point detection is not possible, since the area fraction of silicon exposed by the etch is such a small fraction of the total area, and since the silicon hard mask is exposed to the plasma in any case. This etch is preferably performed to achieve 30 percent over etch of the contact hole in the multi-layer 10. However, although this etch is merely a timed etch and not an end point-detecting etch, the timing has been found to be relatively insensitive.
In a further test of the present invention, contact holes were etched simultaneously to moat (i.e. to the silicon substrate) and to an upper polysilicon layer, so that the upper polysilicon contact area was covered by approximately one micron less resist than was the moat area. The etch was timed to etch the moat area optimally, so that the polysilicon contact was greatly over etched. However, no difference in the contact size was visible.
The presently preferred embodiment uses a total pressure of 100 microns, but this can be widely varied, over a range of at least 30 microns to 500 microns, or even more widely. The total pressure will typically be chosen to accomodate the anisotropy requirements of the particular process in which the present invention is incorporated. The present invention will provide adequate anisotropy for many processes.
If an excessive amount of nitrogen trifluoride is used, the silicon hard mask 14 will be etched, or at least pitted. Alternatively, if no nitrogen trifluoride is used, adequate MLO etching cannot be achieved: a pure oxygen plasma will not cut oxide rapidly. Thus, the preferred range of nitrogen trifluoride admixture in the etching recipe is at least 2 SCCM, but must be less than the flow rate of oxygen used.
The nitrogen trifluoride not only provides a fluorine source for anisotropic oxide etching, but also appears to assist in removal of residues. For example, in the foregoing cantilever-etch-mask embodiment, where the organic spacer layer provides a carbon source, residues will be deposited if the nitrogen trifluoride is reduced to zero, but will not be deposited if even a few sccm of NF3 are flowed. Thus, although the presently preferred embodiment uses NF3 as the sole fluorine-bearing species, other embodiments may also include admixtures of fluorocarbon species or other fluorine-bearing species, as long as NF3 is present and the atomic fraction of oxygen in the whole mixture is greater than that of fluorine (and preferably at least four times greater than that of fluorine).
The preferred flow of oxygen is 100 SCCM, but this can be in the range of 10 to 1000 SCCM. However, oxygen flow rates in the range of 30 to 200 SCCM are particularly preferred.
The area power density is preferably 0.15 watts per square centimeter, but may be varied as much as a order of magnitude or more each way, as long as sufficient cooling power is provided.
The nitrogen trifluoride plus oxygen chemistry turns out to have surprising advantages. In particular, it provides astonishing selectivity of oxide over silicon, contrary to the teachings of the prior art. See, for example: Donnelly, V. M., Flamm, D. L., Dautremont-Smith, W. C., and Werder, D. J., J. Appl. Phys., 55, 242 (1984). For example, this chemistry gives 12 to 1 selectivity to etch phosphosilicate glass preferentially with respect to monocrystalline silicon. It gives 13 to 1 selectivity to etch PSG preferentially with respect to P-type polysilicon. It gives about 11 to 1 selectivity of PSG over undoped polysilicon. It also gives 5.6 to 1 selectivity of PSG over plasma oxide. Thus, the present invention is particularly advantageous for etching PSG or BPSG selectively with respect to silicon-bearing materials (crystalline silicon, or polysilicon, or metal silicides).
A notable characteristic of this etch chemistry is that it will attack organic materials, such as photoresist, rapidly. This is disadvantageous in many applications, and requires use of a hardmask process in most applications. However, this very characteristic is advantageous for etching sloped oxide profiles utilizing the cantilever lithographic concept.
In particular, a polysilicon hardmask is process-compatible with many processes, and the most preferred embodiments of the invention use a polysilicon hardmask.
Even more specifically, such a polysilicon hardmask is preferably combined with a planarizing layer underlying it, as in the principal preferred embodiment discussed above.
The composition of the spacer layer 12 can be selected from a wide variety of planarizing polymers. However, it should be noted that poly(methyl methacrylate) is not very suitable for this layer. Novolac-type photoresist is much more suitable. In general, it is believed that photoresist comprising stable aromatic groups, which AZ does and which PMMA does not have, are more suitable.
Thus, the present invention provides a new class of chemistries for etching silicon oxides preferentially with respect to silicon or silicides.
As will be obvious to those skilled in the art, the present invention can be widely modified and varied, and is not limited except as specified in the accompanying claims.
Claims (10)
1. A process for etching silicon oxides in integrated circuit structures, comprising the steps of:
providing a partially fabricated integrated circuit structure having at the surface thereof a dielectric comprising silicon oxides;
partially covering said dielectric with a patterned hardmask; and
exposing said integrated circuit structure to a plasma in a gas comprising both oxygen and nitrogen trifluoride, the input gas to said plasma comprising more oxygen than nitrogen trifluoride.
2. The process of claim 1, wherein said plasma is generated in a gas having a total pressure in a range between 30 microns and 500 microns.
3. The process of claim 1, wherein said plasma includes more than four times as much oxygen as nitrogen trifluoride.
4. The process of claim 1, wherein said plasma generation step comprises applying power at an area density in the range between 1 and 0.05 watts per square centimeter.
5. The process of claim 1, wherein said plasma generating step comprises applying power at a volumetric density between 1 and 10 watts per liter into said gas mixture in the vicinity of said partially fabricated integrated within a reactor chamber.
6. The process of claim 1, wherein said hardmask consists essentially of polysilicon.
7. The process of claim 1, wherein said dielectric consists essentially of phosphosilicate glass.
8. The process of claim 1, wherein said hard mask layer comprises silicon.
9. The process of claim 1, wherein said dielectric comprises borophosphosilicate glass.
10. A process for fabricating contacts in integrated circuits, comprising the steps of:
providing a partially fabricated integrated circuit structure having at the surface thereof a dielectric comprising silicon oxides;
depositing a hard mask layer comprising silicon over said dielectric;
etching said hard mask layer in a predetermined pattern to cut holes in said hard mask layer at predetermined contact locations;
exposing said integrated circuit structure to a plasma in a gas comprising both oxygen and nitrogen trifluoride, said gas comprising more oxygen than nitrogen trifluoride, to open contact holes in said dielectric;
and depositing a patterned conductor to interconnect said contact holes in a predetermined circuit configuration.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/655,004 US4654112A (en) | 1984-09-26 | 1984-09-26 | Oxide etch |
| JP21358985A JPH0656844B2 (en) | 1984-09-26 | 1985-09-26 | Oxide etch treatment method and etchant used therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/655,004 US4654112A (en) | 1984-09-26 | 1984-09-26 | Oxide etch |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| US4654112A true US4654112A (en) | 1987-03-31 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US06/655,004 Expired - Lifetime US4654112A (en) | 1984-09-26 | 1984-09-26 | Oxide etch |
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| US (1) | US4654112A (en) |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4807016A (en) * | 1985-07-15 | 1989-02-21 | Texas Instruments Incorporated | Dry etch of phosphosilicate glass with selectivity to undoped oxide |
| EP0482519A1 (en) * | 1990-10-19 | 1992-04-29 | Tokyo Electron Limited | Method of etching oxide materials |
| US5228950A (en) * | 1990-12-04 | 1993-07-20 | Applied Materials, Inc. | Dry process for removal of undesirable oxide and/or silicon residues from semiconductor wafer after processing |
| US5413670A (en) * | 1993-07-08 | 1995-05-09 | Air Products And Chemicals, Inc. | Method for plasma etching or cleaning with diluted NF3 |
| US5468342A (en) * | 1994-04-28 | 1995-11-21 | Cypress Semiconductor Corp. | Method of etching an oxide layer |
| US5562801A (en) * | 1994-04-28 | 1996-10-08 | Cypress Semiconductor Corporation | Method of etching an oxide layer |
| US5633534A (en) * | 1993-12-06 | 1997-05-27 | Sgs-Thomson Microelectronics, Inc. | Integrated circuit with enhanced planarization |
| US5793114A (en) * | 1993-12-17 | 1998-08-11 | Sgs-Thomson Microelectronics, Inc. | Self-aligned method for forming contact with zero offset to gate |
| US5814563A (en) * | 1996-04-29 | 1998-09-29 | Applied Materials, Inc. | Method for etching dielectric using fluorohydrocarbon gas, NH3 -generating gas, and carbon-oxygen gas |
| US5843847A (en) * | 1996-04-29 | 1998-12-01 | Applied Materials, Inc. | Method for etching dielectric layers with high selectivity and low microloading |
| US5913131A (en) * | 1996-11-14 | 1999-06-15 | Advanced Micro Devices, Inc. | Alternative process for BPTEOS/BPSG layer formation |
| US6027861A (en) * | 1998-03-20 | 2000-02-22 | Taiwan Semiconductor Manufacturing Company | VLSIC patterning process |
| US6051864A (en) * | 1993-12-17 | 2000-04-18 | Stmicroelectronics, Inc. | Memory masking for periphery salicidation of active regions |
| US6067999A (en) * | 1998-04-23 | 2000-05-30 | International Business Machines Corporation | Method for deposition tool cleaning |
| US6107194A (en) * | 1993-12-17 | 2000-08-22 | Stmicroelectronics, Inc. | Method of fabricating an integrated circuit |
| US6451184B1 (en) * | 1997-02-19 | 2002-09-17 | Canon Kabushiki Kaisha | Thin film forming apparatus and process for forming thin film using same |
| US6719808B1 (en) * | 1999-10-27 | 2004-04-13 | Samsung Electronics Co., Ltd. | Method of and apparatus for manufacturing a semiconductor device using a polysilicon hard mask |
| US20070281491A1 (en) * | 2006-06-05 | 2007-12-06 | Lam Research Corporation | Residue free hardmask trim |
| US9966232B2 (en) | 2012-12-14 | 2018-05-08 | The Penn State Research Foundation | Ultra-high speed anisotropic reactive ion etching |
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Cited By (34)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4807016A (en) * | 1985-07-15 | 1989-02-21 | Texas Instruments Incorporated | Dry etch of phosphosilicate glass with selectivity to undoped oxide |
| EP0482519A1 (en) * | 1990-10-19 | 1992-04-29 | Tokyo Electron Limited | Method of etching oxide materials |
| US5302236A (en) * | 1990-10-19 | 1994-04-12 | Tokyo Electron Limited | Method of etching object to be processed including oxide or nitride portion |
| US5228950A (en) * | 1990-12-04 | 1993-07-20 | Applied Materials, Inc. | Dry process for removal of undesirable oxide and/or silicon residues from semiconductor wafer after processing |
| US5413670A (en) * | 1993-07-08 | 1995-05-09 | Air Products And Chemicals, Inc. | Method for plasma etching or cleaning with diluted NF3 |
| US5837613A (en) * | 1993-12-06 | 1998-11-17 | Stmicroelectronics, Inc. | Enhanced planarization technique for an integrated circuit |
| USRE39690E1 (en) * | 1993-12-06 | 2007-06-12 | Stmicroelectronics, Inc. | Enhanced planarization technique for an integrated circuit |
| US5986330A (en) * | 1993-12-06 | 1999-11-16 | Stmicroelectronics, Inc. | Enhanced planarization technique for an integrated circuit |
| US5633534A (en) * | 1993-12-06 | 1997-05-27 | Sgs-Thomson Microelectronics, Inc. | Integrated circuit with enhanced planarization |
| US5793114A (en) * | 1993-12-17 | 1998-08-11 | Sgs-Thomson Microelectronics, Inc. | Self-aligned method for forming contact with zero offset to gate |
| US6051864A (en) * | 1993-12-17 | 2000-04-18 | Stmicroelectronics, Inc. | Memory masking for periphery salicidation of active regions |
| US6661064B2 (en) | 1993-12-17 | 2003-12-09 | Stmicroelectronics, Inc. | Memory masking for periphery salicidation of active regions |
| US6514811B2 (en) | 1993-12-17 | 2003-02-04 | Stmicroelectronics, Inc. | Method for memory masking for periphery salicidation of active regions |
| US6284584B1 (en) | 1993-12-17 | 2001-09-04 | Stmicroelectronics, Inc. | Method of masking for periphery salicidation of active regions |
| US6107194A (en) * | 1993-12-17 | 2000-08-22 | Stmicroelectronics, Inc. | Method of fabricating an integrated circuit |
| US5562801A (en) * | 1994-04-28 | 1996-10-08 | Cypress Semiconductor Corporation | Method of etching an oxide layer |
| US5468342A (en) * | 1994-04-28 | 1995-11-21 | Cypress Semiconductor Corp. | Method of etching an oxide layer |
| US5814563A (en) * | 1996-04-29 | 1998-09-29 | Applied Materials, Inc. | Method for etching dielectric using fluorohydrocarbon gas, NH3 -generating gas, and carbon-oxygen gas |
| US5843847A (en) * | 1996-04-29 | 1998-12-01 | Applied Materials, Inc. | Method for etching dielectric layers with high selectivity and low microloading |
| US6097079A (en) * | 1996-11-14 | 2000-08-01 | Advanced Micro Devices, Inc. | Boron implanted dielectric structure |
| US5913131A (en) * | 1996-11-14 | 1999-06-15 | Advanced Micro Devices, Inc. | Alternative process for BPTEOS/BPSG layer formation |
| US6451184B1 (en) * | 1997-02-19 | 2002-09-17 | Canon Kabushiki Kaisha | Thin film forming apparatus and process for forming thin film using same |
| US6027861A (en) * | 1998-03-20 | 2000-02-22 | Taiwan Semiconductor Manufacturing Company | VLSIC patterning process |
| US6067999A (en) * | 1998-04-23 | 2000-05-30 | International Business Machines Corporation | Method for deposition tool cleaning |
| US6719808B1 (en) * | 1999-10-27 | 2004-04-13 | Samsung Electronics Co., Ltd. | Method of and apparatus for manufacturing a semiconductor device using a polysilicon hard mask |
| US20070281491A1 (en) * | 2006-06-05 | 2007-12-06 | Lam Research Corporation | Residue free hardmask trim |
| WO2007143585A2 (en) * | 2006-06-05 | 2007-12-13 | Lam Research Corporation | Residue free hardmask trim |
| WO2007143585A3 (en) * | 2006-06-05 | 2008-02-28 | Lam Res Corp | Residue free hardmask trim |
| CN101461044A (en) * | 2006-06-05 | 2009-06-17 | 朗姆研究公司 | Residue free hardmask trim |
| US7851369B2 (en) | 2006-06-05 | 2010-12-14 | Lam Research Corporation | Hardmask trim method |
| US20110049099A1 (en) * | 2006-06-05 | 2011-03-03 | Lam Research Corporation | Hardmask trim method |
| US8124540B2 (en) | 2006-06-05 | 2012-02-28 | Lam Research Corporation | Hardmask trim method |
| CN101461044B (en) * | 2006-06-05 | 2013-09-04 | 朗姆研究公司 | Residue free hardmask trim |
| US9966232B2 (en) | 2012-12-14 | 2018-05-08 | The Penn State Research Foundation | Ultra-high speed anisotropic reactive ion etching |
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