US4692205A - Silicon-containing polyimides as oxygen etch stop and dual dielectric coatings - Google Patents

Silicon-containing polyimides as oxygen etch stop and dual dielectric coatings Download PDF

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US4692205A
US4692205A US06/824,893 US82489386A US4692205A US 4692205 A US4692205 A US 4692205A US 82489386 A US82489386 A US 82489386A US 4692205 A US4692205 A US 4692205A
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layer
substrate
silicon
lift
containing polyimide
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US06/824,893
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Krishna G. Sachdev
Ranee W. Kwong
Mani R. Gupta
Mark S. Chace
Harbans S. Sachdev
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International Business Machines Corp
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Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION, A CORP. OF NEW YORK reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION, A CORP. OF NEW YORK ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: CHACE, MARK S., GUPTA, MANI R., KWONG, RANEE WAI-LING, SACHDEV, HARBANS S., SACHDEV, KRISHNA G.
Priority to JP61292649A priority patent/JPS62185325A/en
Priority to EP19860117617 priority patent/EP0230615A3/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/075—Silicon-containing compounds
    • G03F7/0757—Macromolecular compounds containing Si-O, Si-C or Si-N bonds
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/094—Multilayer resist systems, e.g. planarising layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/312—Organic layers, e.g. photoresist
    • H01L21/3121—Layers comprising organo-silicon compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/7688—Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S428/00—Stock material or miscellaneous articles
    • Y10S428/901—Printed circuit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/95—Multilayer mask including nonradiation sensitive layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/97—Specified etch stop material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12389—All metal or with adjacent metals having variation in thickness
    • Y10T428/12396—Discontinuous surface component
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
    • Y10T428/12528—Semiconductor component
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/31504—Composite [nonstructural laminate]
    • Y10T428/31721—Of polyimide

Definitions

  • This invention relates to the fabrication of semiconductor components such as integrated circuits.
  • silicon-containing polyimides as an oxygen etch barrier in a metal lift-off process and as an oxygen etch stop in the fabrication of multi-layer metal structures is disclosed.
  • the lift-off method for forming metallized structures generally involves the fabrication of a multi-layer stencil comprising a solvent removable polymer film as the base or lift-off layer on a substrate.
  • This lift-off layer is sequentially overcoated with a thin oxygen reactive ion etch (RIE) barrier and a resist layer.
  • RIE reactive ion etch
  • the desired pattern in the resist is delineated by standard lithographic techniques and then replicated into the underlying barrier layer by the RIE process using CF 4 ambient, followed by O 2 to etch the pattern into the lift-off layer.
  • Subsequent blanket metal evaporation and solvent soak e.g., N-methylpyrrolidone (NMP) is employed to accomplish the removal of the lift-off stencil, leaving the desired metal pattern intact.
  • NMP N-methylpyrrolidone
  • the conventional O 2 RIE barrier films as employed in the prior art include SiO x , Si 3 N 4 , sputtered quartz, polydimethylsiloxane resins, and plasma-polymerized organosilicon films.
  • the conventional barrier films have been employed effectively as masking layers for O 2 RIE processes in multi-layer metal structures, there are several major drawbacks associated with the use of these materials as discussed below.
  • inorganic films such as silicon oxide and silicon nitride.
  • These high temperatures can be detrimental to underlying organic polymer films resulting in reticulation and shriveling, in addition to the formation of debris at the organic/inorganic film interface.
  • inorganic thin films invariably show high defect density (pinholes) which render them unacceptable for the fine line lithography required in the fabrication of high density integrated circuits.
  • Inorganic barrier films in contact with organic polymer films such as polyimide also have problems of process induced stress cracking of the entire structure due to the mismatch in the coefficients of thermal expansion and the residual stress levels in inorganic versus organic films.
  • Plasma polymerized organosilicon films for use as O 2 RIE resistant layers as described in U.S. Pat. No. 4,493,855 to Sachdev et al., are free from the problems of the other prior art previously mentioned.
  • the solution coated barrier films of this invention provide an inexpensive alternative requiring no special tooling and are specially suited for high volume manufacturing.
  • a further advantage of the barrier films of this invention is the superior adhesion to a variety of organic and inorganic contacting layers without requiring any special surface preparation.
  • U.S Pat. No. 4,430,153 to Gleason et al. discloses the in-situ conversion of an alkyl polyamide/polyimide surface layer to a silicon-containing alkyl polyamide/polyimide layer. This process, however, is unsuitable for practical applications requiring metal lift-off structures due to interference of the processing solvents with the mechanical integrity of the solvent removable lift-off layers. Also, this treatment does not provide an effective O 2 RIE resistance necessary for pattern transfer into the underlayer.
  • Another object of this invention is to provide a simple alternative to the Si 3 N 4 , SiO x deposited by CVD or plasma-enhanced CVD processes, plasma polymerized organosilicons such as HMDS (hexamethyldisilazane) or hexamethyldisiloxane used as oxygen etch stops and dual dielectric in the fabrication of multi-level metal structures.
  • HMDS hexamethyldisilazane
  • hexamethyldisiloxane used as oxygen etch stops
  • dual dielectric in the fabrication of multi-level metal structures.
  • the fabrication of multi-level metal structures is carried out according to the multi-layer resist process utilizing pre-formed silicon-containing polyimides as O 2 /RIE barriers and etch stops.
  • the silicon-containing polyimides either spun-on or sprayed-on, have the requisite properties in terms of the thermal stability, glass transition temperature, mechanical properties, solvent resistance, compatibility of thermal coefficients of expansion with contacting films, and the necessary O 2 etch resistance.
  • Thin films of silicon-containing polyimide formulations utilized in this invention are pinhole free, provide the desired overhang after RIE into the underlying lift-off layer, show no outgassing or fencing during metallization, and allow for clean lift-off in the usual solvent soak to provide excellent metal pattern.
  • the barrier films according to this invention exhibit excellent O 2 RIE resistance, adhesion to commonly employed lift-off layers, resist films, inter-level dielectric layers such as polyimide, and inorganic layers such as silicon oxide, silicon nitride, etc.
  • the silicon-containing polyimides as utilized in this invention, can remain as an integral part of the structure in packaging technology if desired.
  • FIGS. 1A-F illustrate schematically the steps of a tri-layer resist process made possible by the present invention.
  • FIGS. 2A-E illustrate schematically the steps of a bi-layer resist process made possible by the present invention.
  • a substrate 10 such as a siliccn wafer having semiconductor devices, is surface treated with a 0.1% aqueous solution of ⁇ -aminopropyltriethoxysilane ( ⁇ -APS) by spin application at 2,000 RPM for 30 seconds, followed by a 5 minute bake at 85° C. (hot plate).
  • the surface treatment enhances the adhesion between the substrate 10 and a subsequently applied underlayer 12.
  • the lift-off underlayer is spin applied at 2,000 RPM for 30 seconds and baked at 85° C. for 10 minutes, 150° C. for 15 minutes, and 230° C. for 20 minutes, to form an approximately 2.1 micron thick coating.
  • AZ1350J commercially available from the Shipley Company has been used advantageously as the lift-off layer.
  • the lift-off layer is not critical so long as it can be etched with O 2 plasma or RIE processing.
  • This layer typically includes organic polymers such as AZ1350, AZ1350J (products of Shipley Co.), polysulfone resin (ICI Company), or soluble polyimides.
  • Silicon-containing polyimide #250-65 or #250-50 available commercially from the M&T Company, is diluted 1:2.5 with diglyme, filtered through a 0.45 micron silver filter, and spin-applied on the baked lift-off layer 12 at 3,000 RPM for 30 seconds.
  • a bake sequence of 85° C. for 10 minutes, 150° C. for 15 minutes, and 230° C. for 20 minutes follows, resulting in an approximately 0.25-0.30 micron thick layer of the silicon polyimide.
  • a layer of resist 16 is applied over the silicon-containing polyimide barrier layer 14.
  • the surface of silicon-polyimide layer 14 is pre-treated with HMDS- ⁇ APE vapor in Freon-TF for 5 minutes or with a 0.1% solution of a ⁇ -APS in toluene by spin coating.
  • the layer of diazonaphthoquinone-novolak resist 16 is applied at 3,000 RPM for 30 seconds followed by a 30 minute bake at 85° C. to form a thick film approximately 0.9-1.1 microns thick.
  • the resist layer 16 can be a standard resist material known in the art, it may be positive or negative, and may be sensitive to near, mid or deep UV; electron beam; X-ray; ion beam; or laser. Examples are novolak based resists with diazoquinone type of photoactive component, acrylate polymers such as PMMA, polyolefin sulfones, etc. Patterning of the resist can be carried out according to standard lithographic processes.
  • resist layer 16 is developed with AZ2401 (Shipley Co.) developer diluted 1:3.5 with deionized water (FIG. 1B).
  • the image in the resist layer 16 is subsequently replicated into the silicon-containing polyimide layer 14 by RIE using a CF 4 -O 2 mixed gas system at a 2.5:1 flow rate ratio at 38-48 mtorr, with power level in the range 250-300 watts. Under these conditions, the barrier layer 14 can be etched at the rate of 1100-1300 Angstroms/min. The resulting structure is shown in FIG. 1C.
  • the silicon-containing polyimide layer 14 and exposed areas of substrate 10 are sputter cleaned for 6 minutes at 220° C. prior to metallization.
  • a blanket layer of metal 22, such as Al-Cu, is evaporated over the exposed surfaces at 120° to 150° C.
  • the lift-off is accomplished by the standard solvent soak in NMP for 2 hours with brief ultrasonic agitation to accelerate removal of the lift-off stencil, leaving the metallurgy network 22 as shown in FIG. 1F.
  • the metal film may be any metal conventionally employed, e.g., aluminum, copper alloy, palladium, platinum, chromium, etc.
  • soluble polyimide XU284, manufactured by CIBA GEIGY, or other lift-off layers can be used in place of the baked AZ layer 12 without departing from the scope of this invention.
  • the lift-off layer can be 1-5 ⁇ m in thickness, the silicon polyimide layer is typically in the range 0.15-0.65 ⁇ m and the imaging layer thickness is adjusted such that the desired level of image resolution and reduction of defect density is achieved.
  • the imaging layer thickness is typically in the range 0.15-7.2 ⁇ m. All other processing steps would follow as described above.
  • a substrate 30, which can be a semiconductor wafer or packaging substrate, is provided.
  • a lift-off layer 32 which can be a photoresist material or other polymer, is next applied on the substrate 30 as previously described.
  • a 10% solution of silicon-polyimide BE221 (available from M&T Company) in NMP is doped with a diazonaphthoquinone-based photoactive compound (PAC).
  • PAC diazonaphthoquinone-based photoactive compound
  • the photoactive compound comprises approximately 18% of the solution.
  • the mixture is filtered through a 0.2 micron silver filter and spin applied on lift-off layer 32.
  • the resulting silicon-polyimide/PAC layer 34 is exposed to mid-UV exposure through mask 38 for approximately 20 seconds.
  • metal 38 is blanket deposited on the layer 34 and exposed areas of substrate 30 (FIG. 2D), resulting in the metallurgy pattern after removal of the lift-off stencil as seen in FIG. 2E.
  • the base substrate may be silicon wafers, ceramic substrates, polyimide packaging layers, other polymeric films used in semiconductor processing, silicon wafers or ceramic substrates with one or more layers of insulating materials or dielectric layers, etc. Even a layer of silicon-containing polyimide could be present as a dielectric layer. Additionally, other structures of silicon-containing polyimides may be used other then those specifically disclosed. Accordingly, the process herein disclosed is to be considered merely as illustrative, and the invention is to be limited only as specified in the claims.

Abstract

The use of silicon-containing polyimide as an oxygen etch barrier in a metal lift-off process and as an oxygen etch stop in the fabrication of multi-layer metal structures is described. In practice, a lift-off layer is applied on a substrate, followed by a layer of silicon-containing polyimide and a layer of photoresist. The photoresist is lithographically patterned, and the developed image is transferred into the silicon-containing polyimide layer with a reactive ion etch using a CF4 /O2 gas mixture. The pattern is transferred to the lift-off layer in a reactive ion etch process using oxygen. Subsequent blanket metal evaporation followed by removal of the lift-off stencil results in the desired metal pattern on the substrate. In an alternate embodiment, the silicon-containing polyimide can be doped with a photoactive compound reducing the need for a separate photoresist imaging layer on the top.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the fabrication of semiconductor components such as integrated circuits. In particular, the use of silicon-containing polyimides as an oxygen etch barrier in a metal lift-off process and as an oxygen etch stop in the fabrication of multi-layer metal structures is disclosed.
2. Background Information
Improved materials and processes are required in advanced integrated circuit technology to meet the demands of fabricating high density interconnective multi-level metallurgy systems. In the lift-off method for fabricating fine metal lines, it is required that the contacting films maintain mechanical and interfacial integrity during the various processing steps; have requisite etch characteristics for compatibility with dry etch process schemes; and show the necessary thermal stability to allow high temperature metallization without any problem of outgassing, or image deformation.
The lift-off method for forming metallized structures generally involves the fabrication of a multi-layer stencil comprising a solvent removable polymer film as the base or lift-off layer on a substrate. This lift-off layer is sequentially overcoated with a thin oxygen reactive ion etch (RIE) barrier and a resist layer. The desired pattern in the resist is delineated by standard lithographic techniques and then replicated into the underlying barrier layer by the RIE process using CF4 ambient, followed by O2 to etch the pattern into the lift-off layer. Subsequent blanket metal evaporation and solvent soak (e.g., N-methylpyrrolidone (NMP)) is employed to accomplish the removal of the lift-off stencil, leaving the desired metal pattern intact.
The conventional O2 RIE barrier films as employed in the prior art include SiOx, Si3 N4, sputtered quartz, polydimethylsiloxane resins, and plasma-polymerized organosilicon films. Although the conventional barrier films have been employed effectively as masking layers for O2 RIE processes in multi-layer metal structures, there are several major drawbacks associated with the use of these materials as discussed below.
Relatively high temperatures, e.g., 200° to 275° C. are required for the deposition of inorganic films such as silicon oxide and silicon nitride. These high temperatures, however, can be detrimental to underlying organic polymer films resulting in reticulation and shriveling, in addition to the formation of debris at the organic/inorganic film interface. Furthermore, inorganic thin films invariably show high defect density (pinholes) which render them unacceptable for the fine line lithography required in the fabrication of high density integrated circuits. Inorganic barrier films in contact with organic polymer films such as polyimide also have problems of process induced stress cracking of the entire structure due to the mismatch in the coefficients of thermal expansion and the residual stress levels in inorganic versus organic films.
The solution coated thin films of spun-on glass utilized in the prior art, Franco, et al., U.S. Pat. No. 4,004,044 suffer from the problem of being susceptible to cracking above 250° to 300° C. when in contact with organic polymer films. Also, the glass-resin formulations have short shelf life and undergo formation of microgels which interfere with the film quality, resulting in a high level of defects.
Plasma polymerized organosilicon films for use as O2 RIE resistant layers as described in U.S. Pat. No. 4,493,855 to Sachdev et al., are free from the problems of the other prior art previously mentioned. However, the solution coated barrier films of this invention provide an inexpensive alternative requiring no special tooling and are specially suited for high volume manufacturing. A further advantage of the barrier films of this invention is the superior adhesion to a variety of organic and inorganic contacting layers without requiring any special surface preparation.
U.S Pat. No. 4,430,153 to Gleason et al., discloses the in-situ conversion of an alkyl polyamide/polyimide surface layer to a silicon-containing alkyl polyamide/polyimide layer. This process, however, is unsuitable for practical applications requiring metal lift-off structures due to interference of the processing solvents with the mechanical integrity of the solvent removable lift-off layers. Also, this treatment does not provide an effective O2 RIE resistance necessary for pattern transfer into the underlayer.
It is highly desirable to have an O2 RIE barrier which can be used in a manufacturing environment for fabrication of the sub-micron line widths required for high density interconnective metallurgy patterns, and which overcomes all the problems with the prior art.
SUMMARY OF THE INVENTION
Therefore, it is the object of this invention to provide an improved method for fabricating semiconductor devices and packaging using lift-off technology.
It is also an object of this invention to provide a new and superior spun-on oxygen RIE barrier film as part of a lift-off mask employed for forming interconnective metallurgy systems for semiconductor components and packaging.
Another object of this invention is to provide a simple alternative to the Si3 N4, SiOx deposited by CVD or plasma-enhanced CVD processes, plasma polymerized organosilicons such as HMDS (hexamethyldisilazane) or hexamethyldisiloxane used as oxygen etch stops and dual dielectric in the fabrication of multi-level metal structures.
In accordance with these objects, the fabrication of multi-level metal structures is carried out according to the multi-layer resist process utilizing pre-formed silicon-containing polyimides as O2 /RIE barriers and etch stops. The silicon-containing polyimides, either spun-on or sprayed-on, have the requisite properties in terms of the thermal stability, glass transition temperature, mechanical properties, solvent resistance, compatibility of thermal coefficients of expansion with contacting films, and the necessary O2 etch resistance.
Thin films of silicon-containing polyimide formulations utilized in this invention are pinhole free, provide the desired overhang after RIE into the underlying lift-off layer, show no outgassing or fencing during metallization, and allow for clean lift-off in the usual solvent soak to provide excellent metal pattern. The barrier films according to this invention exhibit excellent O2 RIE resistance, adhesion to commonly employed lift-off layers, resist films, inter-level dielectric layers such as polyimide, and inorganic layers such as silicon oxide, silicon nitride, etc.
Due to the superior mechanical properties, thermal stability, excellent adhesion and low dielectric constant, the silicon-containing polyimides, as utilized in this invention, can remain as an integral part of the structure in packaging technology if desired.
BRIEF DESCRIPTION OF THE DRAWING
The foregoing and other advantages of the invention will be more fully understood with reference to the description of the preferred embodiment and with reference to the drawings wherein:
FIGS. 1A-F illustrate schematically the steps of a tri-layer resist process made possible by the present invention.
FIGS. 2A-E illustrate schematically the steps of a bi-layer resist process made possible by the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT Tri-layer Resist Process
Referring to FIG. 1A, a substrate 10, such as a siliccn wafer having semiconductor devices, is surface treated with a 0.1% aqueous solution of γ-aminopropyltriethoxysilane (γ-APS) by spin application at 2,000 RPM for 30 seconds, followed by a 5 minute bake at 85° C. (hot plate). The surface treatment enhances the adhesion between the substrate 10 and a subsequently applied underlayer 12. The lift-off underlayer is spin applied at 2,000 RPM for 30 seconds and baked at 85° C. for 10 minutes, 150° C. for 15 minutes, and 230° C. for 20 minutes, to form an approximately 2.1 micron thick coating. AZ1350J, commercially available from the Shipley Company has been used advantageously as the lift-off layer.
The lift-off layer is not critical so long as it can be etched with O2 plasma or RIE processing. This layer typically includes organic polymers such as AZ1350, AZ1350J (products of Shipley Co.), polysulfone resin (ICI Company), or soluble polyimides.
Following the application of layer 12, an oxygen RIE barrier 14 is applied. Silicon-containing polyimide #250-65 or #250-50, available commercially from the M&T Company, is diluted 1:2.5 with diglyme, filtered through a 0.45 micron silver filter, and spin-applied on the baked lift-off layer 12 at 3,000 RPM for 30 seconds. A bake sequence of 85° C. for 10 minutes, 150° C. for 15 minutes, and 230° C. for 20 minutes follows, resulting in an approximately 0.25-0.30 micron thick layer of the silicon polyimide.
Next, a layer of resist 16 is applied over the silicon-containing polyimide barrier layer 14. To enhance the adhesion of the resist 16 to the silicon-polyimide layer 14, the surface of silicon-polyimide layer 14 is pre-treated with HMDS-γAPE vapor in Freon-TF for 5 minutes or with a 0.1% solution of a γ-APS in toluene by spin coating. The layer of diazonaphthoquinone-novolak resist 16 is applied at 3,000 RPM for 30 seconds followed by a 30 minute bake at 85° C. to form a thick film approximately 0.9-1.1 microns thick.
The resist layer 16 can be a standard resist material known in the art, it may be positive or negative, and may be sensitive to near, mid or deep UV; electron beam; X-ray; ion beam; or laser. Examples are novolak based resists with diazoquinone type of photoactive component, acrylate polymers such as PMMA, polyolefin sulfones, etc. Patterning of the resist can be carried out according to standard lithographic processes.
After exposure to mid-UV light through mask 18, resist layer 16 is developed with AZ2401 (Shipley Co.) developer diluted 1:3.5 with deionized water (FIG. 1B). The image in the resist layer 16 is subsequently replicated into the silicon-containing polyimide layer 14 by RIE using a CF4 -O2 mixed gas system at a 2.5:1 flow rate ratio at 38-48 mtorr, with power level in the range 250-300 watts. Under these conditions, the barrier layer 14 can be etched at the rate of 1100-1300 Angstroms/min. The resulting structure is shown in FIG. 1C.
Subsequent image transfer down to the substrate 10 is accomplished by an O2 RIE at 40 mtorr and 300 watts with 50-95% overetch past end point. The resulting structure is seen in FIG. 1D. The overetch provides for the overhang 20 which facilitates the metal lift-off process.
Referring to FIG. 1E, the silicon-containing polyimide layer 14 and exposed areas of substrate 10 are sputter cleaned for 6 minutes at 220° C. prior to metallization. A blanket layer of metal 22, such as Al-Cu, is evaporated over the exposed surfaces at 120° to 150° C. Following this evaporation, the lift-off is accomplished by the standard solvent soak in NMP for 2 hours with brief ultrasonic agitation to accelerate removal of the lift-off stencil, leaving the metallurgy network 22 as shown in FIG. 1F. The metal film may be any metal conventionally employed, e.g., aluminum, copper alloy, palladium, platinum, chromium, etc.
In alternate embodiments, soluble polyimide XU284, manufactured by CIBA GEIGY, or other lift-off layers can be used in place of the baked AZ layer 12 without departing from the scope of this invention. The lift-off layer can be 1-5μm in thickness, the silicon polyimide layer is typically in the range 0.15-0.65μm and the imaging layer thickness is adjusted such that the desired level of image resolution and reduction of defect density is achieved. The imaging layer thickness is typically in the range 0.15-7.2μm. All other processing steps would follow as described above.
BI-LAYER RESIST PROCESS
Referring to FIG. 2A, a substrate 30, which can be a semiconductor wafer or packaging substrate, is provided. A lift-off layer 32, which can be a photoresist material or other polymer, is next applied on the substrate 30 as previously described.
A 10% solution of silicon-polyimide BE221 (available from M&T Company) in NMP is doped with a diazonaphthoquinone-based photoactive compound (PAC). The photoactive compound comprises approximately 18% of the solution. The mixture is filtered through a 0.2 micron silver filter and spin applied on lift-off layer 32. The resulting silicon-polyimide/PAC layer 34 is exposed to mid-UV exposure through mask 38 for approximately 20 seconds.
Following solvent development with AZ2401 diluted 1:6 with deionized water or with tetramethylammonium hydroxide and a hot plate bake up to 200° C., the developed pattern appears as in FIG. 2B. Reactive ion etching with O2 at 300 watts transfers the pattern into the lift-off layer 32 as seen in FIG. 2C.
As described in the tri-layer process above, metal 38 is blanket deposited on the layer 34 and exposed areas of substrate 30 (FIG. 2D), resulting in the metallurgy pattern after removal of the lift-off stencil as seen in FIG. 2E.
MATERIAL STRUCTURE AND PROPERTIES
The following silicon-containing polyimides are useful as O2 RIE barriers and/or O2 etch stops: ##STR1##
Desirable Material Properties
Thermal Stability: to 400° C. (minimum 250° C.)
Molecular Weight: 20,000 to 100,000 (preferred 30,000 to 50,000)
Dielectric Constant: 2.9-3.5
Glass Transition Temp: >100° C.
While the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that various changes in detail may be made therein without departing from the spirit, scope and teaching of the invention. For example, the base substrate may be silicon wafers, ceramic substrates, polyimide packaging layers, other polymeric films used in semiconductor processing, silicon wafers or ceramic substrates with one or more layers of insulating materials or dielectric layers, etc. Even a layer of silicon-containing polyimide could be present as a dielectric layer. Additionally, other structures of silicon-containing polyimides may be used other then those specifically disclosed. Accordingly, the process herein disclosed is to be considered merely as illustrative, and the invention is to be limited only as specified in the claims.

Claims (14)

We claim:
1. A method for depositing metal conductors on a substrate comprising the following steps:
providing a substrate;
depositing a lift-off polymer layer on the substrate;
depositing a layer of silicon-containing polyimide on the lift-off layer;
depositing a radiation sensitive layer on the silicon-containing polyimide layer;
imagewise exposing the radiation sensitive layer to radiation;
developing the imagewise exposed radiation sensitive layer;
etching the silicon-containing polyimide layer using the developed radiation sensitive layer as an etch mask;
etching the lift-off layer using the silicon-containing polyimide layer as an oxygen etch mask;
blanket depositing a layer of metal on the silicon-containing polyimide layer and exposed substrate;
removing the lift-off layer, the silicon-containing polyimide layer and overlying metal layer, leaving the metal conductors on the substrate.
2. The method as claimed in claim 1 which the lift-off layer is etched using O2.
3. A method for depositing metal conductors on a substrate comprising the following steps:
providing a substrate;
depositing a first layer of lift-off material on the substrate;
depositing a second layer of radiation-sensitized, silicon-containing polyimide on the first layer;
imagewise exposing the second layer to radiation;
developing the second layer;
etching the first layer with oxygen using the developed second layer as a mask;
blanket depositing a layer of metal on the second layer and exposed substrate;
removing the first and second layers and overlying metal layer, leaving the metal conductors of the substrate.
4. The method as claimed in claim 1 or 3 wherein the substrate is a semiconductor wafer.
5. The method as claimed in claim 1 or 3 wherein the substrate is a polymeric material.
6. The method as claimed in claim 1 or 3 wherein the substrate is ceramic.
7. The method as claimed in claim 1 or 3 wherein the lift-off material is selected from the group consistirg of photoresist, polysulfone and soluble polyimide.
8. The method as claimed in claim 1 or 3 wherein the substrate includes at least one layer selected from the group consisting of silicon oxide, silicon dioxide and silicon nitride.
9. The method as claimed in claim 1 or 3 wherein the silicon-containing polyimide layer is selected from the group consisting of: ##STR2##
10. The method as claimed in claim 1 or 3 wherein a silicon-containing polyimide dielectric layer is deposited on the substrate prior to the lift-off layer.
11. A multi-level metal structure comprising:
a substrate;
a first dielectric layer covering said substrate;
a silicon-containing polyimide dielectric layer covering said first dielectric layer; and
a pattern of metal conductors overlying the silicon-containing polyimide dielectric layer.
12. The structure as claimed in claim 11 wherein said substrate is a semiconductor wafer.
13. The structure as claimed in claim 11 wherein the substrate is ceramic.
14. The structure as claimed in claim 13 wherein the substrate has at least one metallic layer thereon.
US06/824,893 1986-01-31 1986-01-31 Silicon-containing polyimides as oxygen etch stop and dual dielectric coatings Expired - Fee Related US4692205A (en)

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Cited By (82)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4787957A (en) * 1987-09-25 1988-11-29 Air Products And Chemicals, Inc. Desmear and etchback using NF3 /O2 gas mixtures
US4851368A (en) * 1987-12-04 1989-07-25 Cornell Research Foundation, Inc. Method of making travelling wave semi-conductor laser
US4891303A (en) * 1988-05-26 1990-01-02 Texas Instruments Incorporated Trilayer microlithographic process using a silicon-based resist as the middle layer
US4897676A (en) * 1988-01-05 1990-01-30 Max Levy Autograph, Inc. High-density circuit and method of its manufacture
US4933132A (en) * 1989-02-28 1990-06-12 Hoechst Celanese Corp. Process of making a shaped article from intermediate molecular weight polyimides
US4968552A (en) * 1989-10-13 1990-11-06 International Business Machines Corp. Versatile reactive ion etch barriers from polyamic acid salts
EP0403817A2 (en) * 1989-06-13 1990-12-27 International Business Machines Corporation Dielectric structures with material resistant to etching and method of fabrication thereof
US5024896A (en) * 1989-07-06 1991-06-18 International Business Machines Corporation Collimated metal deposition
US5108542A (en) * 1990-08-23 1992-04-28 Hewlett Packard Company Selective etching method for tungsten and tungsten alloys
US5162191A (en) * 1988-01-05 1992-11-10 Max Levy Autograph, Inc. High-density circuit and method of its manufacture
US5258264A (en) * 1989-07-06 1993-11-02 International Business Machines Corporation Process of forming a dual overhang collimated lift-off stencil with subsequent metal deposition
US5371047A (en) * 1992-10-30 1994-12-06 International Business Machines Corporation Chip interconnection having a breathable etch stop layer
US5488394A (en) * 1988-01-05 1996-01-30 Max Levy Autograph, Inc. Print head and method of making same
US5533635A (en) * 1994-10-11 1996-07-09 Chartered Semiconductor Manufacturing Pte. Ltd. Method of wafer cleaning after metal etch
US5776805A (en) * 1995-12-29 1998-07-07 Lg Semicon Co., Ltd. Method for manufacturing MESFET
US5780363A (en) * 1997-04-04 1998-07-14 International Business Machines Coporation Etching composition and use thereof
US5804248A (en) * 1995-11-25 1998-09-08 International Business Machines Corporation Solder paste deposition
US5965465A (en) * 1997-09-18 1999-10-12 International Business Machines Corporation Etching of silicon nitride
US6033996A (en) * 1997-11-13 2000-03-07 International Business Machines Corporation Process for removing etching residues, etching mask and silicon nitride and/or silicon dioxide
US6087270A (en) * 1998-06-18 2000-07-11 Micron Technology, Inc. Method of patterning substrates
US6117796A (en) * 1998-08-13 2000-09-12 International Business Machines Corporation Removal of silicon oxide
US6150282A (en) * 1997-11-13 2000-11-21 International Business Machines Corporation Selective removal of etching residues
US6200891B1 (en) 1998-08-13 2001-03-13 International Business Machines Corporation Removal of dielectric oxides
US6270948B1 (en) 1996-08-22 2001-08-07 Kabushiki Kaisha Toshiba Method of forming pattern
US6423907B1 (en) 1998-02-09 2002-07-23 Tessera, Inc. Components with releasable leads
US20030228740A1 (en) * 2002-04-04 2003-12-11 Masaharu Nagai Method of fabricating semiconductor device, and developing apparatus using the method
US20040009673A1 (en) * 2002-07-11 2004-01-15 Sreenivasan Sidlgata V. Method and system for imprint lithography using an electric field
US20040091820A1 (en) * 2002-10-29 2004-05-13 Masaharu Nagai Method for removing resist pattern and method for manufacturing semiconductor device
US20040104641A1 (en) * 1999-10-29 2004-06-03 University Of Texas System Method of separating a template from a substrate during imprint lithography
US6746965B2 (en) * 2001-08-01 2004-06-08 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
US20040112153A1 (en) * 2002-12-12 2004-06-17 Molecular Imprints, Inc. Method and system for determining characteristics of substrates employing fluid geometries
US20040170771A1 (en) * 2000-10-12 2004-09-02 Board Of Regents, The University Of Texas System Method of creating a dispersion of a liquid on a substrate
US6797586B2 (en) * 2001-06-28 2004-09-28 Koninklijke Philips Electronics N.V. Silicon carbide schottky barrier diode and method of making
US20040189996A1 (en) * 2000-07-16 2004-09-30 Board Of Regents, The University Of Texas System Method of aligning a template with a substrate employing moire patterns
US6900881B2 (en) 2002-07-11 2005-05-31 Molecular Imprints, Inc. Step and repeat imprint lithography systems
US6916584B2 (en) 2002-08-01 2005-07-12 Molecular Imprints, Inc. Alignment methods for imprint lithography
US6926929B2 (en) 2002-07-09 2005-08-09 Molecular Imprints, Inc. System and method for dispensing liquids
US6929762B2 (en) 2002-11-13 2005-08-16 Molecular Imprints, Inc. Method of reducing pattern distortions during imprint lithography processes
US6932934B2 (en) 2002-07-11 2005-08-23 Molecular Imprints, Inc. Formation of discontinuous films during an imprint lithography process
US6954275B2 (en) 2000-08-01 2005-10-11 Boards Of Regents, The University Of Texas System Methods for high-precision gap and orientation sensing between a transparent template and substrate for imprint lithography
US6964793B2 (en) 2002-05-16 2005-11-15 Board Of Regents, The University Of Texas System Method for fabricating nanoscale patterns in light curable compositions using an electric field
US20050258522A1 (en) * 1998-09-28 2005-11-24 Ibiden Co., Ltd. Printed wiring board and method for producing the same
US20050260848A1 (en) * 2004-05-21 2005-11-24 Molecular Imprints, Inc. Method of forming a recessed structure employing a reverse tone process
US6980282B2 (en) 2002-12-11 2005-12-27 Molecular Imprints, Inc. Method for modulating shapes of substrates
US20060009038A1 (en) * 2004-07-12 2006-01-12 International Business Machines Corporation Processing for overcoming extreme topography
US20060063277A1 (en) * 2004-09-21 2006-03-23 Molecular Imprints, Inc. Method of forming an in-situ recessed structure
US20060063387A1 (en) * 2004-09-21 2006-03-23 Molecular Imprints, Inc. Method of Patterning Surfaces While Providing Greater Control of Recess Anisotropy
US20060060557A1 (en) * 2004-09-21 2006-03-23 Sreenivasan Sidlgata V Reverse tone patterning on surfaces having surface planarity perturbations
US7019819B2 (en) 2002-11-13 2006-03-28 Molecular Imprints, Inc. Chucking system for modulating shapes of substrates
US7027156B2 (en) 2002-08-01 2006-04-11 Molecular Imprints, Inc. Scatterometry alignment for imprint lithography
US7037639B2 (en) 2002-05-01 2006-05-02 Molecular Imprints, Inc. Methods of manufacturing a lithography template
US20060113697A1 (en) * 2004-12-01 2006-06-01 Molecular Imprints, Inc. Eliminating printability of sub-resolution defects in imprint lithography
US7071088B2 (en) 2002-08-23 2006-07-04 Molecular Imprints, Inc. Method for fabricating bulbous-shaped vias
US7070405B2 (en) 2002-08-01 2006-07-04 Molecular Imprints, Inc. Alignment systems for imprint lithography
US7077992B2 (en) 2002-07-11 2006-07-18 Molecular Imprints, Inc. Step and repeat imprint lithography processes
US7090716B2 (en) 2003-10-02 2006-08-15 Molecular Imprints, Inc. Single phase fluid imprint lithography method
US7122079B2 (en) 2004-02-27 2006-10-17 Molecular Imprints, Inc. Composition for an etching mask comprising a silicon-containing material
US20060231930A1 (en) * 2005-04-19 2006-10-19 Hitachi Global Storage Technologies Netherlands B.V. Heat resistant photomask for high temperature fabrication processes
US7136150B2 (en) 2003-09-25 2006-11-14 Molecular Imprints, Inc. Imprint lithography template having opaque alignment marks
US20060292868A1 (en) * 2002-12-16 2006-12-28 Fuji Xerox Co., Ltd. Surface emitting semiconductor laser
US7157036B2 (en) 2003-06-17 2007-01-02 Molecular Imprints, Inc Method to reduce adhesion between a conformable region and a pattern of a mold
US20070017899A1 (en) * 2005-07-19 2007-01-25 Molecular Imprints, Inc. Method of controlling the critical dimension of structures formed on a substrate
US7179396B2 (en) 2003-03-25 2007-02-20 Molecular Imprints, Inc. Positive tone bi-layer imprint lithography method
US20070077770A1 (en) * 2005-09-30 2007-04-05 Molecular Imprints, Inc. Etching technique to planarize a multi-layer structure
US7205244B2 (en) 2004-09-21 2007-04-17 Molecular Imprints Patterning substrates employing multi-film layers defining etch-differential interfaces
US20080118872A1 (en) * 2003-03-25 2008-05-22 Molecular Imprints, Inc. Positive Tone Bi-Layer Method
US7396475B2 (en) 2003-04-25 2008-07-08 Molecular Imprints, Inc. Method of forming stepped structures employing imprint lithography
US7452574B2 (en) 2003-02-27 2008-11-18 Molecular Imprints, Inc. Method to reduce adhesion between a polymerizable layer and a substrate employing a fluorine-containing layer
US20090045827A1 (en) * 2007-08-17 2009-02-19 Andrew Gangoso Multi-Site Probe
US20090130608A1 (en) * 2007-11-20 2009-05-21 Irving Lyn M Photopatternable deposition inhibitor containing siloxane
US7547504B2 (en) 2004-09-21 2009-06-16 Molecular Imprints, Inc. Pattern reversal employing thick residual layers
US7906180B2 (en) 2004-02-27 2011-03-15 Molecular Imprints, Inc. Composition for an etching mask comprising a silicon-containing material
US8076386B2 (en) 2004-02-23 2011-12-13 Molecular Imprints, Inc. Materials for imprint lithography
US8124525B1 (en) 2010-10-27 2012-02-28 International Business Machines Corporation Method of forming self-aligned local interconnect and structure formed thereby
US8211214B2 (en) 2003-10-02 2012-07-03 Molecular Imprints, Inc. Single phase fluid imprint lithography method
US8349241B2 (en) 2002-10-04 2013-01-08 Molecular Imprints, Inc. Method to arrange features on a substrate to replicate features having minimal dimensional variability
CN103155100A (en) * 2010-08-06 2013-06-12 布鲁尔科技公司 Multiple bonding layers for thin-wafer handling
US8466000B2 (en) 2011-04-14 2013-06-18 United Microelectronics Corp. Backside-illuminated image sensor and fabricating method thereof
US9223202B2 (en) 2000-07-17 2015-12-29 Board Of Regents, The University Of Texas System Method of automatic fluid dispensing for imprint lithography processes
US9461270B2 (en) * 2013-11-25 2016-10-04 Lg Display Co., Ltd. Method for manufacturing organic light emitting diode display device
US10546821B2 (en) * 2013-12-31 2020-01-28 Texas Instruments Incorporated Opening in a multilayer polymeric dielectric layer without delamination
WO2024045270A1 (en) * 2022-09-01 2024-03-07 中国科学院微电子研究所 Laminated structure and preparation method therefor, pattern transfer method, and reworking method

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR910006446B1 (en) * 1988-09-16 1991-08-24 삼성전자 주식회사 A method manufacturing the capacitor of semiconductor device
DE69021022T2 (en) * 1989-12-07 1996-01-18 Toshiba Kawasaki Kk Photosensitive composition and resin-coated semiconductor device.
US5100503A (en) * 1990-09-14 1992-03-31 Ncr Corporation Silica-based anti-reflective planarizing layer
JPH0697128A (en) * 1992-07-31 1994-04-08 Internatl Business Mach Corp <Ibm> Pattern formation method of polyimide in manufacture of multilayer metal structure
DE10025550A1 (en) * 2000-05-19 2001-11-29 Infineon Technologies Ag Plasma etching process used in the production of Fe-RAMs comprises applying a polyimide mask before the structure is etched
US20040070048A1 (en) * 2002-10-15 2004-04-15 Kwok Siang Ping Providing high precision resistance in an integrated circuit using a thin film resistor of controlled dimension
WO2007148160A2 (en) * 2006-06-20 2007-12-27 Freescale Semiconductor, Inc. Method of multi-layer lithography
JP6548024B2 (en) * 2015-09-24 2019-07-24 国立研究開発法人情報通信研究機構 Method of manufacturing substrate including uneven structure and method of manufacturing semiconductor light emitting device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4430153A (en) * 1983-06-30 1984-02-07 International Business Machines Corporation Method of forming an RIE etch barrier by in situ conversion of a silicon containing alkyl polyamide/polyimide
US4493855A (en) * 1982-12-23 1985-01-15 International Business Machines Corporation Use of plasma polymerized organosilicon films in fabrication of lift-off masks

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4140572A (en) * 1976-09-07 1979-02-20 General Electric Company Process for selective etching of polymeric materials embodying silicones therein
EP0133533B1 (en) * 1983-08-01 1993-04-21 Hitachi, Ltd. Low thermal expansion resin material for a wiring insulating film.
JPH0727217B2 (en) * 1985-09-30 1995-03-29 松下電子工業株式会社 Method of forming resist pattern on substrate
JPH0727966B2 (en) * 1986-07-04 1995-03-29 日立化成工業株式会社 Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4493855A (en) * 1982-12-23 1985-01-15 International Business Machines Corporation Use of plasma polymerized organosilicon films in fabrication of lift-off masks
US4430153A (en) * 1983-06-30 1984-02-07 International Business Machines Corporation Method of forming an RIE etch barrier by in situ conversion of a silicon containing alkyl polyamide/polyimide

Cited By (149)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4787957A (en) * 1987-09-25 1988-11-29 Air Products And Chemicals, Inc. Desmear and etchback using NF3 /O2 gas mixtures
US4851368A (en) * 1987-12-04 1989-07-25 Cornell Research Foundation, Inc. Method of making travelling wave semi-conductor laser
US5317342A (en) * 1988-01-05 1994-05-31 Max Levy Autograph, Inc. High-density print head
US4897676A (en) * 1988-01-05 1990-01-30 Max Levy Autograph, Inc. High-density circuit and method of its manufacture
US5162191A (en) * 1988-01-05 1992-11-10 Max Levy Autograph, Inc. High-density circuit and method of its manufacture
US5416502A (en) * 1988-01-05 1995-05-16 Max Levy Autograph, Inc. High-density circuit and method of its manufacture
US5488394A (en) * 1988-01-05 1996-01-30 Max Levy Autograph, Inc. Print head and method of making same
US5624708A (en) * 1988-01-05 1997-04-29 Max Levy Autograph, Inc. High-density circuit and method of its manufacture
US4891303A (en) * 1988-05-26 1990-01-02 Texas Instruments Incorporated Trilayer microlithographic process using a silicon-based resist as the middle layer
US4933132A (en) * 1989-02-28 1990-06-12 Hoechst Celanese Corp. Process of making a shaped article from intermediate molecular weight polyimides
EP0403817A3 (en) * 1989-06-13 1991-12-18 International Business Machines Corporation Dielectric structures with material resistant to etching and method of fabrication thereof
EP0403817A2 (en) * 1989-06-13 1990-12-27 International Business Machines Corporation Dielectric structures with material resistant to etching and method of fabrication thereof
US5258264A (en) * 1989-07-06 1993-11-02 International Business Machines Corporation Process of forming a dual overhang collimated lift-off stencil with subsequent metal deposition
US5024896A (en) * 1989-07-06 1991-06-18 International Business Machines Corporation Collimated metal deposition
US4968552A (en) * 1989-10-13 1990-11-06 International Business Machines Corp. Versatile reactive ion etch barriers from polyamic acid salts
US5108542A (en) * 1990-08-23 1992-04-28 Hewlett Packard Company Selective etching method for tungsten and tungsten alloys
US5371047A (en) * 1992-10-30 1994-12-06 International Business Machines Corporation Chip interconnection having a breathable etch stop layer
US5533635A (en) * 1994-10-11 1996-07-09 Chartered Semiconductor Manufacturing Pte. Ltd. Method of wafer cleaning after metal etch
US5804248A (en) * 1995-11-25 1998-09-08 International Business Machines Corporation Solder paste deposition
US6096131A (en) * 1995-11-25 2000-08-01 International Business Machines Corporation Solder paste deposition
US5776805A (en) * 1995-12-29 1998-07-07 Lg Semicon Co., Ltd. Method for manufacturing MESFET
US6270948B1 (en) 1996-08-22 2001-08-07 Kabushiki Kaisha Toshiba Method of forming pattern
US5780363A (en) * 1997-04-04 1998-07-14 International Business Machines Coporation Etching composition and use thereof
US5965465A (en) * 1997-09-18 1999-10-12 International Business Machines Corporation Etching of silicon nitride
US6066267A (en) * 1997-09-18 2000-05-23 International Business Machines Corporation Etching of silicon nitride
US6033996A (en) * 1997-11-13 2000-03-07 International Business Machines Corporation Process for removing etching residues, etching mask and silicon nitride and/or silicon dioxide
US6150282A (en) * 1997-11-13 2000-11-21 International Business Machines Corporation Selective removal of etching residues
US20040217003A1 (en) * 1998-02-09 2004-11-04 Tessera, Inc. Method of making components with releasable leads
US6763579B2 (en) 1998-02-09 2004-07-20 Tessera, Inc. Method of making components with releasable leads
US6423907B1 (en) 1998-02-09 2002-07-23 Tessera, Inc. Components with releasable leads
US20020117329A1 (en) * 1998-02-09 2002-08-29 Belgacem Haba Components with releasable leads
US6557253B1 (en) 1998-02-09 2003-05-06 Tessera, Inc. Method of making components with releasable leads
US7114250B2 (en) 1998-02-09 2006-10-03 Tessera, Inc. Method of making components with releasable leads
US6664484B2 (en) 1998-02-09 2003-12-16 Tessera, Inc. Components with releasable leads
US6087270A (en) * 1998-06-18 2000-07-11 Micron Technology, Inc. Method of patterning substrates
US6117796A (en) * 1998-08-13 2000-09-12 International Business Machines Corporation Removal of silicon oxide
US6200891B1 (en) 1998-08-13 2001-03-13 International Business Machines Corporation Removal of dielectric oxides
US20050258522A1 (en) * 1998-09-28 2005-11-24 Ibiden Co., Ltd. Printed wiring board and method for producing the same
US20080292852A1 (en) * 1998-09-28 2008-11-27 Ibiden Co., Ltd Printed wiring board and method for producing the same
US20090090003A1 (en) * 1998-09-28 2009-04-09 Ibiden Co., Ltd Printed wiring board and method for producing the same
US20080289864A1 (en) * 1998-09-28 2008-11-27 Ibiden Co., Ltd Printed wiring board and method for producing the same
US20090205857A1 (en) * 1998-09-28 2009-08-20 Ibiden Co., Ltd Printed wiring board and method for producing the same
US20080289176A1 (en) * 1998-09-28 2008-11-27 Ibiden Co., Ltd Printed wiring board and method for producing the same
US7504719B2 (en) 1998-09-28 2009-03-17 Ibiden Co., Ltd. Printed wiring board having a roughened surface formed on a metal layer, and method for producing the same
US8020291B2 (en) 1998-09-28 2011-09-20 Ibiden Co., Ltd. Method of manufacturing a printed wiring board
US8533943B2 (en) * 1998-09-28 2013-09-17 Ibiden Co., Ltd. Printed wiring board and method for producing the same
US8030577B2 (en) 1998-09-28 2011-10-04 Ibiden Co., Ltd. Printed wiring board and method for producing the same
US8093507B2 (en) 1998-09-28 2012-01-10 Ibiden Co., Ltd. Printed wiring board and method for producing the same
US7535095B1 (en) * 1998-09-28 2009-05-19 Ibiden Co., Ltd. Printed wiring board and method for producing the same
US8018045B2 (en) 1998-09-28 2011-09-13 Ibiden Co., Ltd. Printed circuit board
US20090183904A1 (en) * 1998-09-28 2009-07-23 Ibiden Co., Ltd. Printed wiring board and method for producing the same
US8006377B2 (en) 1998-09-28 2011-08-30 Ibiden Co., Ltd. Method for producing a printed wiring board
US20090188708A1 (en) * 1998-09-28 2009-07-30 Ibiden Co., Ltd Printed wiring board and method for producing the same
US7994433B2 (en) 1998-09-28 2011-08-09 Ibiden Co., Ltd. Printed wiring board and method for producing the same
US20040104641A1 (en) * 1999-10-29 2004-06-03 University Of Texas System Method of separating a template from a substrate during imprint lithography
US6955868B2 (en) 1999-10-29 2005-10-18 Board Of Regents, The University Of Texas System Method to control the relative position between a body and a surface
US7060402B2 (en) 1999-10-29 2006-06-13 Board Of Regents, The University Of Texas System Method of orientating a template with respect to a substrate in response to a force exerted on the template
US7098572B2 (en) 1999-10-29 2006-08-29 Board Of Regents, The University Of Texas System Apparatus to control displacement of a body spaced-apart from a surface
US20040168588A1 (en) * 1999-10-29 2004-09-02 Board Of Regents, The University Of Texas System Method of orientating a template with respect to a substrate in response to a force exerted on the template
US20050089774A1 (en) * 1999-10-29 2005-04-28 Board Of Regents, The University Of Texas System Method to control the relative position between a body and a surface
US20040209177A1 (en) * 2000-07-16 2004-10-21 Board Of Regents, The University Of Texas System Dual wavelength method of determining a relative position of a substrate and a template
US6842229B2 (en) 2000-07-16 2005-01-11 Board Of Regents, The University Of Texas System Imprint lithography template comprising alignment marks
US6916585B2 (en) 2000-07-16 2005-07-12 Board Of Regents, The University Of Texas Systems Method of varying template dimensions to achieve alignment during imprint lithography
US20040189996A1 (en) * 2000-07-16 2004-09-30 Board Of Regents, The University Of Texas System Method of aligning a template with a substrate employing moire patterns
US6902853B2 (en) 2000-07-16 2005-06-07 Board Of Regents, The University Of Texas System Dual wavelength method of determining a relative position of a substrate and a template
US6986975B2 (en) 2000-07-16 2006-01-17 Board Of Regents, The University Of Texas System Method of aligning a template with a substrate employing moire patterns
US6921615B2 (en) 2000-07-16 2005-07-26 Board Of Regents, The University Of Texas System High-resolution overlay alignment methods for imprint lithography
US6919152B2 (en) 2000-07-16 2005-07-19 Board Of Regents, The University Of Texas System High resolution overlay alignment systems for imprint lithography
US9223202B2 (en) 2000-07-17 2015-12-29 Board Of Regents, The University Of Texas System Method of automatic fluid dispensing for imprint lithography processes
US6954275B2 (en) 2000-08-01 2005-10-11 Boards Of Regents, The University Of Texas System Methods for high-precision gap and orientation sensing between a transparent template and substrate for imprint lithography
US20040170771A1 (en) * 2000-10-12 2004-09-02 Board Of Regents, The University Of Texas System Method of creating a dispersion of a liquid on a substrate
US7060324B2 (en) 2000-10-12 2006-06-13 Board Of Regents, The University Of Texas System Method of creating a dispersion of a liquid on a substrate
US6797586B2 (en) * 2001-06-28 2004-09-28 Koninklijke Philips Electronics N.V. Silicon carbide schottky barrier diode and method of making
US6746965B2 (en) * 2001-08-01 2004-06-08 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
US7119022B2 (en) 2001-08-01 2006-10-10 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
US20040224514A1 (en) * 2001-08-01 2004-11-11 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
US20070155182A1 (en) * 2001-08-01 2007-07-05 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
US8420546B2 (en) 2001-08-01 2013-04-16 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
US20030228740A1 (en) * 2002-04-04 2003-12-11 Masaharu Nagai Method of fabricating semiconductor device, and developing apparatus using the method
US7344825B2 (en) 2002-04-04 2008-03-18 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating semiconductor device, and developing apparatus using the method
US7799515B2 (en) 2002-04-04 2010-09-21 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating semiconductor device, and developing apparatus using the method
US7037639B2 (en) 2002-05-01 2006-05-02 Molecular Imprints, Inc. Methods of manufacturing a lithography template
US6964793B2 (en) 2002-05-16 2005-11-15 Board Of Regents, The University Of Texas System Method for fabricating nanoscale patterns in light curable compositions using an electric field
US6926929B2 (en) 2002-07-09 2005-08-09 Molecular Imprints, Inc. System and method for dispensing liquids
US6932934B2 (en) 2002-07-11 2005-08-23 Molecular Imprints, Inc. Formation of discontinuous films during an imprint lithography process
US6908861B2 (en) 2002-07-11 2005-06-21 Molecular Imprints, Inc. Method for imprint lithography using an electric field
US6900881B2 (en) 2002-07-11 2005-05-31 Molecular Imprints, Inc. Step and repeat imprint lithography systems
US7077992B2 (en) 2002-07-11 2006-07-18 Molecular Imprints, Inc. Step and repeat imprint lithography processes
US20040009673A1 (en) * 2002-07-11 2004-01-15 Sreenivasan Sidlgata V. Method and system for imprint lithography using an electric field
US6916584B2 (en) 2002-08-01 2005-07-12 Molecular Imprints, Inc. Alignment methods for imprint lithography
US7070405B2 (en) 2002-08-01 2006-07-04 Molecular Imprints, Inc. Alignment systems for imprint lithography
US7027156B2 (en) 2002-08-01 2006-04-11 Molecular Imprints, Inc. Scatterometry alignment for imprint lithography
US7071088B2 (en) 2002-08-23 2006-07-04 Molecular Imprints, Inc. Method for fabricating bulbous-shaped vias
US8349241B2 (en) 2002-10-04 2013-01-08 Molecular Imprints, Inc. Method to arrange features on a substrate to replicate features having minimal dimensional variability
US20040091820A1 (en) * 2002-10-29 2004-05-13 Masaharu Nagai Method for removing resist pattern and method for manufacturing semiconductor device
US7875419B2 (en) 2002-10-29 2011-01-25 Semiconductor Energy Laboratory Co., Ltd. Method for removing resist pattern and method for manufacturing semiconductor device
US7019819B2 (en) 2002-11-13 2006-03-28 Molecular Imprints, Inc. Chucking system for modulating shapes of substrates
US6929762B2 (en) 2002-11-13 2005-08-16 Molecular Imprints, Inc. Method of reducing pattern distortions during imprint lithography processes
US6980282B2 (en) 2002-12-11 2005-12-27 Molecular Imprints, Inc. Method for modulating shapes of substrates
US6871558B2 (en) 2002-12-12 2005-03-29 Molecular Imprints, Inc. Method for determining characteristics of substrate employing fluid geometries
US20040112153A1 (en) * 2002-12-12 2004-06-17 Molecular Imprints, Inc. Method and system for determining characteristics of substrates employing fluid geometries
US20060292868A1 (en) * 2002-12-16 2006-12-28 Fuji Xerox Co., Ltd. Surface emitting semiconductor laser
US7452574B2 (en) 2003-02-27 2008-11-18 Molecular Imprints, Inc. Method to reduce adhesion between a polymerizable layer and a substrate employing a fluorine-containing layer
US7179396B2 (en) 2003-03-25 2007-02-20 Molecular Imprints, Inc. Positive tone bi-layer imprint lithography method
US7670953B2 (en) 2003-03-25 2010-03-02 Molecular Imprints, Inc. Positive tone bi-layer method
US20080118872A1 (en) * 2003-03-25 2008-05-22 Molecular Imprints, Inc. Positive Tone Bi-Layer Method
US7396475B2 (en) 2003-04-25 2008-07-08 Molecular Imprints, Inc. Method of forming stepped structures employing imprint lithography
US7157036B2 (en) 2003-06-17 2007-01-02 Molecular Imprints, Inc Method to reduce adhesion between a conformable region and a pattern of a mold
US7136150B2 (en) 2003-09-25 2006-11-14 Molecular Imprints, Inc. Imprint lithography template having opaque alignment marks
US8211214B2 (en) 2003-10-02 2012-07-03 Molecular Imprints, Inc. Single phase fluid imprint lithography method
US7090716B2 (en) 2003-10-02 2006-08-15 Molecular Imprints, Inc. Single phase fluid imprint lithography method
US8076386B2 (en) 2004-02-23 2011-12-13 Molecular Imprints, Inc. Materials for imprint lithography
US7906180B2 (en) 2004-02-27 2011-03-15 Molecular Imprints, Inc. Composition for an etching mask comprising a silicon-containing material
US7122079B2 (en) 2004-02-27 2006-10-17 Molecular Imprints, Inc. Composition for an etching mask comprising a silicon-containing material
US7186656B2 (en) 2004-05-21 2007-03-06 Molecular Imprints, Inc. Method of forming a recessed structure employing a reverse tone process
US20050260848A1 (en) * 2004-05-21 2005-11-24 Molecular Imprints, Inc. Method of forming a recessed structure employing a reverse tone process
US20060009038A1 (en) * 2004-07-12 2006-01-12 International Business Machines Corporation Processing for overcoming extreme topography
US9263292B2 (en) 2004-07-12 2016-02-16 Globalfoundries Inc. Processing for overcoming extreme topography
US8603846B2 (en) 2004-07-12 2013-12-10 International Business Machines Corporation Processing for overcoming extreme topography
US20060060557A1 (en) * 2004-09-21 2006-03-23 Sreenivasan Sidlgata V Reverse tone patterning on surfaces having surface planarity perturbations
US7041604B2 (en) 2004-09-21 2006-05-09 Molecular Imprints, Inc. Method of patterning surfaces while providing greater control of recess anisotropy
US7547504B2 (en) 2004-09-21 2009-06-16 Molecular Imprints, Inc. Pattern reversal employing thick residual layers
US20060063277A1 (en) * 2004-09-21 2006-03-23 Molecular Imprints, Inc. Method of forming an in-situ recessed structure
US20060063387A1 (en) * 2004-09-21 2006-03-23 Molecular Imprints, Inc. Method of Patterning Surfaces While Providing Greater Control of Recess Anisotropy
US7252777B2 (en) 2004-09-21 2007-08-07 Molecular Imprints, Inc. Method of forming an in-situ recessed structure
US7241395B2 (en) 2004-09-21 2007-07-10 Molecular Imprints, Inc. Reverse tone patterning on surfaces having planarity perturbations
US7205244B2 (en) 2004-09-21 2007-04-17 Molecular Imprints Patterning substrates employing multi-film layers defining etch-differential interfaces
US7357876B2 (en) 2004-12-01 2008-04-15 Molecular Imprints, Inc. Eliminating printability of sub-resolution defects in imprint lithography
US20060113697A1 (en) * 2004-12-01 2006-06-01 Molecular Imprints, Inc. Eliminating printability of sub-resolution defects in imprint lithography
US20060231930A1 (en) * 2005-04-19 2006-10-19 Hitachi Global Storage Technologies Netherlands B.V. Heat resistant photomask for high temperature fabrication processes
US20070017899A1 (en) * 2005-07-19 2007-01-25 Molecular Imprints, Inc. Method of controlling the critical dimension of structures formed on a substrate
US7256131B2 (en) 2005-07-19 2007-08-14 Molecular Imprints, Inc. Method of controlling the critical dimension of structures formed on a substrate
US20070077770A1 (en) * 2005-09-30 2007-04-05 Molecular Imprints, Inc. Etching technique to planarize a multi-layer structure
US7259102B2 (en) 2005-09-30 2007-08-21 Molecular Imprints, Inc. Etching technique to planarize a multi-layer structure
US7847568B2 (en) * 2007-08-17 2010-12-07 Advanced Micro Devices, Inc. Multi-site probe
US20090045827A1 (en) * 2007-08-17 2009-02-19 Andrew Gangoso Multi-Site Probe
US7846644B2 (en) 2007-11-20 2010-12-07 Eastman Kodak Company Photopatternable deposition inhibitor containing siloxane
US20090130608A1 (en) * 2007-11-20 2009-05-21 Irving Lyn M Photopatternable deposition inhibitor containing siloxane
US20140174627A1 (en) * 2010-08-06 2014-06-26 Brewer Science Inc. Multiple bonding layers for thin-wafer handling
US9224631B2 (en) * 2010-08-06 2015-12-29 Brewer Science Inc. Multiple bonding layers for thin-wafer handling
CN103155100A (en) * 2010-08-06 2013-06-12 布鲁尔科技公司 Multiple bonding layers for thin-wafer handling
US9263314B2 (en) 2010-08-06 2016-02-16 Brewer Science Inc. Multiple bonding layers for thin-wafer handling
CN103155100B (en) * 2010-08-06 2016-08-03 布鲁尔科技公司 Many adhesive layers that LED reverse mounting type processes
US9472436B2 (en) 2010-08-06 2016-10-18 Brewer Science Inc. Multiple bonding layers for thin-wafer handling
US8124525B1 (en) 2010-10-27 2012-02-28 International Business Machines Corporation Method of forming self-aligned local interconnect and structure formed thereby
US8466000B2 (en) 2011-04-14 2013-06-18 United Microelectronics Corp. Backside-illuminated image sensor and fabricating method thereof
US9461270B2 (en) * 2013-11-25 2016-10-04 Lg Display Co., Ltd. Method for manufacturing organic light emitting diode display device
US10546821B2 (en) * 2013-12-31 2020-01-28 Texas Instruments Incorporated Opening in a multilayer polymeric dielectric layer without delamination
WO2024045270A1 (en) * 2022-09-01 2024-03-07 中国科学院微电子研究所 Laminated structure and preparation method therefor, pattern transfer method, and reworking method

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EP0230615A2 (en) 1987-08-05
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