This application is a divisional of application Ser. No. 180,697 filed Apr. 8, 1988, which is a continuation of Ser. No. 928,559, filed Nov. 10, 1986 both are abandoned.

BACKGROUND OF THE INVENTION

The present invention relates to a multichip package.

Conventionally, in manufacturing multichip packages, a wire bonding method or a TAB (Tape Automatic Bonding) method is utilized to mount and connect ICs on a ceramic substrate on which a polyimide insulating film is formed (COPPER/POLYIMIDE MATERIALS SYSTEM FOR HIGH PERFORMANCE PACKAGING, 0569-5503/84/0000-0073 1984 IEEE). Also, a soldering method is utilized (The Thin-Film Module as a High-Performance Semiconductor Package, IBM J. RES. DEVELOP. VOL. 26, NO. 3 May 1982).

In the above conventional wire bonding or TAB connection method, since lead terminals extend outwardly from the outer sides of an IC or LSI chip, packaging efficiency is degraded. In addition, since thermal bonding or ultrasonic welding is utilized, the polyimide insulating film on the surface of the ceramic substrate is deformed or damaged, degrading the reliability. Furthermore, with the soldering connection method, the size of the connection pad or connection bump cannot be suppressed to about 50 μm, and high-density packaging cannot thus be performed.

SUMMARY OF THE INVENTION

A multichip package according to the present invention comprises a ceramic multilayer substrate having a multilayer circuit wiring therein, input/output pins connected to a lower surface of the multilayer substrate, a first polyimide insulating layer formed on an upper surface of the multilayer substrate, a first vertical wiring formed on an uppermost layer of the first polyimide insulating layer, and a plurality of semiconductor elements each having a second polyimide insulating layer and a second vertical wiring which are connected to the first polyimide insulating layer and the first vertical wiring, respectively.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic sectional view showing a first embodiment of the present invention;

FIG. 2 is a schematic sectional view showing a second embodiment of the present invention; and

FIG. 3 is a schematic sectional view showing a third embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention will be described with reference to the accompanying drawings.

FIG. 1 shows a multichip package according to an embodiment of the present invention. Referring to FIG. 1, a ceramic multilayer substrate 1 is a multilayer circuit substrate comprising an alumina ceramic including a tungsten (W) or molybdenum (Mo) power source wiring pattern 2 and a gold (Au) or silver-palladium (Ag/Pd) signal wiring pattern 3. Input/output pins 4 of a koval material or the like are connected to the lower surface of the multilayer substrate 1 by a silver-copper eutectic alloy. A polyimide insulating layer 5 is formed on the upper surface of the multilayer substrate 1. A plurality of vertical wirings 6 connected to the power source and signal patterns 2 and 3 are formed in the polyimide insulating layer 5 such that the surfaces thereof are planar with an upper surface of the polyimide insulating layer 5.

A polyimide insulating layer 9 is formed on the lower surface of each of a plurality of integrated circuit chips 7. Vertical wirings 8 are formed in the polyimide insulating layer 9 such that the lower surfaces thereof are planar with the lower surface of the polyimide insulating layer 9. The upper surface of the polyimide insulating layer 5 is directly bonded to the lower surface of the polyimide insulating layer 9, and the upper surfaces of the vertical wirings 6 are directly bonded to the respective lower surfaces of the vertical wirings 8. Each vertical wiring 8 formed on the lower surface of each integrated circuit chip 7 is made of gold (Au) and is a square with a side of 20 to 30 μm. The polyimide insulating layer 9 is a polyimide resin at an intermediate stage (anti-cure state) of dehydration cyclopolymerization before it is bonded. Similarly, each wiring 6 at the ceramic multilayer substrate 1 side is made of gold (Au) and is square with a side of 20 to 30 μm. The uppermost layer of the polyimide insulating layer 5 is in an anti-cure state before it is bonded. The polyimide insulating layers 9 and the vertical wirings 8 at the integrated circuit chip 7 side are caused to oppose the polyimide insulating layer 5 and the vertical wirings 6 at the ceramic multilayer circuit substrate 1 side, respectively, and are bonded with each other in an N.sub.2 atmosphere at a pressure of about 2 kg/mm.sup.2 and a temperature of about 400 polyimide insulating layers 5 and 9 are completely cured and bonded with each other, and the vertical wirings 6 and 8 are subjected to gold (Au)-gold (Au) thermal bonding and adhered to each other. In this case, unlike in the wire bonding or TAB method, since no pressure is locally applied and the polyimide insulating layers 9 on the surfaces of the integrated circuit chips 7 are abutted against the polyimide insulating layer 5 of the ceramic multilayer substrate 1, no deformation or breakdown occurs in the insulating layers 5 and 9.

FIG. 2 shows another embodiment of the present invention. Referring to FIG. 2, a ceramic multilayer substrate 11 incorporates a power source wiring pattern 12 and a signal wiring pattern 13, and input/output pins 14 and a polyimide insulating layer 15 are formed on the upper and lower surface of the ceramic multilayer substrate 11, respectively, in a similar manner so that in the embodiment shown in FIG. 1. The insulating layer 15 is a multilayer and wiring patterns 10 are formed to extend between the respective layer of the insulating layer 15. The wiring patterns 10 of the respective layers of the insulating layer 15 are connected with each other through via holes formed in the respective layers of the insulating layer 15 as needed. The uppermost wiring pattern 10 is connected to an integrated circuit chip 17 through vertical wirings 16 and 18 in a similar manner to that in FIG. 1.

FIG. 3 shows still another embodiment of the present invention wherein a chip carrier 33 is mounted on a structure similar to that of FIG. 2, instead of an integrated circuit chip 17. Each of a plurality of chip carriers 33 incorporates an IC chip 31 and leads 32. The leads 32 connect the IC chip 31 with vertical wirings 28 provided in a polyimide insulating layer 29 in a similar manner to the vertical wirings 18 of FIG. 2. The chip carriers 33 are bonded on the upper surface of an insulating layer 29 in a similar bonding mechanism to in the case of integrated circuit chips. In this case, if an IC chip 31 of any chip carrier 33 is to be replaced or tested, the chip carrier 33 can be easily removed. Therefore, the ceramic multilayer substrate portion having a wiring pattern and the chip carrier 33 can be tested independently.

As described above, according to the present invention, a polyimide insulating layer and a vertical wiring on a ceramic multilayer substrate having a multilayer circuit wiring are directly bonded to a polyimide insulating layer and a vertical wiring on an integrated circuit chip or chip carrier to oppose each other. As a result, since connection can be made with a small size of about 50 μm or less, packaging density can be increased and a highly reliable multichip package can be obtained.