US4954456A - Fabrication method for high speed and high packing density semiconductor device (BiCMOS) - Google Patents
Fabrication method for high speed and high packing density semiconductor device (BiCMOS) Download PDFInfo
- Publication number
- US4954456A US4954456A US07/224,020 US22402088A US4954456A US 4954456 A US4954456 A US 4954456A US 22402088 A US22402088 A US 22402088A US 4954456 A US4954456 A US 4954456A
- Authority
- US
- United States
- Prior art keywords
- oxide film
- polysilicon
- order
- depositing
- impurity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/011—Bipolar transistors
Abstract
Description
Claims (3)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019870008119A KR890003827B1 (en) | 1987-07-25 | 1987-07-25 | Process adapted to the manufacture of bicmos |
KR87-8119 | 1987-07-25 |
Publications (1)
Publication Number | Publication Date |
---|---|
US4954456A true US4954456A (en) | 1990-09-04 |
Family
ID=19263293
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US07/224,020 Expired - Fee Related US4954456A (en) | 1987-07-25 | 1988-07-25 | Fabrication method for high speed and high packing density semiconductor device (BiCMOS) |
Country Status (3)
Country | Link |
---|---|
US (1) | US4954456A (en) |
JP (1) | JPH065706B2 (en) |
KR (1) | KR890003827B1 (en) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5001073A (en) * | 1990-07-16 | 1991-03-19 | Sprague Electric Company | Method for making bipolar/CMOS IC with isolated vertical PNP |
US5011784A (en) * | 1988-01-21 | 1991-04-30 | Exar Corporation | Method of making a complementary BiCMOS process with isolated vertical PNP transistors |
US5262345A (en) * | 1990-01-25 | 1993-11-16 | Analog Devices, Inc. | Complimentary bipolar/CMOS fabrication method |
US5409845A (en) * | 1992-01-31 | 1995-04-25 | Analog Devices, Inc. | Method of making complementary bipolar polysilicon emitter devices |
US6455364B1 (en) | 1999-03-15 | 2002-09-24 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
US20040166638A1 (en) * | 2002-12-30 | 2004-08-26 | Dongbu Electronics Co. Ltd. | Method of forming isolation structures in embedded semiconductor device |
US20070111457A1 (en) * | 2003-11-13 | 2007-05-17 | Volterra Semiconductor Corporation | Method of fabricating a lateral double-diffused mosfet (ldmos) transistor and a conventional cmos transistor |
US20080303089A1 (en) * | 2007-06-07 | 2008-12-11 | Advanced Micro Devices, Inc. | Integrated circuit system with triode |
US20110133274A1 (en) * | 2003-11-13 | 2011-06-09 | Volterra Semiconductor Corporation | Lateral double-diffused mosfet |
US20120299114A1 (en) * | 2011-05-24 | 2012-11-29 | Semiconductor Components Industrires, LLC | Semiconductor device and method of manufacturing the same |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6037195A (en) * | 1997-09-25 | 2000-03-14 | Kabushiki Kaisha Toshiba | Process of producing thin film transistor |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4686762A (en) * | 1985-08-05 | 1987-08-18 | Electronics And Telecommunication Research Institute | Fabricating semiconductor device with polysilicon protection layer during processing |
US4784971A (en) * | 1986-04-23 | 1988-11-15 | American Telephone And Telegraph Company, At&T Bell Laboratories | Process for manufacturing semiconductor BICMOS device |
-
1987
- 1987-07-25 KR KR1019870008119A patent/KR890003827B1/en not_active IP Right Cessation
-
1988
- 1988-07-19 JP JP63178271A patent/JPH065706B2/en not_active Expired - Lifetime
- 1988-07-25 US US07/224,020 patent/US4954456A/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4686762A (en) * | 1985-08-05 | 1987-08-18 | Electronics And Telecommunication Research Institute | Fabricating semiconductor device with polysilicon protection layer during processing |
US4784971A (en) * | 1986-04-23 | 1988-11-15 | American Telephone And Telegraph Company, At&T Bell Laboratories | Process for manufacturing semiconductor BICMOS device |
Cited By (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5011784A (en) * | 1988-01-21 | 1991-04-30 | Exar Corporation | Method of making a complementary BiCMOS process with isolated vertical PNP transistors |
US5262345A (en) * | 1990-01-25 | 1993-11-16 | Analog Devices, Inc. | Complimentary bipolar/CMOS fabrication method |
US5001073A (en) * | 1990-07-16 | 1991-03-19 | Sprague Electric Company | Method for making bipolar/CMOS IC with isolated vertical PNP |
US5409845A (en) * | 1992-01-31 | 1995-04-25 | Analog Devices, Inc. | Method of making complementary bipolar polysilicon emitter devices |
US5444285A (en) * | 1992-01-31 | 1995-08-22 | Analog Devices, Inc. | Complementary bipolar polysilicon emitter devices |
US6455364B1 (en) | 1999-03-15 | 2002-09-24 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
EP1037284A3 (en) * | 1999-03-15 | 2002-10-30 | Matsushita Electric Industrial Co., Ltd. | Heterojunction bipolar transistor and method for fabricating the same |
US20020197809A1 (en) * | 1999-03-15 | 2002-12-26 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
US6713790B2 (en) | 1999-03-15 | 2004-03-30 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
US20040166638A1 (en) * | 2002-12-30 | 2004-08-26 | Dongbu Electronics Co. Ltd. | Method of forming isolation structures in embedded semiconductor device |
US20070111457A1 (en) * | 2003-11-13 | 2007-05-17 | Volterra Semiconductor Corporation | Method of fabricating a lateral double-diffused mosfet (ldmos) transistor and a conventional cmos transistor |
US7666731B2 (en) * | 2003-11-13 | 2010-02-23 | Volterra Semiconductor Corporation | Method of fabricating a lateral double-diffused MOSFET (LDMOS) transistor and a conventional CMOS transistor |
US20110133274A1 (en) * | 2003-11-13 | 2011-06-09 | Volterra Semiconductor Corporation | Lateral double-diffused mosfet |
US7981739B1 (en) * | 2003-11-13 | 2011-07-19 | Volterra Semiconductor Corporation | Method of fabricating a lateral double-diffused MOSFET (LDMOS) transistor and a conventional CMOS transistor |
US8354717B2 (en) | 2003-11-13 | 2013-01-15 | Volterra Semiconductor Corporation | Lateral double-diffused MOSFET |
US8405148B1 (en) | 2003-11-13 | 2013-03-26 | Volterra Semiconductor Corporation | Method of fabricating a lateral double-diffused MOSFET (LDMOS) transistor and a conventional CMOS transistor |
US8574973B1 (en) * | 2003-11-13 | 2013-11-05 | Volterra Semiconductor Corporation | Method of fabricating a lateral double-diffused MOSFET (LDMOS) transistor and a conventional CMOS transistor |
US8698242B2 (en) | 2003-11-13 | 2014-04-15 | Volterra Semiconductor Corporation | Lateral double-diffused MOSFET |
US8994106B2 (en) | 2003-11-13 | 2015-03-31 | Volterra Semiconductor LLC | Lateral double-diffused MOSFET |
US20080303089A1 (en) * | 2007-06-07 | 2008-12-11 | Advanced Micro Devices, Inc. | Integrated circuit system with triode |
US8089125B2 (en) * | 2007-06-07 | 2012-01-03 | Advanced Micro Devices, Inc. | Integrated circuit system with triode |
US20120299114A1 (en) * | 2011-05-24 | 2012-11-29 | Semiconductor Components Industrires, LLC | Semiconductor device and method of manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
JPH0193159A (en) | 1989-04-12 |
KR890003827B1 (en) | 1989-10-05 |
KR890003026A (en) | 1989-04-12 |
JPH065706B2 (en) | 1994-01-19 |
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Legal Events
Date | Code | Title | Description |
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Owner name: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTIT Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:KIM, KWANG SOO;CHAI, SANG HUN;KOO, YOUNG SEO;AND OTHERS;REEL/FRAME:004975/0992;SIGNING DATES FROM 19880926 TO 19880928 Owner name: KOREA TELECOMMUNICATION AUTHORITY, 100, SEJONG-NO, Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:KIM, KWANG SOO;CHAI, SANG HUN;KOO, YOUNG SEO;AND OTHERS;REEL/FRAME:004975/0992;SIGNING DATES FROM 19880926 TO 19880928 Owner name: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTIT Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KIM, KWANG SOO;CHAI, SANG HUN;KOO, YOUNG SEO;AND OTHERS;SIGNING DATES FROM 19880926 TO 19880928;REEL/FRAME:004975/0992 Owner name: KOREA TELECOMMUNICATION AUTHORITY, KOREA, REPUBLIC Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KIM, KWANG SOO;CHAI, SANG HUN;KOO, YOUNG SEO;AND OTHERS;SIGNING DATES FROM 19880926 TO 19880928;REEL/FRAME:004975/0992 |
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