US5021683A - Circuit arrangement comprising two parallel branches for transmitting a binary signal - Google Patents
Circuit arrangement comprising two parallel branches for transmitting a binary signal Download PDFInfo
- Publication number
- US5021683A US5021683A US07/478,793 US47879390A US5021683A US 5021683 A US5021683 A US 5021683A US 47879390 A US47879390 A US 47879390A US 5021683 A US5021683 A US 5021683A
- Authority
- US
- United States
- Prior art keywords
- branch
- supply means
- circuit arrangement
- binary signal
- gates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/22—Arrangements for detecting or preventing errors in the information received using redundant apparatus to increase reliability
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
- Small-Scale Networks (AREA)
- Electronic Switches (AREA)
- Safety Devices In Control Systems (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
A circuit arrangement for transmitting in an undisturbed manner a binary signal through two parallel branches even in case of breakdown, failure or interruption of operating voltages of individual components of a branch, and also to enable a disturbance-free exchanging of individual modules in a branch in which each branch has its own supply means fed by an input for the binary signal to be transmitted, which supply means has two gates together producing an inverting and a non-inverting output. Each branch has its own receiver which is connected to the non-inverted output of the supply means of that branch and the inverting output of the supply means of the other branch. Each receiver includes a difference amplifier which provides the output of the branch, and a network of resistors and diodes which feeds the difference amplifier.
Description
The invention relates to a circuit arrangement comprising two parallel branches for transmitting a binary signal, one signal source each applying a binary signal to each branch
Such circuit arrangements are necessary, for example, for clock supply means in information technology For this purpose, in order to fulfil the requirements as to operating reliability, it is advantageous to arrange the most important modules in e.g. two parallel branches, a binary signal, e. g. a clock signal, being applied to each branch from its independent source. The two binary signals are synchronised and show great similarity. One branch is used while the other branch is kept in reserve. In case of breakdown or failure of the utilized branch, the branch kept in reserve can assure proper functioning.
It is an object of the invention to provide a circuit arrangement of the type mentioned in the opening paragraph, which transmits the binary signal in an undisturbed manner without a switchover in case of breakdown, failure or interruption of the operating voltage of individual circuit components in a branch, whilst also the exchanging of individual modules in a branch is possible without disturbing the transmission of the binary signal.
The object is achieved by means of a circuit arrangement of the type mentioned in the opening paragraph, in that the branches comprise each a supply means fed by the binary signal, each means comprising two gates that have an inverting and a non-inverting output, in that each branch comprises at least one receiver that includes a differential amplifier, to which receiver the non-inverting output of the associated supply means and the inverting output of the other supply means are connected and in that the operating voltages are furnished through time delay means.
The invention will be further explained with reference to the drawing in which:
The sole drawing FIGURE shows a circuit arrangement comprising two parallel branches for transmitting a binary signal in accordance with the invention.
The sole FIGURE shows a redundant electronic circuit arrangement comprising two parallel branches for transmitting a binary signal. An identical binary signal UE is applied to each branch from two independent sources. The first branch comprises a first supply means S1 fed by an operating voltage UB1 and a first receiver E1 fed by an operating voltage UB3. The second branch connected in parallel to the first branch has the same structure as the first branch and comprises a second supply means S2 fed by an operating voltage UB2 and also includes a second receiver E2 fed by an operating voltage UB4.
Each supply means comprises a first gate G having a non-inverting output connected to the anode of a diode D1, and also includes a second gate I having an inverting output connected to the anode of a diode D2. The operating voltages UB1, OB2 of the supply means S1, S2 are furnished through time delaY means T. A binary signal UE is applied to the power supply means S1, S2 from two independent sources (not shown in the drawing) and switched to the inputs of the gates G. The binary signals are synchronised so that they show great similarity
A signal 1 on the cathode of the diode D1 of the first transmitter S1 is applied to the non-inverting input of a difference amplifier A of the first receiver E1 through a resistor R1, whereas a signal 2 on the cathode of the diode D2 of the first transmitter S1 is switched to the inverting input of the difference amplifier A of the second receiver E2 through a resistor R2 Accordingly, a signal 3 on the cathode of the diode D1 of the second transmitter S2 is switched to the non-inverting input of the differential amplifier A of the second receiver E2 and a signal 4 on the cathode of the diode D2 of the second transmitter S2 is switched to the inverting input of the difference amplifier A of the first receiver E1. At the outputs of the differential amplifiers A of the two receivers E1, E2 are available signals 5, 6 which are combined to one output signal UA through the decoupling resistors R5, R6.
The operating voltages UB3, UB4 of the differential amplifiers A of receivers E1, E2 are also applied through time delay means T. The inputs of the differential amplifiers A are decoupled through a resistor network R1, R2, R3, R4 and their voltages are limited across parallel diodes D3, D1 For this purpose the anode of diode D3 is connected to the non-inverting input of the differential amplifier A whereas the cathode is connected to the inverting input. The diode D4 is connected in opposite polarity to D3. In addition, the inputs of the differential amplifier A are interconnected via a series connection of the resistors R3, R4, the operating voltage UB3 being applied over their common junction 7 through a resistor R7. The junction 7 is also connected to ground across a diode D5.
In order to avoid reactions on the function of the circuitry, the outputs of the gates G, I respectively, are to become high-ohmic together with the inverting output (inverter I) of the supply means in case of failure For this purpose the gate G and the inverter I of the supply means S1, S2 are advantageously arranged as tri-state buffers in TTL technology, i.e. the output of the gate G and the inverter I may assume also a third high-ohmic state in addition to the two states 1 or 0.
Each supply means and receiver is arranged as a plug-in module. The necessary ground contacts of each module are then realised as so-called leading ground contacts, i e when the individual modules are plugged in, first the ground contacts are established before the live connections are made.
The circuit arrangement of the exemplary embodiment shown in the FIGURE thus provides that the binary signal UE, also in case of breakdown, failure or interruptions of operating voltages of individual circuit components is transmitted in an undisturbed manner. Furthermore, the exchanging of individual modules can also be realised without disturbing the transmission of the binary signal UE.
If the operating voltage UB1 of the first transmitter and thus of the gate G and inverter I fails, the diodes D1 and D2 will e.g. decouple the lines carryinq the signals 1 2 at the outputs of gate G and inverter l The receivers E1, E2 will then be supplied with the signals 3, 4 of the second transmitter S2 in an undisturbed manner. The circuit arrangement will behave accordinglY if the oPerating voltage UB2 of the second transmitter fails. Since the gate G and the inverter I are arranged as tri-state buffers in TTL technology, their outputs will assume a high-ohmic state if the operating voltages fail.
The inputs to the receivers E1, E2 are decoupled through the resistors R1, R2, their outputs through the resistors R5, R6 so that, e.g. if the operating voltage UB3 of the first receiver fails, the second receiver will be further fed by means of the signals 2, 3 and will thus transmit the binary signal UE in an undisturbed manner.
The breakdown of a transmitter S1 or S2 or the failure of the binary signal UE at the input of a transmitter S1, S2 will be ineffective with respect to the transmission of the binary signals UE owing to the resistor network R1, R2, R3, R4 and owing to the grounded diodes D5 of the receiver E1, E2 and also as a result of a suitably high sensitivity of the differential amplifier A.
The great sensitivity of the differential amplifier A leads to high switching voltages when individual modules are exchanged. Consequently, in order to avoid this problem, the voltages of the differential amplifier A are limited by means of the diodes D3, D4. In order to further maintain the switching voltages at a low level especially when a module is plugged in, the operating voltages UB1, UB2, UB3, UB4 of the transmitters S1, S2 and receivers E1, E2 are supplied through time delay means T.
The reliability may even be enhanced by connecting further receivers in parallel with the receivers E1, E2.
Claims (6)
1. Circuit arrangement comprising two parallel connected branches for transmitting a binary signal, an input for applying said binary signal (UE) to each branch, characterized in that each branch comprises a supply means (S1, S2) coupled to the input, each supply means comprising two gates coupled to said input, one of said two gates having an inverted output and another of said two gates having a non-inverted output, each branch further comprises a receiver (E1, E2) that includes a differential amplifier (A), having the non-inverted output of the supply means of the respective branch and the inverted output of the supply means of the other branch connected thereto and wherein operating voltages (UB1, UB2, UB3, UB4) are coupled to the gates and the differential amplifiers through time delay means (T).
2. Circuit arrangement as claimed in claim 1, characterized in that the gates (G, I) of the supply means (S1, S2) are arranged as tri-state buffers in TTL technology.
3. Circuit arrangement as claimed in claim 1, characterized in that the receivers (E) further comprise a resistor network (R1, R2, R3, R4) and rectifier diodes (D3, D4).
4. Circuit arrangement as claimed in claim 1, characterized in that the supply means (S1, S2) and the receivers (E1, E2) are arranged as plug-in modules.
5. Circuit arrangement as claimed in claim 2, characterized in that the receivers (E) further comprise a resistor network (R1, R2, R3, R4) and rectifier diodes (D3, D4).
6. Circuit arrangement as claimed in claim 5, characterized in that the supply means (S1, S2) and the receivers (E1, E2) are arranged as plug-in modules.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE3905689A DE3905689A1 (en) | 1989-02-24 | 1989-02-24 | CIRCUIT ARRANGEMENT WITH TWO PARALLEL BRANCHES FOR TRANSMITTING A BINARY SIGNAL |
| DE3905689 | 1989-02-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| US5021683A true US5021683A (en) | 1991-06-04 |
Family
ID=6374807
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US07/478,793 Expired - Fee Related US5021683A (en) | 1989-02-24 | 1990-02-12 | Circuit arrangement comprising two parallel branches for transmitting a binary signal |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5021683A (en) |
| EP (1) | EP0384528B1 (en) |
| JP (1) | JPH0317720A (en) |
| DE (2) | DE3905689A1 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5721875A (en) * | 1993-11-12 | 1998-02-24 | Intel Corporation | I/O transceiver having a pulsed latch receiver circuit |
| US5870332A (en) * | 1996-04-22 | 1999-02-09 | United Technologies Corporation | High reliability logic circuit for radiation environment |
| US6262605B1 (en) * | 1999-05-06 | 2001-07-17 | International Business Machines Corporation | Automated line driver control circuit for power managed system |
| US6381506B1 (en) * | 1996-11-27 | 2002-04-30 | Victor Grappone | Fail-safe microprocessor-based control and monitoring of electrical devices |
| WO2006059269A2 (en) * | 2004-12-01 | 2006-06-08 | Koninklijke Philips Electronics N.V. | Electronic device having logic circuitry and method for designing logic circuitry |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5386424A (en) * | 1993-03-31 | 1995-01-31 | Honeywell, Inc. | Apparatus and method for transmitting information between dual redundant components utilizing four signal paths |
| DE19814098C1 (en) * | 1998-03-30 | 1999-10-07 | Hartmann & Braun Gmbh & Co Kg | Redundant relay contact control circuit for automation system |
| DE10062373A1 (en) * | 2000-12-14 | 2002-07-04 | Siemens Ag | Generating clock signal involves reference clock unit generating clock signal to clock and/or synchronize circuit unit if clock signal normally received from another clock unit fails |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4066910A (en) * | 1976-04-09 | 1978-01-03 | Lawrence Systems, Inc. | Transmissivity-coded data card systems |
| US4154978A (en) * | 1977-12-08 | 1979-05-15 | Operating Systems, Inc. | Self-contained bidirectional amplifying repeater |
| US4250570A (en) * | 1976-07-15 | 1981-02-10 | Intel Corporation | Redundant memory circuit |
| US4419595A (en) * | 1981-10-14 | 1983-12-06 | The United States Of America As Represented By The Secretary Of The Air Force | Analog or gate circuit |
| US4475049A (en) * | 1981-05-07 | 1984-10-02 | Smith Robert E | Redundant serial communication circuit |
| US4480198A (en) * | 1981-05-20 | 1984-10-30 | La Telephonie Industrielle Et Commerciale Telic Alcatel | Device for increasing the operational security of a duplicated clock |
| US4608504A (en) * | 1983-01-20 | 1986-08-26 | Sharp Kabushiki Kaisha | Interface circuit for interconnecting peripherals to an information processing device |
| US4611136A (en) * | 1982-12-14 | 1986-09-09 | Pioneer Electronic Corporation | Signal delay generating circuit |
| US4626707A (en) * | 1983-06-03 | 1986-12-02 | Hitachi, Ltd. | Signal selection circuit |
| US4761572A (en) * | 1986-03-15 | 1988-08-02 | Fujitsu Limited | Semiconductor large scale integrated circuit with noise cut circuit |
| US4835422A (en) * | 1988-03-14 | 1989-05-30 | North American Philips Corporation | Arbiter circuits with metastable free outputs |
| US4849657A (en) * | 1984-09-17 | 1989-07-18 | Honeywell Inc. | Fault tolerant integrated circuit design |
| US4928022A (en) * | 1987-07-17 | 1990-05-22 | Trw Inc. | Redundancy interconnection circuitry |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2359553A1 (en) * | 1976-07-22 | 1978-02-17 | France Etat | DIGITAL TRANSMISSION DUAL CHANNEL SYSTEM |
| JPS60208135A (en) * | 1984-03-31 | 1985-10-19 | Toshiba Corp | Data transmission equipment |
-
1989
- 1989-02-24 DE DE3905689A patent/DE3905689A1/en not_active Withdrawn
-
1990
- 1990-02-12 US US07/478,793 patent/US5021683A/en not_active Expired - Fee Related
- 1990-02-19 DE DE59009168T patent/DE59009168D1/en not_active Expired - Fee Related
- 1990-02-19 EP EP90200375A patent/EP0384528B1/en not_active Expired - Lifetime
- 1990-02-21 JP JP2040840A patent/JPH0317720A/en active Pending
Patent Citations (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4066910A (en) * | 1976-04-09 | 1978-01-03 | Lawrence Systems, Inc. | Transmissivity-coded data card systems |
| US4250570B1 (en) * | 1976-07-15 | 1996-01-02 | Intel Corp | Redundant memory circuit |
| US4250570A (en) * | 1976-07-15 | 1981-02-10 | Intel Corporation | Redundant memory circuit |
| US4154978A (en) * | 1977-12-08 | 1979-05-15 | Operating Systems, Inc. | Self-contained bidirectional amplifying repeater |
| US4475049A (en) * | 1981-05-07 | 1984-10-02 | Smith Robert E | Redundant serial communication circuit |
| US4480198A (en) * | 1981-05-20 | 1984-10-30 | La Telephonie Industrielle Et Commerciale Telic Alcatel | Device for increasing the operational security of a duplicated clock |
| US4419595A (en) * | 1981-10-14 | 1983-12-06 | The United States Of America As Represented By The Secretary Of The Air Force | Analog or gate circuit |
| US4611136A (en) * | 1982-12-14 | 1986-09-09 | Pioneer Electronic Corporation | Signal delay generating circuit |
| US4608504A (en) * | 1983-01-20 | 1986-08-26 | Sharp Kabushiki Kaisha | Interface circuit for interconnecting peripherals to an information processing device |
| US4626707A (en) * | 1983-06-03 | 1986-12-02 | Hitachi, Ltd. | Signal selection circuit |
| US4849657A (en) * | 1984-09-17 | 1989-07-18 | Honeywell Inc. | Fault tolerant integrated circuit design |
| US4761572A (en) * | 1986-03-15 | 1988-08-02 | Fujitsu Limited | Semiconductor large scale integrated circuit with noise cut circuit |
| US4928022A (en) * | 1987-07-17 | 1990-05-22 | Trw Inc. | Redundancy interconnection circuitry |
| US4835422A (en) * | 1988-03-14 | 1989-05-30 | North American Philips Corporation | Arbiter circuits with metastable free outputs |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5721875A (en) * | 1993-11-12 | 1998-02-24 | Intel Corporation | I/O transceiver having a pulsed latch receiver circuit |
| US5870332A (en) * | 1996-04-22 | 1999-02-09 | United Technologies Corporation | High reliability logic circuit for radiation environment |
| US6381506B1 (en) * | 1996-11-27 | 2002-04-30 | Victor Grappone | Fail-safe microprocessor-based control and monitoring of electrical devices |
| US6262605B1 (en) * | 1999-05-06 | 2001-07-17 | International Business Machines Corporation | Automated line driver control circuit for power managed system |
| WO2006059269A2 (en) * | 2004-12-01 | 2006-06-08 | Koninklijke Philips Electronics N.V. | Electronic device having logic circuitry and method for designing logic circuitry |
| WO2006059269A3 (en) * | 2004-12-01 | 2006-08-10 | Koninkl Philips Electronics Nv | Electronic device having logic circuitry and method for designing logic circuitry |
| US20090230988A1 (en) * | 2004-12-01 | 2009-09-17 | Koninklijke Philips Electronics, N.V. | Electronic device having logic circuitry and method for designing logic circuitry |
Also Published As
| Publication number | Publication date |
|---|---|
| EP0384528A3 (en) | 1991-11-13 |
| DE59009168D1 (en) | 1995-07-06 |
| DE3905689A1 (en) | 1990-08-30 |
| EP0384528B1 (en) | 1995-05-31 |
| JPH0317720A (en) | 1991-01-25 |
| EP0384528A2 (en) | 1990-08-29 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| AS | Assignment |
Owner name: U.S. PHILIPS CORPORATION, A CORP. OF DELAWARE, NEW Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:SCHEMMEL, HANS-ROBERT;REEL/FRAME:005278/0375 Effective date: 19900328 |
|
| FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
| FPAY | Fee payment |
Year of fee payment: 4 |
|
| REMI | Maintenance fee reminder mailed | ||
| LAPS | Lapse for failure to pay maintenance fees | ||
| STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
| FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20030604 |