US5183770A - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
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- US5183770A US5183770A US07/842,515 US84251592A US5183770A US 5183770 A US5183770 A US 5183770A US 84251592 A US84251592 A US 84251592A US 5183770 A US5183770 A US 5183770A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 52
- 239000010410 layer Substances 0.000 claims abstract description 52
- 238000000034 method Methods 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 238000009413 insulation Methods 0.000 claims abstract description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 27
- 229920005591 polysilicon Polymers 0.000 claims abstract description 27
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 26
- 229910052681 coesite Inorganic materials 0.000 claims abstract description 26
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract description 26
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 26
- 229910052682 stishovite Inorganic materials 0.000 claims abstract description 26
- 229910052905 tridymite Inorganic materials 0.000 claims abstract description 26
- 238000010438 heat treatment Methods 0.000 claims abstract description 20
- 238000000151 deposition Methods 0.000 claims abstract description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 238000009792 diffusion process Methods 0.000 claims abstract description 8
- 239000012212 insulator Substances 0.000 claims abstract description 8
- 239000011229 interlayer Substances 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 8
- 239000010703 silicon Substances 0.000 claims abstract description 8
- 238000005468 ion implantation Methods 0.000 claims abstract description 5
- 150000002500 ions Chemical class 0.000 claims description 12
- 230000007547 defect Effects 0.000 claims description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 239000005380 borophosphosilicate glass Substances 0.000 claims 4
- 238000001020 plasma etching Methods 0.000 description 10
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 230000000717 retained effect Effects 0.000 description 3
- -1 Si2 H6 Chemical class 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- 229910003910 SiCl4 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- XMIJDTGORVPYLW-UHFFFAOYSA-N [SiH2] Chemical compound [SiH2] XMIJDTGORVPYLW-UHFFFAOYSA-N 0.000 description 1
- 238000010306 acid treatment Methods 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- FDNAPBUWERUEDA-UHFFFAOYSA-N silicon tetrachloride Chemical compound Cl[Si](Cl)(Cl)Cl FDNAPBUWERUEDA-UHFFFAOYSA-N 0.000 description 1
- 230000007306 turnover Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
- H01L21/2652—Through-implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Definitions
- This invention relates to a method for fabricating semiconductor devices. More specifically, it relates to a method for fabricating MOS devices having the so-called LDD structure in which diffusion regions are formed in a silicon substrate with use of a gate electrode part having side walls as a mask. This method reduces crystalline defects of the Si substrate significantly.
- FIG. 2 A typical and conventional method for fabricating a MOS device having a LDD structure is illustrated with reference to FIG. 2.
- a gate electrode 13 is formed on a Si substrate 11 with a SiO 2 film 12 interposed therebetween in accordance with a common method [See FIG. 2(a)]. Subsequently, the Si substrate 11 and the gate electrode 13 are thoroughly covered with another SiO 2 film by CVD process. Such a SiO 2 film is then subjected to reactive ion etching (RIE) and HF cleaning but is retained around the gate electrode and on the substrate, to form side walls [See FIG. 2(b)]. In this case the thickness of the SiO 2 film 14a retained on the substrate is about 100-400 ⁇ .
- impurity ions 15 are implanted with use of the gate electrode and side walls as a mask [See FIG. 2(c)], followed by a heat treatment at an elevated temperature, to form diffusion regions in the Si substrate.
- the present invention is accomplished to overcome the foregoing problems.
- the invention provides a method for fabricating a semiconductor device, comprising the steps of:
- a gate electrode is formed on a Si substrate with a gate oxide sandwiched therebetween.
- the gate oxide is formed by a thermal oxidation process.
- the gate electrode may be composed of a single polysilicon layer or a stacked layer of polysilicon, non-doped silicated glass (NSG), boron-doped phospho-silicate glass (BPSG) and the like. These layers can be formed by CVD process.
- next step (b) first, an insulation film is formed to entirely cover the substrate and the gate electrode, and a polysilicon or amorphous silicon layer is then formed on the insulation film.
- the insulation film may be the same SiO 2 film as the gate oxide in the above step (a) but may be a SiN film.
- the insulation film is 50 to 100 ⁇ in thickness.
- the polysilicon or amorphous silicon layer can be formed by LPCVD technique, using a Si compound such as Si 2 H 6 , SiH 4 , SiH 2 Cl 2 , SiCl 4 or the like.
- the polysilicon layer is in general formed by CVD technique at a relatively high temperature such as 600° to 650° C. under a pressure of 10 to 50 Pa.
- the amorphous silicon layer is in general formed by CVD technique at a relatively low temperature such as 450° to 500° C. under a pressure of 10 to 50 Pa.
- these polysilicon layer or amorphous silicon layer are 100 to 200 ⁇ in thickness.
- next step (c) side walls are formed. They are formed in a manner that SiO 2 is first deposited by LPCVD technique to entirely cover the amorphous silicon layer or polysilicon layer and then etched.
- a dry etching method is used and particularly, RIE method is available which uses positive ions (for example CF 3 + etc.) generated by applying high-frequency power to a carbon floride gas such as CF 4 , C 2 F 6 , CHF 3 or the like under vacuum to cause it to discharge.
- positive ions for example CF 3 + etc.
- a carbon floride gas such as CF 4 , C 2 F 6 , CHF 3 or the like under vacuum to cause it to discharge.
- a HF treatment may be carried out for example in order to etch the edge part of the side wall.
- ions such as AS + , P + or the like are vertically implanted to the Si substrate.
- next step (d) first, the side walls are removed by a HF treatment to make the device stress-free. Thereafter, a heat treatment is conducted for the purpose of forming in the Si substrate a diffusion region of the implanted ions.
- This suitable heat treatment is for example that at a medium temperature of 800° to 850° C.
- Sequentially the polysilicon layer or amorphous silicon layer is removed by etching. a dry etching method is used, and particularly, RIE method having a strong isotropic property which uses CCL 4 , SF 6 or the like is available.
- An interlayer insulator is then stacked on the entire surface.
- the interlayer insulator may comprise a single BPSG layer or a stacked layer of NSG and BPSG in this order.
- the heat treatment at a high temperature for example at 900° to 950° C. is then performed to planarise the interlayer insulator and to complete the formation of the diffusion regions.
- FIG. 1 (a)-(d) schematically illustrates fabrication steps of a semiconductor device according to a method for fabricating a semiconductor device of the invention
- FIG. 2 (a)-(c) schematically illustrates fabrication steps of a semiconductor device according to a conventional method for fabricating a semiconductor device.
- a gate electrode 3 is formed on a Si substrate 1 by CVD technique with a gate oxide sandwiched therebetween. A small amount of SiO 2 existing on the substrate 1 is then removed with hydrofluoric acid.
- the overall surface of the Si substrate 1 and the gate electrode 3 undergoes thermal oxidation to form a SiO 2 insulation film 4 of about 50-100 ⁇ thick.
- a polysilicon layer 5 is deposited on the film 4 to about 100-200 ⁇ thick by a CVD technique using Si 2 H 6 at 620° C. under 20 Pa.
- SiO 2 is deposited by CVD technique and etched by RIE method using CF 4 with optional HF cleaning to form side walls 6 on both sides of the gate electrode portion including the SiO 2 insulation film 4 and the polysilicon layer 5.
- As + ions are implanted (indicated by an arrow 7) at an acceleration energy of 60-80 KeV and a dose of 5 ⁇ 10 15 with use of the gate electrode portion and side walls 6 as a mask.
- a heat treatment at 800°-850° C. is conducted to form a diffusinon region 8, followed by removal of the polysilicon layer 5 by RIE method using CCl 4 , as shown in FIG. (d).
- a BPSG layer is deposited over the entire surface of the device by a common technique, and a heat treatment at 900°-950° C. is conducted to planarize the BPSG layer, followed by forming a contact hole and metallic wiring.
- a semiconductor device is completed.
- a gate electrode 3 is first formed on a Si substrate 1 by the same technique as that in Example 1 with a gate oxide sandwiched therebetween. A small amount of SiO 2 existing on the substrate 1 is then removed with hydrofluoric acid.
- the overall surface of the Si substrate 1 and the gate electrode 3 undergoes thermal oxidation to form a SiO 2 insulation film 4 of about 50-100 ⁇ thick.
- a SiO 2 insulation film 4 of about 50-100 ⁇ thick.
- an amorphous silicon layer 5' to about 100-200 ⁇ thick by a CVD technique using Si 2 H 6 at 460° C. under 20 Pa.
- SiO 2 is deposited by CVD technique and etched by RIE method using CF 4 with optional HF treatment to form side walls 6 on both sides of the gate electrode portion including the SiO 2 film 4 and the amorphous silicon layer 5'.
- As + ions are implanted (indicated by an arrow 7) at an acceleration energy of 60-80 KeV and a dose of 5 ⁇ 10 15 with use of the gate electrode portion and side walls 6 as a mask.
- the side walls are removed by a HF treatment to make the device stress-free, then a heat treatment at 800°-850° C. is conducted to diffuse the implanted ions, followed by removal of the amorphous silicon layer 5' by RIE method using CCl 4 , as shown in FIG. (d).
- NSG layer and a BPSG layer are deposited in turn over the entire surface of the device by a common technique, and a heat treatment at 900°-950° C. is conducted to planarize the above layers, followed by forming a contact hole and metallic wiring.
- a semiconductor device is completed.
- the polysilicon or amorphous silicon layer over the SiO 2 insulation film covering the Si substrate makes it possible to materially reduce the amount of oxygen of the SiO 2 insulation film to possibly be injected into the Si substrate as ions are implanted.
- the diffusion layer formed after the heat treatment has significantly reduced crystalline defects.
- the polysilicon or amorphous silicon layer blocks the etching for making side-walls, resulting in reduced variation in thickness of the SiO 2 insulation film and polysilicon or amorphous silicon layer. This turns out to be facilitated control of film thickness and decreased defect density in the diffusion layer.
- the amorphous silicon layer is substantially equivalent to the SiO 2 insulation film in injection coefficient, leading to uniform ion implantation. This results in an improved semiconductor device of reduced leakage of current, sufficient resistance against junction stress, enhanced reliability and increased yield.
Abstract
A method for fabricating a semiconductor device in which diffusion regions are formed in a silicon substrate with use of a gate electrode parts having side walls as a mask, including the steps of: (a) forming a gate electrode on a silicon substrate with a gate oxide interposed therebetween; (b) depositing an insulation film to entirely cover the substrate and the gate electrode, followed by depositing a polysilicon or amorphous silicon layer on the insulation film; (c) forming side walls of SiO2 on lateral sides of the gate electrode covered with the insulation film and the polysilicon or amorphous silicon layer, followed by ion implantation; and (d) subjecting the resulting substrate to a heat treatment at a medium temperature after removal of the side walls, followed by stacking an interlayer insulator after removal of the polysilicon or amorphous silicon layer, and subjecting the resultant to a heat treatment at a high temperature.
Description
This invention relates to a method for fabricating semiconductor devices. More specifically, it relates to a method for fabricating MOS devices having the so-called LDD structure in which diffusion regions are formed in a silicon substrate with use of a gate electrode part having side walls as a mask. This method reduces crystalline defects of the Si substrate significantly.
A typical and conventional method for fabricating a MOS device having a LDD structure is illustrated with reference to FIG. 2.
First, a gate electrode 13 is formed on a Si substrate 11 with a SiO2 film 12 interposed therebetween in accordance with a common method [See FIG. 2(a)]. Subsequently, the Si substrate 11 and the gate electrode 13 are thoroughly covered with another SiO2 film by CVD process. Such a SiO2 film is then subjected to reactive ion etching (RIE) and HF cleaning but is retained around the gate electrode and on the substrate, to form side walls [See FIG. 2(b)]. In this case the thickness of the SiO2 film 14a retained on the substrate is about 100-400 Å. Next, impurity ions 15 are implanted with use of the gate electrode and side walls as a mask [See FIG. 2(c)], followed by a heat treatment at an elevated temperature, to form diffusion regions in the Si substrate.
With the above method, however, oxygen existing in the SiO2 film is injected along with the impurity ions into the Si substrate thereby fixing crystalline defects 16 of the substrate. These defects 16 cannot be removed even if subjected to the subsequent heat treatment at a high temperature. Furthermore, since the retained SiO2 film 14a resulted from the RIE and HF cleaning is largely irregular in thickness, the defect density of the substrate is made higher, leading to occurrence of current leakage and decrease in yield.
The present invention is accomplished to overcome the foregoing problems.
Thus, the invention provides a method for fabricating a semiconductor device, comprising the steps of:
(a) forming a gate electrode on a semiconductor silicon substrate with a gate oxide interposed therebetween;
(b) depositing an insulation film to entirely cover the substrate and the gate electrode, followed by depositing a polysilicon or amorphous silicon layer on the insulation film;
(c) forming side walls of SiO2 on lateral sides of the gate electrode covered with the insulation film and the polysilicon or amorphous silicon layer, followed by ion implantation; and
(d) subjecting the resulting substrate to a heat treatment at a medium temperature after removal of the side walls, stacking an interlayer insulator after removal of the polysilicon or amorphous silicon layer, and subjecting the sultant to a heat treatment at a high temperature.
Each of the above-mentioned steps (a) to (d) of the present invention can be carried out using known means and apparatus.
In step (a), a gate electrode is formed on a Si substrate with a gate oxide sandwiched therebetween. The gate oxide is formed by a thermal oxidation process. The gate electrode may be composed of a single polysilicon layer or a stacked layer of polysilicon, non-doped silicated glass (NSG), boron-doped phospho-silicate glass (BPSG) and the like. These layers can be formed by CVD process.
In next step (b), first, an insulation film is formed to entirely cover the substrate and the gate electrode, and a polysilicon or amorphous silicon layer is then formed on the insulation film.
The insulation film may be the same SiO2 film as the gate oxide in the above step (a) but may be a SiN film.
Preferably the insulation film is 50 to 100 Å in thickness. The polysilicon or amorphous silicon layer can be formed by LPCVD technique, using a Si compound such as Si2 H6, SiH4, SiH2 Cl2, SiCl4 or the like. The polysilicon layer is in general formed by CVD technique at a relatively high temperature such as 600° to 650° C. under a pressure of 10 to 50 Pa. The amorphous silicon layer is in general formed by CVD technique at a relatively low temperature such as 450° to 500° C. under a pressure of 10 to 50 Pa. Preferably, these polysilicon layer or amorphous silicon layer are 100 to 200 Å in thickness.
In next step (c), side walls are formed. They are formed in a manner that SiO2 is first deposited by LPCVD technique to entirely cover the amorphous silicon layer or polysilicon layer and then etched.
A dry etching method is used and particularly, RIE method is available which uses positive ions (for example CF3 + etc.) generated by applying high-frequency power to a carbon floride gas such as CF4, C2 F6, CHF3 or the like under vacuum to cause it to discharge.
After this RIE method, a HF treatment may be carried out for example in order to etch the edge part of the side wall. Subsequently, ions such as AS+, P+ or the like are vertically implanted to the Si substrate.
In next step (d), first, the side walls are removed by a HF treatment to make the device stress-free. Thereafter, a heat treatment is conducted for the purpose of forming in the Si substrate a diffusion region of the implanted ions. This suitable heat treatment is for example that at a medium temperature of 800° to 850° C. Sequentially the polysilicon layer or amorphous silicon layer is removed by etching. a dry etching method is used, and particularly, RIE method having a strong isotropic property which uses CCL4, SF6 or the like is available. An interlayer insulator is then stacked on the entire surface. The interlayer insulator may comprise a single BPSG layer or a stacked layer of NSG and BPSG in this order.
The heat treatment at a high temperature, for example at 900° to 950° C. is then performed to planarise the interlayer insulator and to complete the formation of the diffusion regions.
FIG. 1 (a)-(d) schematically illustrates fabrication steps of a semiconductor device according to a method for fabricating a semiconductor device of the invention;
FIG. 2 (a)-(c) schematically illustrates fabrication steps of a semiconductor device according to a conventional method for fabricating a semiconductor device.
The present invention will be more fully described by way of the following Examples with reference to the drawings. The Examples are merely examples and are not intended to limit the invention.
As shown in FIG. 1(a), a gate electrode 3 is formed on a Si substrate 1 by CVD technique with a gate oxide sandwiched therebetween. A small amount of SiO2 existing on the substrate 1 is then removed with hydrofluoric acid.
Next, as shown in FIG. 1(b), the overall surface of the Si substrate 1 and the gate electrode 3 undergoes thermal oxidation to form a SiO2 insulation film 4 of about 50-100 Å thick. On the film 4 is deposited a polysilicon layer 5 to about 100-200 Å thick by a CVD technique using Si2 H6 at 620° C. under 20 Pa.
In turn, as shown in FIG. 1(c), SiO2 is deposited by CVD technique and etched by RIE method using CF4 with optional HF cleaning to form side walls 6 on both sides of the gate electrode portion including the SiO2 insulation film 4 and the polysilicon layer 5. Subsequently, As+ ions are implanted (indicated by an arrow 7) at an acceleration energy of 60-80 KeV and a dose of 5×1015 with use of the gate electrode portion and side walls 6 as a mask.
Thereafter, the side walls are removed by a hydrofluoric acid treatment to make the device stress-free, then a heat treatment at 800°-850° C. is conducted to form a diffusinon region 8, followed by removal of the polysilicon layer 5 by RIE method using CCl4, as shown in FIG. (d). A BPSG layer is deposited over the entire surface of the device by a common technique, and a heat treatment at 900°-950° C. is conducted to planarize the BPSG layer, followed by forming a contact hole and metallic wiring. Thus, a semiconductor device is completed.
As shown in FIG. 1(a), a gate electrode 3 is first formed on a Si substrate 1 by the same technique as that in Example 1 with a gate oxide sandwiched therebetween. A small amount of SiO2 existing on the substrate 1 is then removed with hydrofluoric acid.
Next, as shown in FIG. 1(b), the overall surface of the Si substrate 1 and the gate electrode 3 undergoes thermal oxidation to form a SiO2 insulation film 4 of about 50-100 Å thick. On the film 4 is deposited an amorphous silicon layer 5' to about 100-200 Å thick by a CVD technique using Si2 H6 at 460° C. under 20 Pa.
In turn, as shown in FIG. 1(c), SiO2 is deposited by CVD technique and etched by RIE method using CF4 with optional HF treatment to form side walls 6 on both sides of the gate electrode portion including the SiO2 film 4 and the amorphous silicon layer 5'. Subsequently, As+ ions are implanted (indicated by an arrow 7) at an acceleration energy of 60-80 KeV and a dose of 5×1015 with use of the gate electrode portion and side walls 6 as a mask.
Thereafter, the side walls are removed by a HF treatment to make the device stress-free, then a heat treatment at 800°-850° C. is conducted to diffuse the implanted ions, followed by removal of the amorphous silicon layer 5' by RIE method using CCl4, as shown in FIG. (d). NSG layer and a BPSG layer are deposited in turn over the entire surface of the device by a common technique, and a heat treatment at 900°-950° C. is conducted to planarize the above layers, followed by forming a contact hole and metallic wiring. Thus, a semiconductor device is completed.
According to the present invention, formation of the polysilicon or amorphous silicon layer over the SiO2 insulation film covering the Si substrate makes it possible to materially reduce the amount of oxygen of the SiO2 insulation film to possibly be injected into the Si substrate as ions are implanted. Hence, the diffusion layer formed after the heat treatment has significantly reduced crystalline defects. Furthermore, the polysilicon or amorphous silicon layer blocks the etching for making side-walls, resulting in reduced variation in thickness of the SiO2 insulation film and polysilicon or amorphous silicon layer. This turns out to be facilitated control of film thickness and decreased defect density in the diffusion layer. In addition, the amorphous silicon layer is substantially equivalent to the SiO2 insulation film in injection coefficient, leading to uniform ion implantation. This results in an improved semiconductor device of reduced leakage of current, sufficient resistance against junction stress, enhanced reliability and increased yield.
Claims (14)
1. A method for fabricating a semiconductor device, comprising the steps of:
(a) forming a gate electrode on a semiconductor silicon substrate with a gate oxide interposed therebetween;
(b) depositing an insulation film to entirely cover the substrate and the gate electrode, followed by depositing a polysilicon or amorphous silicon layer on the insulation film;
(c) forming side walls of SiO2 on lateral sides of the gate electrode covered with the insulation film and the polysilicon or amorphous silicon layer, followed by ion implantation; and then
(d) subjecting the substrate to a heat treatment at a first temperature for forming a diffusion region after removal of the side walls, stacking an interlayer insulator over the substrate including the gate electrode after removal of the polysilicon or amorphous silicon layer, and then subjecting the substrate to a heat treatment at a second temperature higher than the first temperature for planarizing the interlayer insulator.
2. A method according to claim 1 wherein the insulation film is a SiO2 film.
3. A method according to claim 1 wherein the interlayer insulator comprises a single BPSG layer or a stacked layer of NSG or BPSG.
4. A method according to claim 1 wherein a heat treatment at the first temperature is conducted at 800° to 850° C.
5. A method according to claim 1 wherein a heat treatment at the second temperature is conducted at 900° to 950 ° C.
6. A method for fabricating a semiconductor device, comprising:
forming a gate electrode on a semiconductor silicon substrate with a gate oxide interposed therebetween;
depositing an insulation film over the substrate and gate electrode;
depositing a polysilicon or amorphous silicon layer on the insulation film;
forming sidewalls of SiO2 on lateral sides of the insulation covered gate electrode and the polysilicon or amorphous silicon layer;
implanting ions into the substrate using the sidewalls and gate electrode as a mask;
removing the sidewalls;
heating the substrate to a first temperature;
removing the polysilicon or amorphous silicon layer;
depositing at least one layer of insulation over the surface of the device; and
heating the substrate at a second temperature higher than the first temperature.
7. A method according to claim 6 wherein the first temperature is sufficient to diffuse the implanted ions in the semiconductor silicon substrate.
8. A method according to claim 7 wherein the second temperature is sufficient to planarize the at least one layer of insulation.
9. A method according to claim 6 wherein the insulation film is a SiO2 film.
10. A method according to claim 6 wherein the at least one layer of insulation includes a single BPSG layer or a stacked layer of NSG and BPSG.
11. A method according to claim 6 wherein the first temperature is in the range of 800° to 850° C.
12. A method according to claim 6 wherein the second temperature is in the range of 900° to 950° C.
13. A method according to claim 6 wherein ions are implanted at an energy in the range of 60-80 KeV.
14. A method according to claim 6 wherein the polysilicon or amorphous silicon layer reduces the amount of oxygen from the insulation film that is injected into the silicon substrate during ion implantation to reduce crystalline defects therein.
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3758591 | 1991-03-04 | ||
JP3-037585 | 1991-03-04 | ||
JP3-120805 | 1991-05-27 | ||
JP12080591 | 1991-05-27 | ||
JP4017754A JP2994128B2 (en) | 1991-03-04 | 1992-02-03 | Method for manufacturing semiconductor device |
JP4-017754 | 1992-02-03 |
Publications (1)
Publication Number | Publication Date |
---|---|
US5183770A true US5183770A (en) | 1993-02-02 |
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Application Number | Title | Priority Date | Filing Date |
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US07/842,515 Expired - Lifetime US5183770A (en) | 1991-03-04 | 1992-02-27 | Semiconductor device |
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JP (1) | JP2994128B2 (en) |
Cited By (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5322810A (en) * | 1990-07-03 | 1994-06-21 | Sharp Kabushiki Kaisha | Method for manufacturing a semiconductor device |
US5420079A (en) * | 1990-02-20 | 1995-05-30 | Sharp Kabushiki Kaisha | Process for producing semiconductor device comprising two step annealing treatment |
US5501995A (en) * | 1993-12-17 | 1996-03-26 | Samsung Electronics Co., Ltd. | Method for manufacturing a gate electrode of a MOS transistor |
US5573965A (en) * | 1991-03-27 | 1996-11-12 | Lucent Technologies Inc. | Method of fabricating semiconductor devices and integrated circuits using sidewall spacer technology |
US5702972A (en) * | 1997-01-27 | 1997-12-30 | Taiwan Semiconductor Manufacturing Company Ltd. | Method of fabricating MOSFET devices |
US5783475A (en) * | 1995-11-13 | 1998-07-21 | Motorola, Inc. | Method of forming a spacer |
US5804499A (en) * | 1996-05-03 | 1998-09-08 | Siemens Aktiengesellschaft | Prevention of abnormal WSix oxidation by in-situ amorphous silicon deposition |
WO1998053491A2 (en) * | 1997-05-23 | 1998-11-26 | Koninklijke Philips Electronics N.V. | Manufacture of a semiconductor device with a mos transistor having an ldd structure |
US5915199A (en) * | 1998-06-04 | 1999-06-22 | Sharp Microelectronics Technology, Inc. | Method for manufacturing a CMOS self-aligned strapped interconnection |
US6078073A (en) * | 1996-06-19 | 2000-06-20 | Kabushiki Kaisha Toshiba | Semiconductor apparatus formed by SAC (self-aligned contact) method and manufacturing method therefor |
GB2314676B (en) * | 1996-06-24 | 2001-04-18 | Hyundai Electronics Ind | Method for forming shallow junction of a semiconductor device |
US20030075734A1 (en) * | 2001-10-19 | 2003-04-24 | Yoon-Soo Chun | Methods of manufacturing a semiconductor device having increased gaps between gates and semiconductor devices manufactured thereby |
US20040147070A1 (en) * | 2003-01-24 | 2004-07-29 | National Chiao-Tung University | Ultra-shallow junction formation for nano MOS devices using amorphous-si capping layer |
US20050118802A1 (en) * | 2003-12-02 | 2005-06-02 | Chang-Sheng Tsao | Method for implementing poly pre-doping in deep sub-micron process |
US7473968B2 (en) | 1999-01-11 | 2009-01-06 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device including a thin film transistor and a storage capacitor |
US7553732B1 (en) | 2005-06-13 | 2009-06-30 | Advanced Micro Devices, Inc. | Integration scheme for constrained SEG growth on poly during raised S/D processing |
US7572705B1 (en) | 2005-09-21 | 2009-08-11 | Advanced Micro Devices, Inc. | Semiconductor device and method of manufacturing a semiconductor device |
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US4642878A (en) * | 1984-08-28 | 1987-02-17 | Kabushiki Kaisha Toshiba | Method of making MOS device by sequentially depositing an oxidizable layer and a masking second layer over gated device regions |
US5087582A (en) * | 1988-08-24 | 1992-02-11 | Inmos Limited | Mosfet and fabrication method |
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JPS62120082A (en) * | 1985-11-20 | 1987-06-01 | Toshiba Corp | Semiconductor device and manufacture thereof |
JPS63314868A (en) * | 1987-10-03 | 1988-12-22 | Nec Corp | Manufacture of mos semiconductor device |
-
1992
- 1992-02-03 JP JP4017754A patent/JP2994128B2/en not_active Expired - Fee Related
- 1992-02-27 US US07/842,515 patent/US5183770A/en not_active Expired - Lifetime
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US4642878A (en) * | 1984-08-28 | 1987-02-17 | Kabushiki Kaisha Toshiba | Method of making MOS device by sequentially depositing an oxidizable layer and a masking second layer over gated device regions |
US5087582A (en) * | 1988-08-24 | 1992-02-11 | Inmos Limited | Mosfet and fabrication method |
Non-Patent Citations (2)
Title |
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Cited By (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5420079A (en) * | 1990-02-20 | 1995-05-30 | Sharp Kabushiki Kaisha | Process for producing semiconductor device comprising two step annealing treatment |
US5322810A (en) * | 1990-07-03 | 1994-06-21 | Sharp Kabushiki Kaisha | Method for manufacturing a semiconductor device |
US5573965A (en) * | 1991-03-27 | 1996-11-12 | Lucent Technologies Inc. | Method of fabricating semiconductor devices and integrated circuits using sidewall spacer technology |
US5501995A (en) * | 1993-12-17 | 1996-03-26 | Samsung Electronics Co., Ltd. | Method for manufacturing a gate electrode of a MOS transistor |
US5783475A (en) * | 1995-11-13 | 1998-07-21 | Motorola, Inc. | Method of forming a spacer |
US5804499A (en) * | 1996-05-03 | 1998-09-08 | Siemens Aktiengesellschaft | Prevention of abnormal WSix oxidation by in-situ amorphous silicon deposition |
US6483138B1 (en) | 1996-06-19 | 2002-11-19 | Kabushiki Kaisha Toshiba | Semiconductor apparatus formed by SAC (self-aligned contact) |
US6078073A (en) * | 1996-06-19 | 2000-06-20 | Kabushiki Kaisha Toshiba | Semiconductor apparatus formed by SAC (self-aligned contact) method and manufacturing method therefor |
GB2314676B (en) * | 1996-06-24 | 2001-04-18 | Hyundai Electronics Ind | Method for forming shallow junction of a semiconductor device |
US5702972A (en) * | 1997-01-27 | 1997-12-30 | Taiwan Semiconductor Manufacturing Company Ltd. | Method of fabricating MOSFET devices |
WO1998053491A2 (en) * | 1997-05-23 | 1998-11-26 | Koninklijke Philips Electronics N.V. | Manufacture of a semiconductor device with a mos transistor having an ldd structure |
WO1998053491A3 (en) * | 1997-05-23 | 1999-02-25 | Koninkl Philips Electronics Nv | Manufacture of a semiconductor device with a mos transistor having an ldd structure |
US5915199A (en) * | 1998-06-04 | 1999-06-22 | Sharp Microelectronics Technology, Inc. | Method for manufacturing a CMOS self-aligned strapped interconnection |
US7473968B2 (en) | 1999-01-11 | 2009-01-06 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device including a thin film transistor and a storage capacitor |
US6911740B2 (en) | 2001-10-19 | 2005-06-28 | Samsung Electronics Co., Ltd. | Semiconductor device having increased gaps between gates |
US20040207099A1 (en) * | 2001-10-19 | 2004-10-21 | Yoon-Soo Chun | Semiconductor device having increased gaps between gates |
US6852581B2 (en) | 2001-10-19 | 2005-02-08 | Samsung Electronics Co., Ltd. | Methods of manufacturing a semiconductor device having increased gaps between gates |
KR100416607B1 (en) * | 2001-10-19 | 2004-02-05 | 삼성전자주식회사 | Semiconductor device including transistor and manufacturing methode thereof |
US20030075734A1 (en) * | 2001-10-19 | 2003-04-24 | Yoon-Soo Chun | Methods of manufacturing a semiconductor device having increased gaps between gates and semiconductor devices manufactured thereby |
US20040147070A1 (en) * | 2003-01-24 | 2004-07-29 | National Chiao-Tung University | Ultra-shallow junction formation for nano MOS devices using amorphous-si capping layer |
US20050118802A1 (en) * | 2003-12-02 | 2005-06-02 | Chang-Sheng Tsao | Method for implementing poly pre-doping in deep sub-micron process |
US7553732B1 (en) | 2005-06-13 | 2009-06-30 | Advanced Micro Devices, Inc. | Integration scheme for constrained SEG growth on poly during raised S/D processing |
US7572705B1 (en) | 2005-09-21 | 2009-08-11 | Advanced Micro Devices, Inc. | Semiconductor device and method of manufacturing a semiconductor device |
US20090267152A1 (en) * | 2005-09-21 | 2009-10-29 | Advanced Micro Devices, Inc. | Semiconductor device and method of manufacturing a semiconductor device |
US7910996B2 (en) | 2005-09-21 | 2011-03-22 | Globalfoundries Inc. | Semiconductor device and method of manufacturing a semiconductor device |
Also Published As
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JPH0574803A (en) | 1993-03-26 |
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