US5200361A - Process for preparing a semiconductor device using hydrogen fluoride and nitrogen to remove deposits - Google Patents

Process for preparing a semiconductor device using hydrogen fluoride and nitrogen to remove deposits Download PDF

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US5200361A
US5200361A US07/772,869 US77286991A US5200361A US 5200361 A US5200361 A US 5200361A US 77286991 A US77286991 A US 77286991A US 5200361 A US5200361 A US 5200361A
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deposits
interlayer dielectric
dielectric film
wiring
hydrogen fluoride
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Shigeo Onishi
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Sharp Corp
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Sharp Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes

Definitions

  • the present invention relates to a process for preparing a semiconductor device and, more specifically, to a process for forming a via-hole in an interlayer dielectric film provided in a multilayered metal wiring.
  • via-holes on a semiconductor substrate which are required to a multilayered metal wiring are formed by a reactive ion etching using, for example, SF 6 gas.
  • the aluminum or aluminum alloy recoils to form deposits (for example, AlF 3 and Al 2 O 3 ) in the via-hole. These deposits have insulating properties and thus can cause a defective conduction between the first and second wirings.
  • the deposits have been removed by so-called wet etching method using hydrofluoric acid aqueous solution.
  • Such a wet etching method may often etch too much interlayer-dielectric material existing around the deposits. Because hydrofluoric acid is hard to penetrate into the interface of the deposits and the interlayer dielectric film, and thus the interlayer-dielectric film material around the deposits must be much more etched than necessary (refer to FIG. 3). Therefore, the via-hole becomes far larger in diameter than optimal.
  • the present invention is accomplished in view of the abovementioned problem, and an object thereof is to provide a process for preparing a semiconductor device which is formed with via-holes such as to have an optimal diameter for assuring electrical characteristics thereof.
  • a process for preparing a semiconductor device comprising the steps of forming a lower wiring of aluminum or an aluminum alloy on a semiconductor substrate, coating said lower wiring with an interlayer dielectric film, forming via-holes in said interlayer dielectric film through a patterned resist by a reactive ion etching method, removing deposits produced by said method in said via-holes and a portion of said interlayer dielectric film around said deposits by means of hydrogen fluoride gas and nitrogen gas in the presence or absence of water vapor, and then forming an upper wiring on said interlayer dielectric film.
  • the main feature of the invention resides in the use of a mixed gas of hydrogen fluoride and nitrogen in the presence or absence of water vapor for removing unnecessary deposits remaining in a via-hole.
  • a mixed gas of hydrogen fluoride and nitrogen in the presence or absence of water vapor for removing unnecessary deposits remaining in a via-hole.
  • FIGS. 1a-1e are explanatory view illustrating a process of Example 1.
  • FIG. 2 is a schematic diagram illustrating a via-hole formed by processes of Examples 1 and 2.
  • FIG. 3 is a schematic diagram illustrating a via-hole formed by a conventional process.
  • FIG. 4 is a schematic diagram illustrating a state of a via-hole prior to subjecting to a process of the invention.
  • semiconductor substrate is meant herein by a single-crystal silicon substrate injected or not injected with impurities, and other known substrates.
  • the wiring has a multilayered structure of two or more layers.
  • the aluminum alloy used in the invention for the wiring may contain, for example, 1% of silicon. Any aluminum alloy which is conventionally used for wiring may also be usable in the invention.
  • the interlayer dielectric film of the invention is an SiO 2 film formed by a plasma CVD method to a thickness (d) of preferably 0.5-1.5 ⁇ m, more preferably about 1 ⁇ m which however is not specifically limited.
  • the interlayer dielectric film may include a so-called PSG film which is a SiO 2 film containing phosphorus (P) as impurity formed by CVD method, and a so-called BPSG film being an SiO 2 film containing boron (B) and phosphorus (P) as impurities formed by CVD method.
  • the via-hole is formed by Reactive Ion Etching (RIE) method through a patterned resist.
  • the patterned resist can be formed by a known method, and is used for masking an overall surface of the interlayer dielectric film except an limited area thereof to be etched by RIE method to form the via-hole.
  • the RIE method and the patterned resist enable to form in the interlayer dielectric film a little tapered and vertically extending via-hole 3 of which diameter is, for example, as microscopic as 0.8 ⁇ m (refer to FIG. 4).
  • SF 6 gas or a mixed gas of CF 4 and H 2 is a mixed gas of CF 4 and H 2 .
  • another mixed gas containing fluorine may be usable.
  • the flow rate of SF 6 is preferably 10 -2- 10 -1 l/min.
  • the etching temperature is preferably 20-25° C.
  • the RIE method is used for forming in the interlayer dielectric film the via-hole for electrically connecting the lower wiring with the upper wiring, and thus the interlayer is etched until the wiring has been exposed, entailing the etching of a top surface of the lower wiring.
  • This etching of the top surface of the lower wiring produces an aluminum halide such as AlF 3 resulted from a reaction of ionized etching gas (halide ion such as F - ) and Al constituting the lower wiring, and further an aluminum oxide such as Al 2 O 3 as deposits in the via-hole.
  • the via-hole is substantially formed, however, the unnecessary deposits are also formed by recoil from the aluminum or aluminum alloy of the lower wiring in etching.
  • a minimal amount of the interlayer dielectric film adjacent the deposits is removed together with the deposits.
  • the semiconductor device prior to or after the removal of the patterned resist the semiconductor device is placed under a mixed ga of hydrogen fluoride and nitrogen in the presence or absence of water vapor, this process being so-called HF gas etching, whereby the deposits as well as a minimal amount of the interlayer dielectric film adjacent the deposits can be removed.
  • a ratio of hydrogen fluoride to nitrogen is suitably 0.1-20 wt.%, preferably 1.0-5.0 wt.%, and a ratio of water vapor to nitrogen is preferably 0.01-1.0 wt.%.
  • a ratio of hydrogen fluoride to nitrogen is suitably 0.1-20 wt.%, preferably 1.0-5.0 wt.%.
  • Etching time by means of the mixed gas for removing the deposits together with the interlayer dielectric film existing therearound can be properly decided on the basis of the concentration of the mixed gas, for example, in the case of the mixed gas having 0.1 wt.% of H 2 O (water vapor) and 1.0 wt.% of HF, the preferred etching time is 5-20 sec., as well in the case of the mixed gas of hydrogen fluoride and nitrogen having 1.0 wt.% of HF, the preferred etching time is also 5-20 sec. In both of the above cases etching time of longer than 60 sec. is not suitable because the lower wiring exposing in the bottom portion of the via-hole is etched too much, whereas etching time of shorter than 2 sec. is also unsuitable because the deposits cannot be completely removed. This etching may be carried out prior to the removal of the resist pattern, but preferable is after the removal thereof.
  • the above two mixed gases can easily be inserted into the interface between the deposits and the interlayer dielectric film, thereby enabling to remove the deposits with etching a far less amount of the interlayer dielectric film adjacent the deposits than conventional methods.
  • the thickness of the interlayer dielectric film to be removed is specifically described later.
  • the deposits in the bottom portion of the via-hole can be peeled off from the lower wiring surface in cooperation with the etching of the deposits formed on the wall of the via-hole together with the interlayer dielectric film adjacent thereto.
  • all the deposits and a small amount of the interlayer dielectric film are etched but remain in the via-hole as residue.
  • the residue is then sucked and removed by a given method such as an ultrasonic cleaning to form a via-hole free from deposits, thereby preventing a conduction defect between the lower wiring and the upper wiring which is to be formed thereafter and also preventing increase in via-hole resistance caused by the deposits.
  • FIG. 4 illustrates a via-hole formed vertically in an interlayer dielectric film with little tapered wall.
  • the diameter K of the via-hole is 0.8 ⁇ m
  • the maximal thickness D of the deposits 4 is 0.1 ⁇ m
  • the thickness d of the SiO 2 film 2 is 1.0 ⁇ m.
  • the decrease ⁇ d in the thickness d of the SiO 2 film 2 was 0.05 ⁇ m as shown in FIG. 2.
  • the via-hole 3 was tapered with its uppermost portion diameter K 1 and lowermost portion diameter K 2 (K 2 ⁇ K 1 ), the increase ⁇ K 1 in the uppermost portion diameter K 1 was 0.1 ⁇ m, whereas the increase ⁇ K 2 in the lowermost portion diameter K 2 was 0.05 ⁇ m.
  • the decease in the thickness d of the SiO 2 is 0.18-0.22 ⁇ m
  • the increase in the uppermost portion diameter K 1 is 0.36-0.44 ⁇ m
  • the increase in the lowermost portion diameter K 2 is 0.18-0.22 ⁇ m.
  • the patterned resist is removed if necessary and an Al or Al alloy film as the upper wiring is formed on the SiO 2 film and connects to the lower wiring through the via-hole to form a multilayered wiring.
  • a resist film 12 patterned resist
  • the area R of the SiO 2 film 2 was opened by a reactive ion etching method using a mixed gas of CF 4 and H 2 or SF 6 gas as an etching gas to substantially form a via-hole 3 having a vertical wall with little taper as shown in FIG. 1(b).
  • a portion of the top surface of the first Al alloy wiring 1 is etched, and thus deposits 4 considered to be reaction products of Al and the etching gas were adhered to the inside of the via-hole 3.
  • the resist film 12 was removed as shown in FIG. 1(c).
  • the thus treated substrate 11 is placed for 10 sec. in a chamber filled with a mixed gas of water vapor and hydrogen fluoride diluted with nitrogen to remove the deposits 4 together with SiO 2 adjacent the interface 13 (refer to FIG. 4) between the deposits 4 and the SiO 2 film 2 as shown in FIG. 1 (d).
  • the above mixed gas can be produced, for example, in a manner such that N 2 gas is introduced at 3 ⁇ /min. into a water bath to generate water vapor with which 50 cc of hydrogen fluoride and N 2 gas then are mixed. The thus obtained mixed gas is introduced into the chamber.
  • the thus treated silicon substrate having the via-hole 3 was laminated with an Al alloy film to form a second Al alloy wiring 5 as shown in FIG. 1(e), and thus the first and second wirings were in contact with each other through the via-hole 3, whereby a double-layered wiring was completed.
  • FIG. 3 illustrates the via-hole having thus treated, and data thereof is shown in Table 2.
  • the process of the present invention makes it possible to remarkably reduce the amount of SiO 2 to be removed comparing with a conventional method.
  • a semiconductor device having a double-layered wiring was prepared in the same manner as in Example 1 except that a mixed gas used was a mixed gas of hydrogen fluoride and nitrogen, and the treating time with this mixed gas was 10 sec.
  • the above mixed gas can be produced, for example, in a manner such that a hydrofluoric acid is vaporized by introducing thereinto N 2 gas at a flow rate of 2 l/min., and the resulting vapor is diluted with N 2 gas at a rate of 4 l/min.
  • the obtained mixed gas is introduced into a chamber of 25° C.
  • This example also formed the via-hole 3 as shown in FIG. 2, and data thereof is shown in Table 3.
  • Table 3 reveals that the process of the present invention is far superior to the conventional one.
  • unnecessary deposits which are produced in a via-hole when the via-hole is formed by using a reactive ion etching to electrically connect between a multilayered wiring, can be removed together with a minimal amount of an interlayer dielectric film to be inevitably removed. Further, the present invention can prevent a contact portion existing between an upper and lower wirings of Al or an Al alloy from breaking, thereby enabling to provide a semiconductor device of multilayered wiring having assured electric properties.

Abstract

A process for preparing a semiconductor device includes the steps of forming a lower wiring of aluminum or an aluminum alloy on a semiconductor substrate, coating said lower wiring with an interlayer dielectric film, forming via-holes in said interlayer dielectric film through a patterned resist by a reactive ion etching method, removing deposits produced by said method in said via-holes and a portion of said interlayer dielectric film around said deposits by means of hydrogen fluoride gas and nitrogen gas in the presence or absence of water vapor, and then forming an upper wiring on said interlayer dielectric film.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for preparing a semiconductor device and, more specifically, to a process for forming a via-hole in an interlayer dielectric film provided in a multilayered metal wiring.
2. Prior Art
Conventionally, via-holes on a semiconductor substrate which are required to a multilayered metal wiring are formed by a reactive ion etching using, for example, SF6 gas. In this case, if aluminum or an aluminum alloy is used as a lower layer of the metal wiring (first wiring), the aluminum or aluminum alloy recoils to form deposits (for example, AlF3 and Al2 O3) in the via-hole. These deposits have insulating properties and thus can cause a defective conduction between the first and second wirings. In a conventional manner the deposits have been removed by so-called wet etching method using hydrofluoric acid aqueous solution.
Such a wet etching method, however, may often etch too much interlayer-dielectric material existing around the deposits. Because hydrofluoric acid is hard to penetrate into the interface of the deposits and the interlayer dielectric film, and thus the interlayer-dielectric film material around the deposits must be much more etched than necessary (refer to FIG. 3). Therefore, the via-hole becomes far larger in diameter than optimal.
The present invention is accomplished in view of the abovementioned problem, and an object thereof is to provide a process for preparing a semiconductor device which is formed with via-holes such as to have an optimal diameter for assuring electrical characteristics thereof.
SUMMARY OF THE INVENTION
According to the present invention, there is provided a process for preparing a semiconductor device comprising the steps of forming a lower wiring of aluminum or an aluminum alloy on a semiconductor substrate, coating said lower wiring with an interlayer dielectric film, forming via-holes in said interlayer dielectric film through a patterned resist by a reactive ion etching method, removing deposits produced by said method in said via-holes and a portion of said interlayer dielectric film around said deposits by means of hydrogen fluoride gas and nitrogen gas in the presence or absence of water vapor, and then forming an upper wiring on said interlayer dielectric film.
The main feature of the invention resides in the use of a mixed gas of hydrogen fluoride and nitrogen in the presence or absence of water vapor for removing unnecessary deposits remaining in a via-hole. The use of such a mixed gas makes it possible to remarkably reduce the amount of an interlayer dielectric film material inevitably removed together with the unnecessary deposits.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. 1a-1e are explanatory view illustrating a process of Example 1.
FIG. 2 is a schematic diagram illustrating a via-hole formed by processes of Examples 1 and 2.
FIG. 3 is a schematic diagram illustrating a via-hole formed by a conventional process.
FIG. 4 is a schematic diagram illustrating a state of a via-hole prior to subjecting to a process of the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Hereinafter, the present invention will be more fully described with reference to the drawings.
The term "semiconductor substrate" is meant herein by a single-crystal silicon substrate injected or not injected with impurities, and other known substrates.
In the present invention the wiring has a multilayered structure of two or more layers. The aluminum alloy used in the invention for the wiring may contain, for example, 1% of silicon. Any aluminum alloy which is conventionally used for wiring may also be usable in the invention.
An example of the interlayer dielectric film of the invention is an SiO2 film formed by a plasma CVD method to a thickness (d) of preferably 0.5-1.5 μm, more preferably about 1 μm which however is not specifically limited. The interlayer dielectric film may include a so-called PSG film which is a SiO2 film containing phosphorus (P) as impurity formed by CVD method, and a so-called BPSG film being an SiO2 film containing boron (B) and phosphorus (P) as impurities formed by CVD method.
The via-hole is formed by Reactive Ion Etching (RIE) method through a patterned resist. The patterned resist can be formed by a known method, and is used for masking an overall surface of the interlayer dielectric film except an limited area thereof to be etched by RIE method to form the via-hole. The RIE method and the patterned resist enable to form in the interlayer dielectric film a little tapered and vertically extending via-hole 3 of which diameter is, for example, as microscopic as 0.8 μm (refer to FIG. 4). In the RIE method often used is SF6 gas or a mixed gas of CF4 and H2. However, another mixed gas containing fluorine may be usable. Known conditions of the RIE method using SF6 gas may be applicable to this invention, for example, the flow rate of SF6 is preferably 10-2- 10-1 l/min., and the etching temperature is preferably 20-25° C.
The RIE method is used for forming in the interlayer dielectric film the via-hole for electrically connecting the lower wiring with the upper wiring, and thus the interlayer is etched until the wiring has been exposed, entailing the etching of a top surface of the lower wiring. This etching of the top surface of the lower wiring produces an aluminum halide such as AlF3 resulted from a reaction of ionized etching gas (halide ion such as F-) and Al constituting the lower wiring, and further an aluminum oxide such as Al2 O3 as deposits in the via-hole. Thus, the via-hole is substantially formed, however, the unnecessary deposits are also formed by recoil from the aluminum or aluminum alloy of the lower wiring in etching.
In the present invention a minimal amount of the interlayer dielectric film adjacent the deposits is removed together with the deposits. For this purpose, prior to or after the removal of the patterned resist the semiconductor device is placed under a mixed ga of hydrogen fluoride and nitrogen in the presence or absence of water vapor, this process being so-called HF gas etching, whereby the deposits as well as a minimal amount of the interlayer dielectric film adjacent the deposits can be removed.
In the case of the mixed gas of water vapor, hydrogen fluoride and nitrogen, a ratio of hydrogen fluoride to nitrogen is suitably 0.1-20 wt.%, preferably 1.0-5.0 wt.%, and a ratio of water vapor to nitrogen is preferably 0.01-1.0 wt.%. Whereas in the case of the mixed gas of hydrogen fluoride and nitrogen, a ratio of hydrogen fluoride to nitrogen is suitably 0.1-20 wt.%, preferably 1.0-5.0 wt.%.
Etching time by means of the mixed gas for removing the deposits together with the interlayer dielectric film existing therearound can be properly decided on the basis of the concentration of the mixed gas, for example, in the case of the mixed gas having 0.1 wt.% of H2 O (water vapor) and 1.0 wt.% of HF, the preferred etching time is 5-20 sec., as well in the case of the mixed gas of hydrogen fluoride and nitrogen having 1.0 wt.% of HF, the preferred etching time is also 5-20 sec. In both of the above cases etching time of longer than 60 sec. is not suitable because the lower wiring exposing in the bottom portion of the via-hole is etched too much, whereas etching time of shorter than 2 sec. is also unsuitable because the deposits cannot be completely removed. This etching may be carried out prior to the removal of the resist pattern, but preferable is after the removal thereof.
According to the present invention, the above two mixed gases can easily be inserted into the interface between the deposits and the interlayer dielectric film, thereby enabling to remove the deposits with etching a far less amount of the interlayer dielectric film adjacent the deposits than conventional methods.(The thickness of the interlayer dielectric film to be removed is specifically described later.) In this case, the deposits in the bottom portion of the via-hole can be peeled off from the lower wiring surface in cooperation with the etching of the deposits formed on the wall of the via-hole together with the interlayer dielectric film adjacent thereto. Thus, all the deposits and a small amount of the interlayer dielectric film are etched but remain in the via-hole as residue. The residue is then sucked and removed by a given method such as an ultrasonic cleaning to form a via-hole free from deposits, thereby preventing a conduction defect between the lower wiring and the upper wiring which is to be formed thereafter and also preventing increase in via-hole resistance caused by the deposits.
FIG. 4 illustrates a via-hole formed vertically in an interlayer dielectric film with little tapered wall. In this figure the diameter K of the via-hole is 0.8 μm, the maximal thickness D of the deposits 4 is 0.1 μm, and the thickness d of the SiO2 film 2 is 1.0 μm. In the case of using the mixed gas of water vapor, hydrogen fluoride and nitrogen, the decrease Δd in the thickness d of the SiO2 film 2 was 0.05 μm as shown in FIG. 2. As well, the via-hole 3 was tapered with its uppermost portion diameter K1 and lowermost portion diameter K2 (K2 <K1), the increase ΔK1 in the uppermost portion diameter K1 was 0.1 μm, whereas the increase ΔK2 in the lowermost portion diameter K2 was 0.05 μm. If a conventional method is used, the decease in the thickness d of the SiO2 is 0.18-0.22 μm, the increase in the uppermost portion diameter K1 is 0.36-0.44 μm, and the increase in the lowermost portion diameter K2 is 0.18-0.22 μm. When the values given by the present invention are compared with those given by the conventional method, it is apparent that the SiO2 film 2 is not so removed than necessary.
In the present invention the patterned resist is removed if necessary and an Al or Al alloy film as the upper wiring is formed on the SiO2 film and connects to the lower wiring through the via-hole to form a multilayered wiring.
EXAMPLES Example 1
As shown in FIG. 1(a), on a silicon substrate 11 laminated sequentially were a first Al alloy wiring 1 as the lower wiring, SiO2 film 2 as the interlayer dielectric film, and a resist film 12 (patterned resist) for masking the SiO2 film except the area R destined for a via-hole permitting electric connection between the lower wiring and the upper wiring.
The area R of the SiO2 film 2 was opened by a reactive ion etching method using a mixed gas of CF4 and H2 or SF6 gas as an etching gas to substantially form a via-hole 3 having a vertical wall with little taper as shown in FIG. 1(b). In this case a portion of the top surface of the first Al alloy wiring 1 is etched, and thus deposits 4 considered to be reaction products of Al and the etching gas were adhered to the inside of the via-hole 3. Subsequently the resist film 12 was removed as shown in FIG. 1(c).
Next, the thus treated substrate 11 is placed for 10 sec. in a chamber filled with a mixed gas of water vapor and hydrogen fluoride diluted with nitrogen to remove the deposits 4 together with SiO2 adjacent the interface 13 (refer to FIG. 4) between the deposits 4 and the SiO2 film 2 as shown in FIG. 1 (d). In this case the above mixed gas can be produced, for example, in a manner such that N2 gas is introduced at 3 μ/min. into a water bath to generate water vapor with which 50 cc of hydrogen fluoride and N2 gas then are mixed. The thus obtained mixed gas is introduced into the chamber.
Finally, the thus treated silicon substrate having the via-hole 3 was laminated with an Al alloy film to form a second Al alloy wiring 5 as shown in FIG. 1(e), and thus the first and second wirings were in contact with each other through the via-hole 3, whereby a double-layered wiring was completed.
In this Example, the via-hole 3 from which the deposits 4 have removed is shown in FIG. 2, and data thereof is shown in Table 1.
              TABLE 1                                                     
______________________________________                                    
       Prior to Removal                                                   
                  After the removal                                       
       of Deposition                                                      
                  of Deposition                                           
                               Variation                                  
______________________________________                                    
Thickness of                                                              
         1.0 μm    0.95 μm   -0.05 μm                            
SiO.sub.2 film                     (-Δd)                            
(d)                                                                       
Uppermost                                                                 
         0.8 μm    0.90 μm   +0.10 μm                            
Portion                            (=ΔK.sub.1)                      
Diameter K.sub.1                                                          
Lowermost                                                                 
         0.8 μm    0.85 μm   +0.05 μm                            
Portion                            (=ΔK.sub.2)                      
Diameter K.sub.2                                                          
______________________________________                                    
 *The maximal thickness D of the deposits was 0.1 μm.
The same via-hole as shown in FIG. 4 was treated by a conventional method. FIG. 3 illustrates the via-hole having thus treated, and data thereof is shown in Table 2.
              TABLE 2                                                     
______________________________________                                    
       Prior to Removal                                                   
                  After the removal                                       
       of Deposition                                                      
                  of Deposition                                           
                               Variation                                  
______________________________________                                    
Thickness of                                                              
         1.0 μm    0.8 μm    -0.2 μm                             
SiO.sub.2 film                     (-Δd)                            
(d)                                                                       
Uppermost                                                                 
         0.8 μm    1.2 μm    +0.4 μm                             
Portion                            (=ΔK.sub.1)                      
Diameter K.sub.1                                                          
Lowermost                                                                 
         0.8 μm    1.0 μm    +0.2 μm                             
Portion                            (=ΔK.sub.2)                      
Diameter K.sub.2                                                          
______________________________________
As can be understood from Tables 1 and 2, the process of the present invention makes it possible to remarkably reduce the amount of SiO2 to be removed comparing with a conventional method.
EXAMPLE 2
A semiconductor device having a double-layered wiring was prepared in the same manner as in Example 1 except that a mixed gas used was a mixed gas of hydrogen fluoride and nitrogen, and the treating time with this mixed gas was 10 sec. In this case the above mixed gas can be produced, for example, in a manner such that a hydrofluoric acid is vaporized by introducing thereinto N2 gas at a flow rate of 2 l/min., and the resulting vapor is diluted with N2 gas at a rate of 4 l/min. The obtained mixed gas is introduced into a chamber of 25° C.
This example also formed the via-hole 3 as shown in FIG. 2, and data thereof is shown in Table 3. Table 3 reveals that the process of the present invention is far superior to the conventional one.
              TABLE 3                                                     
______________________________________                                    
       Prior to Removal                                                   
                  After the removal                                       
       of Deposition                                                      
                  of Deposition                                           
                               Variation                                  
______________________________________                                    
Thickness of                                                              
         1.0 μm    0.95 μm   -0.05 μm                            
SiO.sub.2 film                     (-Δd)                            
(d)                                                                       
Uppermost                                                                 
         0.8 μm    0.90 μm   +0.10 μm                            
Portion                            (=ΔK.sub.1)                      
Diameter K.sub.1                                                          
Lowermost                                                                 
         0.8 μm    0.85 μm   +0.05 μm                            
Portion                            (=ΔK.sub.2)                      
Diameter K.sub.2                                                          
______________________________________
As seen in Examples 1 and 2, in course of forming a via-hole for a double-layered wiring of an Al alloy used was the mixed gas of hydrogen fluoride and nitrogen for removing the deposits produced in the via-hole instead of the conventional wet etching using hydrofluoric acid. The mixed gas could easily insert into the interface between the deposits and the interlayer dielectric film, and efficiently remove the deposits with far less amount of the interlayer dielectric film removed than in the conventional manner.
According to the present invention, unnecessary deposits, which are produced in a via-hole when the via-hole is formed by using a reactive ion etching to electrically connect between a multilayered wiring, can be removed together with a minimal amount of an interlayer dielectric film to be inevitably removed. Further, the present invention can prevent a contact portion existing between an upper and lower wirings of Al or an Al alloy from breaking, thereby enabling to provide a semiconductor device of multilayered wiring having assured electric properties.
While only certain preferred embodiments have been described together with the examples, as will be apparent with those familiar with the art, certain changes and modification can be made without departing from the spirit and scope of the invention.

Claims (3)

What is claimed is:
1. A process for preparing a semiconductor device comprising the steps of forming a lower wiring of aluminum or an aluminum alloy on a semiconductor substrate, coating said lower wiring with an interlayer dielectric film, forming via-holes in said interlayer dielectric film through a patterned resist by a reactive ion etching method to expose said lower wiring, removing deposits produced by said method in said via-holes and a portion of said interlayer dielectric film around said deposits by means of a mixed gas of hydrogen fluoride gas and nitrogen gas at a ratio of hydrogen fluoride to nitrogen of 0.1-20 wt.% in the absence of water vapor, and then forming upper wiring on said interlayer dielectric film.
2. A process as claimed in claim 1 wherein the interlayer dielectric film is an SiO2 film formed by a plasma CVD method having a thickness of 0.5-1.5 μm.
3. A process as set forth in claim 1 wherein the reactive ion etching step produces deposits including an aluminum oxide and an aluminum halide, the step of removing the deposits including the step of removing the aluminum oxide and aluminum halide deposits.
US07/772,869 1990-11-15 1991-10-08 Process for preparing a semiconductor device using hydrogen fluoride and nitrogen to remove deposits Expired - Lifetime US5200361A (en)

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US5468340A (en) * 1992-10-09 1995-11-21 Gupta; Subhash Highly selective high aspect ratio oxide etch method and products made by the process
US5641382A (en) * 1996-02-02 1997-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method to remove residue of metal etch
US5744402A (en) * 1994-11-30 1998-04-28 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor devices
US6103633A (en) * 1997-11-24 2000-08-15 Taiwan Semiconductor Manufacturing Company Method for cleaning metal precipitates in semiconductor processes
US6174817B1 (en) * 1998-08-26 2001-01-16 Texas Instruments Incorporated Two step oxide removal for memory cells
US6379576B2 (en) 1997-11-17 2002-04-30 Mattson Technology, Inc. Systems and methods for variable mode plasma enhanced processing of semiconductor wafers
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US5348619A (en) * 1992-09-03 1994-09-20 Texas Instruments Incorporated Metal selective polymer removal
USRE36006E (en) * 1992-09-03 1998-12-22 Fsi International, Inc. Metal selective polymer removal
US5468340A (en) * 1992-10-09 1995-11-21 Gupta; Subhash Highly selective high aspect ratio oxide etch method and products made by the process
US5744402A (en) * 1994-11-30 1998-04-28 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor devices
US5641382A (en) * 1996-02-02 1997-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method to remove residue of metal etch
US6379576B2 (en) 1997-11-17 2002-04-30 Mattson Technology, Inc. Systems and methods for variable mode plasma enhanced processing of semiconductor wafers
US6536449B1 (en) 1997-11-17 2003-03-25 Mattson Technology Inc. Downstream surface cleaning process
US6103633A (en) * 1997-11-24 2000-08-15 Taiwan Semiconductor Manufacturing Company Method for cleaning metal precipitates in semiconductor processes
US6174817B1 (en) * 1998-08-26 2001-01-16 Texas Instruments Incorporated Two step oxide removal for memory cells
US20040084413A1 (en) * 1999-01-27 2004-05-06 Matsushita Electric Industrial Co., Ltd. Etching method
US6805139B1 (en) 1999-10-20 2004-10-19 Mattson Technology, Inc. Systems and methods for photoresist strip and residue treatment in integrated circuit manufacturing
US20050022839A1 (en) * 1999-10-20 2005-02-03 Savas Stephen E. Systems and methods for photoresist strip and residue treatment in integrated circuit manufacturing
US6667244B1 (en) 2000-03-24 2003-12-23 Gerald M. Cox Method for etching sidewall polymer and other residues from the surface of semiconductor devices
US20060137710A1 (en) * 2003-05-27 2006-06-29 Applied Materials, Inc. Method for controlling corrosion of a substrate
US8101025B2 (en) 2003-05-27 2012-01-24 Applied Materials, Inc. Method for controlling corrosion of a substrate
US20070193602A1 (en) * 2004-07-12 2007-08-23 Savas Stephen E Systems and Methods for Photoresist Strip and Residue Treatment in Integrated Circuit Manufacturing
US20070186953A1 (en) * 2004-07-12 2007-08-16 Savas Stephen E Systems and Methods for Photoresist Strip and Residue Treatment in Integrated Circuit Manufacturing
US20060223332A1 (en) * 2005-03-30 2006-10-05 Hynix Semiconductor Inc. Method of manufacturing semiconductor device
EP1745864A3 (en) * 2005-07-18 2007-04-25 DALSA Semiconductor Inc. Method of removing residues formed during the manufacture of MEMS systems
US20070134927A1 (en) * 2005-07-18 2007-06-14 Dalsa Semiconductor Inc. Method for removing residues formed during the manufacture of mems devices
EP1745864A2 (en) 2005-07-18 2007-01-24 DALSA Semiconductor Inc. Method of removing residues formed during the manufacture of MEMS systems
US8071486B2 (en) 2005-07-18 2011-12-06 Teledyne Dalsa Semiconductor Inc. Method for removing residues formed during the manufacture of MEMS devices
US11233023B2 (en) 2019-09-20 2022-01-25 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing semiconductor device

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