US5260610A - Programmable logic element interconnections for programmable logic array integrated circuits - Google Patents
Programmable logic element interconnections for programmable logic array integrated circuits Download PDFInfo
- Publication number
- US5260610A US5260610A US07/754,017 US75401791A US5260610A US 5260610 A US5260610 A US 5260610A US 75401791 A US75401791 A US 75401791A US 5260610 A US5260610 A US 5260610A
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- US
- United States
- Prior art keywords
- programmable logic
- conductors
- logic element
- multiplexer
- programmable
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
- H03K19/1737—Controllable logic circuits using multiplexers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17724—Structural details of logic blocks
- H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17736—Structural details of routing resources
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- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Logic Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
Claims (26)
Priority Applications (28)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/754,017 US5260610A (en) | 1991-09-03 | 1991-09-03 | Programmable logic element interconnections for programmable logic array integrated circuits |
US07/880,942 US5260611A (en) | 1991-09-03 | 1992-05-08 | Programmable logic array having local and long distance conductors |
DE69223010T DE69223010D1 (en) | 1991-09-03 | 1992-08-06 | Programmable, integrated logic arrangement |
EP92307217A EP0530985B1 (en) | 1991-09-03 | 1992-08-06 | Programmable logic array integrated circuits |
EP01112375A EP1134896A2 (en) | 1991-09-03 | 1992-08-06 | Programmable logic array integrated circuits |
EP97106242A EP0786871B1 (en) | 1991-09-03 | 1992-08-06 | Programmable logic array integrated circuits |
JP23486892A JP3488258B2 (en) | 1991-09-03 | 1992-09-02 | Programmable logic array integrated circuit |
US08/038,787 US5371422A (en) | 1991-09-03 | 1993-03-29 | Programmable logic device having multiplexers and demultiplexers randomly connected to global conductors for interconnections between logic elements |
US08/039,944 US5376844A (en) | 1991-09-03 | 1993-03-29 | Programmable logic device with multiplexer-based programmable interconnections |
US08/111,693 US5436575A (en) | 1991-09-03 | 1993-08-25 | Programmable logic array integrated circuits |
US08/245,509 US5550782A (en) | 1991-09-03 | 1994-05-18 | Programmable logic array integrated circuits |
US08/356,516 US5485103A (en) | 1991-09-03 | 1994-12-15 | Programmable logic array with local and global conductors |
US08/655,870 US5668771A (en) | 1991-09-03 | 1996-05-24 | Programmable logic array integrated circuits |
US08/664,919 US5883850A (en) | 1991-09-03 | 1996-06-18 | Programmable logic array integrated circuits |
US08/840,534 US5838628A (en) | 1991-09-03 | 1997-04-22 | Programmable logic array integrated circuits |
US08/847,004 US5828229A (en) | 1991-09-03 | 1997-05-01 | Programmable logic array integrated circuits |
US08/852,015 US5764583A (en) | 1991-09-03 | 1997-05-06 | Programmable logic array integrated circuits |
US08/851,761 US5812479A (en) | 1991-09-03 | 1997-05-06 | Programmable logic array integrated circuits |
US08/851,862 US6028808A (en) | 1991-09-03 | 1997-05-06 | Programmable logic array integrated circuits |
US08/851,858 US5848005A (en) | 1991-09-03 | 1997-05-06 | Programmable logic array integrated circuits |
US09/136,317 US5926036A (en) | 1991-09-03 | 1998-08-19 | Programmable logic array circuits comprising look up table implementation of fast carry adders and counters |
US09/156,036 US6023439A (en) | 1991-09-03 | 1998-09-17 | Programmable logic array integrated circuits |
US09/169,332 US6018490A (en) | 1991-09-03 | 1998-10-09 | Programmable logic array integrated circuits |
US09/179,254 US6064599A (en) | 1991-09-03 | 1998-10-26 | Programmable logic array integrated circuits |
US09/184,383 US6134173A (en) | 1991-09-03 | 1998-11-02 | Programmable logic array integrated circuits |
US09/935,792 US20020130681A1 (en) | 1991-09-03 | 2001-08-22 | Programmable logic array integrated circuits |
US10/356,691 US6897679B2 (en) | 1991-09-03 | 2003-01-31 | Programmable logic array integrated circuits |
US10/372,373 US6759870B2 (en) | 1991-09-03 | 2003-02-20 | Programmable logic array integrated circuits |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/754,017 US5260610A (en) | 1991-09-03 | 1991-09-03 | Programmable logic element interconnections for programmable logic array integrated circuits |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US07/880,942 Continuation-In-Part US5260611A (en) | 1991-09-03 | 1992-05-08 | Programmable logic array having local and long distance conductors |
Related Child Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US07/880,942 Continuation-In-Part US5260611A (en) | 1991-09-03 | 1992-05-08 | Programmable logic array having local and long distance conductors |
US08/039,944 Continuation US5376844A (en) | 1991-09-03 | 1993-03-29 | Programmable logic device with multiplexer-based programmable interconnections |
US08/111,693 Continuation-In-Part US5436575A (en) | 1991-09-03 | 1993-08-25 | Programmable logic array integrated circuits |
Publications (1)
Publication Number | Publication Date |
---|---|
US5260610A true US5260610A (en) | 1993-11-09 |
Family
ID=25033127
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US07/754,017 Expired - Lifetime US5260610A (en) | 1991-09-03 | 1991-09-03 | Programmable logic element interconnections for programmable logic array integrated circuits |
US08/039,944 Expired - Lifetime US5376844A (en) | 1991-09-03 | 1993-03-29 | Programmable logic device with multiplexer-based programmable interconnections |
US08/356,516 Expired - Lifetime US5485103A (en) | 1991-09-03 | 1994-12-15 | Programmable logic array with local and global conductors |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/039,944 Expired - Lifetime US5376844A (en) | 1991-09-03 | 1993-03-29 | Programmable logic device with multiplexer-based programmable interconnections |
US08/356,516 Expired - Lifetime US5485103A (en) | 1991-09-03 | 1994-12-15 | Programmable logic array with local and global conductors |
Country Status (4)
Country | Link |
---|---|
US (3) | US5260610A (en) |
EP (3) | EP1134896A2 (en) |
JP (1) | JP3488258B2 (en) |
DE (1) | DE69223010D1 (en) |
Cited By (220)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5352940A (en) * | 1993-05-27 | 1994-10-04 | Altera Corporation | Ram convertible look-up table based macrocell for PLDs |
US5386156A (en) * | 1993-08-27 | 1995-01-31 | At&T Corp. | Programmable function unit with programmable fast ripple logic |
US5434514A (en) * | 1992-11-19 | 1995-07-18 | Altera Corporation | Programmable logic devices with spare circuits for replacement of defects |
WO1995022205A1 (en) * | 1994-02-15 | 1995-08-17 | Xilinx, Inc. | Tile based architecture for fpga |
US5444394A (en) * | 1993-07-08 | 1995-08-22 | Altera Corporation | PLD with selective inputs from local and global conductors |
US5451887A (en) * | 1986-09-19 | 1995-09-19 | Actel Corporation | Programmable logic module and architecture for field programmable gate array device |
US5455525A (en) * | 1993-12-06 | 1995-10-03 | Intelligent Logic Systems, Inc. | Hierarchically-structured programmable logic array and system for interconnecting logic elements in the logic array |
US5457410A (en) * | 1993-08-03 | 1995-10-10 | Btr, Inc. | Architecture and interconnect scheme for programmable logic circuits |
US5457409A (en) * | 1992-08-03 | 1995-10-10 | Advanced Micro Devices, Inc. | Architecture of a multiple array high density programmable logic device with a plurality of programmable switch matrices |
WO1995030952A1 (en) * | 1994-05-04 | 1995-11-16 | Atmel Corporation | Programmable logic device with regional and universal signal routing |
US5483178A (en) * | 1993-03-29 | 1996-01-09 | Altera Corporation | Programmable logic device with logic block outputs coupled to adjacent logic block output multiplexers |
US5485103A (en) * | 1991-09-03 | 1996-01-16 | Altera Corporation | Programmable logic array with local and global conductors |
US5489857A (en) * | 1992-08-03 | 1996-02-06 | Advanced Micro Devices, Inc. | Flexible synchronous/asynchronous cell structure for a high density programmable logic device |
US5521529A (en) * | 1995-06-02 | 1996-05-28 | Advanced Micro Devices, Inc. | Very high-density complex programmable logic devices with a multi-tiered hierarchical switch matrix and optimized flexible logic allocation |
WO1996016480A1 (en) * | 1994-11-23 | 1996-05-30 | Virtual Machine Works, Inc. | Pipe-lined static router for configurable logic system |
US5523706A (en) * | 1993-07-02 | 1996-06-04 | Altera Corporation | High speed, low power macrocell |
US5525917A (en) * | 1994-12-16 | 1996-06-11 | Altera Corporation | Sense amplifier with feedback and stabilization |
US5537057A (en) * | 1995-02-14 | 1996-07-16 | Altera Corporation | Programmable logic array device with grouped logic regions and three types of conductors |
US5541530A (en) * | 1995-05-17 | 1996-07-30 | Altera Corporation | Programmable logic array integrated circuits with blocks of logic regions grouped into super-blocks |
US5543732A (en) * | 1995-05-17 | 1996-08-06 | Altera Corporation | Programmable logic array devices with interconnect lines of various lengths |
US5543730A (en) * | 1995-05-17 | 1996-08-06 | Altera Corporation | Techniques for programming programmable logic array devices |
US5550782A (en) * | 1991-09-03 | 1996-08-27 | Altera Corporation | Programmable logic array integrated circuits |
US5557217A (en) * | 1991-04-25 | 1996-09-17 | Altera Corporation | High-density erasable programmable logic device architecture using multiplexer interconnections |
US5563592A (en) * | 1993-11-22 | 1996-10-08 | Altera Corporation | Programmable logic device having a compressed configuration file and associated decompression |
US5565793A (en) * | 1995-08-22 | 1996-10-15 | Altera Corporation | Programmable logic array integrated circuit devices with regions of enhanced interconnectivity |
US5570040A (en) * | 1995-03-22 | 1996-10-29 | Altera Corporation | Programmable logic array integrated circuit incorporating a first-in first-out memory |
US5572148A (en) * | 1995-03-22 | 1996-11-05 | Altera Corporation | Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory |
US5581501A (en) * | 1995-08-17 | 1996-12-03 | Altera Corporation | Nonvolatile SRAM cells and cell arrays |
US5592102A (en) * | 1995-10-19 | 1997-01-07 | Altera Corporation | Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices |
US5592106A (en) * | 1995-05-17 | 1997-01-07 | Altera Corporation | Programmable logic array integrated circuits with interconnection conductors of overlapping extent |
US5614840A (en) * | 1995-05-17 | 1997-03-25 | Altera Corporation | Programmable logic array integrated circuits with segmented, selectively connectable, long interconnection conductors |
US5615126A (en) * | 1994-08-24 | 1997-03-25 | Lsi Logic Corporation | High-speed internal interconnection technique for integrated circuits that reduces the number of signal lines through multiplexing |
US5617042A (en) * | 1992-08-03 | 1997-04-01 | Advanced Micro Devices, Inc. | Multiple array programmable logic device with a plurality of programmable switch matrices |
EP0767421A1 (en) | 1992-05-08 | 1997-04-09 | Altera Corporation | Look up table implementation of fast carry for adders and counters |
US5621650A (en) * | 1989-10-30 | 1997-04-15 | Advanced Micro Devices, Inc. | Programmable logic device with internal time-constant multiplexing of signals from external interconnect buses |
US5631576A (en) * | 1995-09-01 | 1997-05-20 | Altera Corporation | Programmable logic array integrated circuit devices with flexible carry chains |
US5644496A (en) * | 1989-08-15 | 1997-07-01 | Advanced Micro Devices, Inc. | Programmable logic device with internal time-constant multiplexing of signals from external interconnect buses |
US5659717A (en) * | 1995-07-31 | 1997-08-19 | Altera Corporation | Methods for partitioning circuits in order to allocate elements among multiple circuit groups |
US5670895A (en) * | 1995-10-19 | 1997-09-23 | Altera Corporation | Routing connections for programmable logic array integrated circuits |
US5672985A (en) * | 1995-12-18 | 1997-09-30 | Altera Corporation | Programmable logic array integrated circuits with carry and/or cascade rings |
US5682107A (en) * | 1994-04-01 | 1997-10-28 | Xilinx, Inc. | FPGA architecture with repeatable tiles including routing matrices and logic matrices |
US5689195A (en) * | 1995-05-17 | 1997-11-18 | Altera Corporation | Programmable logic array integrated circuit devices |
US5691653A (en) * | 1996-01-16 | 1997-11-25 | Altera Corporation | Product term based programmable logic array devices with reduced control memory requirements |
US5694058A (en) * | 1996-03-20 | 1997-12-02 | Altera Corporation | Programmable logic array integrated circuits with improved interconnection conductor utilization |
US5714890A (en) * | 1994-09-26 | 1998-02-03 | Philips Electronics North America Corporation | Programmable logic device with fixed and programmable memory |
US5729495A (en) * | 1995-09-29 | 1998-03-17 | Altera Corporation | Dynamic nonvolatile memory cell |
US5744991A (en) * | 1995-10-16 | 1998-04-28 | Altera Corporation | System for distributing clocks using a delay lock loop in a programmable logic circuit |
US5757207A (en) * | 1995-03-22 | 1998-05-26 | Altera Corporation | Programmable logic array integrated circuit incorporating a first-in first-out memory |
US5761099A (en) * | 1994-11-04 | 1998-06-02 | Altera Corporation | Programmable logic array integrated circuits with enhanced carry routing |
US5764080A (en) * | 1995-08-24 | 1998-06-09 | Altera Corporation | Input/output interface circuitry for programmable logic array integrated circuit devices |
US5767734A (en) * | 1995-12-21 | 1998-06-16 | Altera Corporation | High-voltage pump with initiation scheme |
US5768372A (en) * | 1996-03-13 | 1998-06-16 | Altera Corporation | Method and apparatus for securing programming data of a programmable logic device |
US5771264A (en) * | 1996-08-29 | 1998-06-23 | Altera Corporation | Digital delay lock loop for clock signal frequency multiplication |
US5793246A (en) * | 1995-11-08 | 1998-08-11 | Altera Corporation | High voltage pump scheme incorporating an overlapping clock |
US5796268A (en) * | 1996-10-02 | 1998-08-18 | Kaplinsky; Cecil H. | Programmable logic device with partial switch matrix and bypass mechanism |
US5809281A (en) * | 1993-03-30 | 1998-09-15 | Altera Corporation | Field programmable gate array with high speed SRAM based configurable function block configurable as high performance logic or block of SRAM |
US5815726A (en) * | 1994-11-04 | 1998-09-29 | Altera Corporation | Coarse-grained look-up table architecture |
US5818254A (en) * | 1995-06-02 | 1998-10-06 | Advanced Micro Devices, Inc. | Multi-tiered hierarchical high speed switch matrix structure for very high-density complex programmable logic devices |
US5821773A (en) * | 1995-09-06 | 1998-10-13 | Altera Corporation | Look-up table based logic element with complete permutability of the inputs to the secondary signals |
US5828229A (en) * | 1991-09-03 | 1998-10-27 | Altera Corporation | Programmable logic array integrated circuits |
US5835998A (en) * | 1996-04-04 | 1998-11-10 | Altera Corporation | Logic cell for programmable logic devices |
US5844854A (en) * | 1996-09-18 | 1998-12-01 | Altera Corporation | Programmable logic device with two dimensional memory addressing |
US5850564A (en) * | 1995-05-03 | 1998-12-15 | Btr, Inc, | Scalable multiple level tab oriented interconnect architecture |
US5850365A (en) * | 1994-12-16 | 1998-12-15 | Altera Corporation | Sense amplifier with individually optimized high and low power modes |
US5861760A (en) * | 1991-04-25 | 1999-01-19 | Altera Corporation | Programmable logic device macrocell with improved capability |
US5869979A (en) * | 1996-04-05 | 1999-02-09 | Altera Corporation | Technique for preconditioning I/Os during reconfiguration |
US5872463A (en) * | 1996-04-04 | 1999-02-16 | Altera Corporation | Routing in programmable logic devices using shared distributed programmable logic connectors |
US5880597A (en) * | 1996-09-18 | 1999-03-09 | Altera Corporation | Interleaved interconnect for programmable logic array devices |
US5883526A (en) * | 1997-04-17 | 1999-03-16 | Altera Corporation | Hierarchical interconnect for programmable logic devices |
US5883850A (en) * | 1991-09-03 | 1999-03-16 | Altera Corporation | Programmable logic array integrated circuits |
US5889411A (en) * | 1997-02-26 | 1999-03-30 | Xilinx, Inc. | FPGA having logic element carry chains capable of generating wide XOR functions |
US5894565A (en) * | 1996-05-20 | 1999-04-13 | Atmel Corporation | Field programmable gate array with distributed RAM and increased cell utilization |
US5894228A (en) * | 1996-01-10 | 1999-04-13 | Altera Corporation | Tristate structures for programmable logic devices |
US5900743A (en) * | 1995-05-17 | 1999-05-04 | Altera Corporation | Programmable logic array devices with interconnect lines of various lengths |
US5907248A (en) * | 1997-02-26 | 1999-05-25 | Xilinx, Inc. | FPGA interconnect structure with high-speed high fanout capability |
US5909126A (en) * | 1995-05-17 | 1999-06-01 | Altera Corporation | Programmable logic array integrated circuit devices with interleaved logic array blocks |
US5914904A (en) * | 1996-10-01 | 1999-06-22 | Altera Corporation | Compact electrically erasable memory cells and arrays |
US5920202A (en) * | 1997-02-26 | 1999-07-06 | Xilinx, Inc. | Configurable logic element with ability to evaluate five and six input functions |
US5936425A (en) * | 1995-05-17 | 1999-08-10 | Altera Corporation | Tri-statable input/output circuitry for programmable logic |
US5939790A (en) * | 1996-04-09 | 1999-08-17 | Altera Corporation | Integrated circuit pad structures |
US5939930A (en) * | 1996-04-17 | 1999-08-17 | Xilinx, Inc. | Interconnect structure for FPGA using a multiplexer |
US5942913A (en) * | 1997-03-20 | 1999-08-24 | Xilinx, Inc. | FPGA repeatable interconnect structure with bidirectional and unidirectional interconnect lines |
US5942914A (en) * | 1996-10-25 | 1999-08-24 | Altera Corporation | PLD with split multiplexed inputs from global conductors |
US5949710A (en) * | 1996-04-10 | 1999-09-07 | Altera Corporation | Programmable interconnect junction |
US5959891A (en) * | 1996-08-16 | 1999-09-28 | Altera Corporation | Evaluation of memory cell characteristics |
US5963049A (en) * | 1995-05-17 | 1999-10-05 | Altera Corporation | Programmable logic array integrated circuit architectures |
US5963050A (en) * | 1997-02-26 | 1999-10-05 | Xilinx, Inc. | Configurable logic element with fast feedback paths |
US5970255A (en) * | 1995-10-16 | 1999-10-19 | Altera Corporation | System for coupling programmable logic device to external circuitry which selects a logic standard and uses buffers to modify output and input signals accordingly |
US5977793A (en) * | 1996-10-10 | 1999-11-02 | Altera Corporation | Programmable logic device with hierarchical interconnection resources |
US5977791A (en) * | 1996-04-15 | 1999-11-02 | Altera Corporation | Embedded memory block with FIFO mode for programmable logic device |
US5982195A (en) * | 1997-02-20 | 1999-11-09 | Altera Corporation | Programmable logic device architectures |
US5986465A (en) * | 1996-04-09 | 1999-11-16 | Altera Corporation | Programmable logic integrated circuit architecture incorporating a global shareable expander |
US5998295A (en) * | 1996-04-10 | 1999-12-07 | Altera Corporation | Method of forming a rough region on a substrate |
US5999015A (en) * | 1997-02-20 | 1999-12-07 | Altera Corporation | Logic region resources for programmable logic devices |
US5999016A (en) * | 1996-10-10 | 1999-12-07 | Altera Corporation | Architectures for programmable logic devices |
US6005806A (en) * | 1996-03-14 | 1999-12-21 | Altera Corporation | Nonvolatile configuration cells and cell arrays |
US6018476A (en) * | 1996-09-16 | 2000-01-25 | Altera Corporation | Nonvolatile configuration cells and cell arrays |
US6025737A (en) * | 1996-11-27 | 2000-02-15 | Altera Corporation | Circuitry for a low internal voltage integrated circuit |
US6029236A (en) * | 1997-01-28 | 2000-02-22 | Altera Corporation | Field programmable gate array with high speed SRAM based configurable function block configurable as high performance logic or block of SRAM |
US6028446A (en) * | 1995-06-06 | 2000-02-22 | Advanced Micro Devices, Inc. | Flexible synchronous and asynchronous circuits for a very high density programmable logic device |
US6034547A (en) * | 1996-09-04 | 2000-03-07 | Advantage Logic, Inc. | Method and apparatus for universal program controlled bus |
US6034540A (en) * | 1997-04-08 | 2000-03-07 | Altera Corporation | Programmable logic integrated circuit architecture incorporating a lonely register |
US6034536A (en) * | 1997-02-05 | 2000-03-07 | Altera Corporation | Redundancy circuitry for logic circuits |
US6045252A (en) * | 1996-02-20 | 2000-04-04 | Altera Corporation | Methods for allocating circuit design portions among physical circuit portions |
US6049223A (en) * | 1995-03-22 | 2000-04-11 | Altera Corporation | Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory |
US6051991A (en) * | 1993-08-03 | 2000-04-18 | Btr, Inc. | Architecture and interconnect scheme for programmable logic circuits |
US6052327A (en) * | 1997-10-14 | 2000-04-18 | Altera Corporation | Dual-port programmable logic device variable depth and width memory array |
US6069490A (en) * | 1997-12-02 | 2000-05-30 | Xilinx, Inc. | Routing architecture using a direct connect routing mesh |
US6072332A (en) * | 1997-10-14 | 2000-06-06 | Altera Corporation | Variable depth memories for programmable logic devices |
US6084427A (en) * | 1998-05-19 | 2000-07-04 | Altera Corporation | Programmable logic devices with enhanced multiplexing capabilities |
US6091258A (en) * | 1997-02-05 | 2000-07-18 | Altera Corporation | Redundancy circuitry for logic circuits |
US6097212A (en) * | 1997-10-09 | 2000-08-01 | Lattice Semiconductor Corporation | Variable grain architecture for FPGA integrated circuits |
US6107825A (en) * | 1997-10-16 | 2000-08-22 | Altera Corporation | Input/output circuitry for programmable logic devices |
US6107820A (en) * | 1997-05-23 | 2000-08-22 | Altera Corporation | Redundancy circuitry for programmable logic devices with interleaved input circuits |
US6107822A (en) * | 1996-04-09 | 2000-08-22 | Altera Corporation | Logic element for a programmable logic integrated circuit |
US6107824A (en) * | 1997-10-16 | 2000-08-22 | Altera Corporation | Circuitry and methods for internal interconnection of programmable logic devices |
US6118302A (en) * | 1996-05-28 | 2000-09-12 | Altera Corporation | Interface for low-voltage semiconductor devices |
US6121790A (en) * | 1997-10-16 | 2000-09-19 | Altera Corporation | Programmable logic device with enhanced multiplexing capabilities in interconnect resources |
US6127844A (en) * | 1997-02-20 | 2000-10-03 | Altera Corporation | PCI-compatible programmable logic devices |
US6128692A (en) * | 1994-05-18 | 2000-10-03 | Altera Corporation | Programming and verification address generation for random access memory blocks in programmable logic array integrated circuit devices |
US6128215A (en) * | 1997-08-19 | 2000-10-03 | Altera Corporation | Static random access memory circuits |
US6127843A (en) * | 1997-12-22 | 2000-10-03 | Vantis Corporation | Dual port SRAM memory for run time use in FPGA integrated circuits |
US6130555A (en) * | 1997-10-13 | 2000-10-10 | Altera Corporation | Driver circuitry for programmable logic devices |
US6130551A (en) * | 1998-01-19 | 2000-10-10 | Vantis Corporation | Synthesis-friendly FPGA architecture with variable length and variable timing interconnect |
US6160347A (en) * | 1994-10-17 | 2000-12-12 | Canon Kabushiki Kaisha | Electron source and image forming apparatus as well as method of providing the same with means for maintaining activated state thereof |
US6160420A (en) | 1986-09-19 | 2000-12-12 | Actel Corporation | Programmable interconnect architecture |
US6181162B1 (en) | 1994-04-10 | 2001-01-30 | Altera Corporation | Programmable logic device with highly routable interconnect |
US6185724B1 (en) | 1997-12-02 | 2001-02-06 | Xilinx, Inc. | Template-based simulated annealing move-set that improves FPGA architectural feature utilization |
US6184707B1 (en) | 1998-10-07 | 2001-02-06 | Altera Corporation | Look-up table based logic element with complete permutability of the inputs to the secondary signals |
US6184710B1 (en) | 1997-03-20 | 2001-02-06 | Altera Corporation | Programmable logic array devices with enhanced interconnectivity between adjacent logic regions |
US6184706B1 (en) | 1996-04-05 | 2001-02-06 | Altera Corporation | Logic device architecture and method of operation |
US6191998B1 (en) | 1997-10-16 | 2001-02-20 | Altera Corporation | Programmable logic device memory array circuit having combinable single-port memory arrays |
US6201410B1 (en) | 1997-02-26 | 2001-03-13 | Xilinx, Inc. | Wide logic gate implemented in an FPGA configurable logic element |
US6201404B1 (en) | 1998-07-14 | 2001-03-13 | Altera Corporation | Programmable logic device with redundant circuitry |
US6204689B1 (en) | 1997-02-26 | 2001-03-20 | Xilinx, Inc. | Input/output interconnect circuit for FPGAs |
US6236597B1 (en) | 1996-09-16 | 2001-05-22 | Altera Corporation | Nonvolatile memory cell with multiple gate oxide thicknesses |
US6239612B1 (en) | 1997-08-20 | 2001-05-29 | Altera Corporation | Programmable I/O cells with multiple drivers |
US6255850B1 (en) | 1997-10-28 | 2001-07-03 | Altera Corporation | Integrated circuit with both clamp protection and high impedance protection from input overshoot |
US6265926B1 (en) | 1998-05-27 | 2001-07-24 | Altera Corporation | Programmable PCI overvoltage input clamp |
US6288970B1 (en) | 1997-10-16 | 2001-09-11 | Altera Corporation | Programmable logic device memory array circuit having combinable single-port memory arrays |
US6292018B1 (en) * | 1992-11-05 | 2001-09-18 | Xilinx, Inc. | Configurable cellular array |
US6300793B1 (en) | 1995-05-03 | 2001-10-09 | Btr, Inc. | Scalable multiple level tab oriented interconnect architecture |
US6301694B1 (en) | 1996-09-25 | 2001-10-09 | Altera Corporation | Hierarchical circuit partitioning using sliding windows |
US6300794B1 (en) | 1996-10-10 | 2001-10-09 | Altera Corporation | Programmable logic device with hierarchical interconnection resources |
US6320412B1 (en) | 1999-12-20 | 2001-11-20 | Btr, Inc. C/O Corporate Trust Co. | Architecture and interconnect for programmable logic circuits |
US20010049816A1 (en) * | 1999-12-30 | 2001-12-06 | Adaptive Silicon, Inc. | Multi-scale programmable array |
US6384630B2 (en) | 1996-06-05 | 2002-05-07 | Altera Corporation | Techniques for programming programmable logic array devices |
US6407576B1 (en) | 1999-03-04 | 2002-06-18 | Altera Corporation | Interconnection and input/output resources for programmable logic integrated circuit devices |
US6424567B1 (en) | 1999-07-07 | 2002-07-23 | Philips Electronics North America Corporation | Fast reconfigurable programmable device |
US20020130681A1 (en) * | 1991-09-03 | 2002-09-19 | Cliff Richard G. | Programmable logic array integrated circuits |
US6462578B2 (en) | 1993-08-03 | 2002-10-08 | Btr, Inc. | Architecture and interconnect scheme for programmable logic circuits |
US6467017B1 (en) | 1998-06-23 | 2002-10-15 | Altera Corporation | Programmable logic device having embedded dual-port random access memory configurable as single-port memory |
US6480028B2 (en) | 1998-11-18 | 2002-11-12 | Altera Corporation | Programmable logic device architectures with super-regions having logic regions and memory region |
US6507216B1 (en) | 1998-11-18 | 2003-01-14 | Altera Corporation | Efficient arrangement of interconnection resources on programmable logic devices |
US6531887B2 (en) | 2001-06-01 | 2003-03-11 | Macronix International Co., Ltd. | One cell programmable switch using non-volatile cell |
US6545504B2 (en) | 2001-06-01 | 2003-04-08 | Macronix International Co., Ltd. | Four state programmable interconnect device for bus line and I/O pad |
US6545505B1 (en) * | 1997-09-30 | 2003-04-08 | Cypress Semiconductor Corporation | Hybrid routing architecture for high density complex programmable logic devices |
US6577161B2 (en) | 2001-06-01 | 2003-06-10 | Macronix International Co., Ltd. | One cell programmable switch using non-volatile cell with unidirectional and bidirectional states |
US6594810B1 (en) | 2001-10-04 | 2003-07-15 | M2000 | Reconfigurable integrated circuit with a scalable architecture |
US6624658B2 (en) | 1999-02-04 | 2003-09-23 | Advantage Logic, Inc. | Method and apparatus for universal program controlled bus architecture |
US6657457B1 (en) | 2000-03-15 | 2003-12-02 | Intel Corporation | Data transfer on reconfigurable chip |
US6720796B1 (en) | 2001-05-06 | 2004-04-13 | Altera Corporation | Multiple size memories in a programmable logic device |
US6759870B2 (en) | 1991-09-03 | 2004-07-06 | Altera Corporation | Programmable logic array integrated circuits |
US20040155676A1 (en) * | 2003-02-11 | 2004-08-12 | Sinan Kaptanoglu | Fracturable incomplete look up table for area efficient logic elements |
US6798240B1 (en) | 2003-01-24 | 2004-09-28 | Altera Corporation | Logic circuitry with shared lookup table |
US20040193852A1 (en) * | 2003-03-31 | 2004-09-30 | Johnson Scott D. | Extension adapter |
US20040194048A1 (en) * | 2003-03-31 | 2004-09-30 | Arnold Jeffrey M. | System and method for efficiently mapping heterogeneous objects onto an array of heterogeneous programmable logic resources |
US6803785B1 (en) | 2000-06-12 | 2004-10-12 | Altera Corporation | I/O circuitry shared between processor and programmable logic portions of an integrated circuit |
USRE38651E1 (en) * | 1994-05-18 | 2004-11-09 | Altera Corporation | Variable depth and width memory device |
US20050027944A1 (en) * | 2003-07-29 | 2005-02-03 | Williams Kenneth Mark | Instruction set for efficient bit stream and byte stream I/O |
US6874136B2 (en) | 2002-01-10 | 2005-03-29 | M2000 | Crossbar device with reduced parasitic capacitive loading and usage of crossbar devices in reconfigurable circuits |
US20050073337A1 (en) * | 2003-10-07 | 2005-04-07 | University Of Florida | Method and apparatus for a chaotic computing module |
US6882177B1 (en) | 1996-01-10 | 2005-04-19 | Altera Corporation | Tristate structures for programmable logic devices |
US20050114565A1 (en) * | 2003-03-31 | 2005-05-26 | Stretch, Inc. | Systems and methods for selecting input/output configuration in an integrated circuit |
US20050127944A1 (en) * | 2002-10-24 | 2005-06-16 | Altera Corporation | Versatile logic element and logic array block |
US6943580B2 (en) | 2003-02-10 | 2005-09-13 | Altera Corporation | Fracturable lookup table and logic element |
US20050218928A1 (en) * | 2004-03-30 | 2005-10-06 | Pani Peter M | Scalable non-blocking switching network for programmable logic |
US6961884B1 (en) | 2000-06-12 | 2005-11-01 | Altera Corporation | JTAG mirroring circuitry and methods |
US20060023704A1 (en) * | 2004-07-29 | 2006-02-02 | Pani Peter M | Interconnection fabric using switching networks in hierarchy |
US7030652B1 (en) | 2004-04-23 | 2006-04-18 | Altera Corporation | LUT-based logic element with support for Shannon decomposition and associated method |
US7111110B1 (en) | 2002-12-10 | 2006-09-19 | Altera Corporation | Versatile RAM for programmable logic device |
US20060259747A1 (en) * | 2003-07-29 | 2006-11-16 | Stretch, Inc. | Long instruction word processing with instruction extensions |
US7148722B1 (en) | 1997-02-20 | 2006-12-12 | Altera Corporation | PCI-compatible programmable logic devices |
US7176718B1 (en) | 2005-01-21 | 2007-02-13 | Altera Corporation | Organizations of logic modules in programmable logic devices |
US7185035B1 (en) | 2003-10-23 | 2007-02-27 | Altera Corporation | Arithmetic structures for programmable logic devices |
US20070057693A1 (en) * | 2005-09-13 | 2007-03-15 | M2000 | Reconfigurable circuit with redundant reconfigurable cluster(S) |
US20070118783A1 (en) * | 2005-11-23 | 2007-05-24 | M2000 Inc. | Runtime reconfiguration of reconfigurable circuits |
US7340596B1 (en) | 2000-06-12 | 2008-03-04 | Altera Corporation | Embedded processor with watchdog timer for programmable logic |
US20080150578A1 (en) * | 2006-12-22 | 2008-06-26 | Chaologix, Inc. | Dynamically configurable logic gate using a non-linear element |
USRE40423E1 (en) | 1996-07-29 | 2008-07-08 | Xilinx, Inc. | Multiport RAM with programmable data port configuration |
US7423453B1 (en) | 2006-01-20 | 2008-09-09 | Advantage Logic, Inc. | Efficient integrated circuit layout scheme to implement a scalable switching network used in interconnection fabric |
US7424658B1 (en) | 2002-07-01 | 2008-09-09 | Altera Corporation | Method and apparatus for testing integrated circuits |
US20080218208A1 (en) * | 2007-03-09 | 2008-09-11 | Altera Corporation | Programmable logic device having logic array block interconnect lines that can interconnect logic elements in different logic blocks |
US20080278678A1 (en) * | 2003-10-09 | 2008-11-13 | Howell Thomas A | Eyeglasses with user monitoring |
US7484081B1 (en) | 2000-10-10 | 2009-01-27 | Altera Corporation | Method and apparatus for protecting designs in SRAM-based programmable logic devices |
US7508231B2 (en) | 2007-03-09 | 2009-03-24 | Altera Corporation | Programmable logic device having redundancy with logic element granularity |
US7565388B1 (en) | 2003-11-21 | 2009-07-21 | Altera Corporation | Logic cell supporting addition of three binary words |
US7581081B2 (en) | 2003-03-31 | 2009-08-25 | Stretch, Inc. | Systems and methods for software extensible multi-processing |
US20090256590A1 (en) * | 2008-04-10 | 2009-10-15 | Silicon Storage Technology, Inc. | Storage element for controlling a logic circuit, and a logic device having an array of such storage elements |
US7671625B1 (en) | 2004-03-25 | 2010-03-02 | Altera Corporation | Omnibus logic element |
US7679401B1 (en) * | 2005-12-01 | 2010-03-16 | Tabula, Inc. | User registers implemented with routing circuits in a configurable IC |
US20100095147A1 (en) * | 2005-09-13 | 2010-04-15 | Abound Logic, S.A.S. | Reconfigurable circuit with redundant reconfigurable cluster(s) |
US7705629B1 (en) | 2008-12-03 | 2010-04-27 | Advantage Logic, Inc. | Permutable switching network with enhanced interconnectivity for multicasting signals |
US7714611B1 (en) | 2008-12-03 | 2010-05-11 | Advantage Logic, Inc. | Permutable switching network with enhanced multicasting signals routing for interconnection fabric |
US20100219858A1 (en) * | 2003-10-07 | 2010-09-02 | University Of Florida Research Foundation, Inc. | Logic based on the evolution of nonlinear dynamical systems |
US20100219862A1 (en) * | 2009-02-27 | 2010-09-02 | University Of Florida Research Foundation, Inc. | Reconfigurable and reliable logic circuit elements that exploit nonlinearity and noise |
US7800401B1 (en) | 2003-02-10 | 2010-09-21 | Altera Corporation | Fracturable lookup table and logic element |
US20100318506A1 (en) * | 2003-10-07 | 2010-12-16 | Control Dynamics, Inc. | Non-linear dynamical search engine |
US20100327907A1 (en) * | 2009-06-24 | 2010-12-30 | Ting Benjamin S | Enhanced permutable switching network with multicasting signals for interconnection fabric |
EP2288030A1 (en) | 1999-03-24 | 2011-02-23 | Altera Corporation | I/O cell configuration for multiple I/O standards |
US20110085662A1 (en) * | 2009-10-14 | 2011-04-14 | Chaologix, Inc. | High utilization universal logic array with variable circuit topology and logistic map circuit to realize a variety of logic gates with constant power signatures |
US8001266B1 (en) | 2003-03-31 | 2011-08-16 | Stretch, Inc. | Configuring a multi-processor system |
US8461863B2 (en) | 2011-04-29 | 2013-06-11 | Altera Corporation | Method and apparatus for securing a programmable device using a kill switch |
US8487665B2 (en) | 2001-08-29 | 2013-07-16 | Altera Corporation | Programmable high-speed interface |
US8566616B1 (en) | 2004-09-10 | 2013-10-22 | Altera Corporation | Method and apparatus for protecting designs in SRAM-based programmable logic devices and the like |
US8612772B1 (en) | 2004-09-10 | 2013-12-17 | Altera Corporation | Security core using soft key |
US8627105B2 (en) | 2011-04-29 | 2014-01-07 | Altera Corporation | Method and apparatus for securing programming data of a programmable device |
US8719957B2 (en) | 2011-04-29 | 2014-05-06 | Altera Corporation | Systems and methods for detecting and mitigating programmable logic device tampering |
US8736299B1 (en) | 2011-04-29 | 2014-05-27 | Altera Corporation | Setting security features of programmable logic devices |
US9026873B2 (en) | 2013-07-23 | 2015-05-05 | Altera Coporation | Method and apparatus for securing configuration scan chains of a programmable device |
Families Citing this family (106)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5260611A (en) * | 1991-09-03 | 1993-11-09 | Altera Corporation | Programmable logic array having local and long distance conductors |
US5596742A (en) * | 1993-04-02 | 1997-01-21 | Massachusetts Institute Of Technology | Virtual interconnections for reconfigurable logic systems |
US5761484A (en) * | 1994-04-01 | 1998-06-02 | Massachusetts Institute Of Technology | Virtual interconnections for reconfigurable logic systems |
US5550843A (en) * | 1994-04-01 | 1996-08-27 | Xilinx, Inc. | Programmable scan chain testing structure and method |
US5689686A (en) * | 1994-07-29 | 1997-11-18 | Cypress Semiconductor Corp. | Methods for maximizing routability in a programmable interconnect matrix having less than full connectability |
US5442306A (en) * | 1994-09-09 | 1995-08-15 | At&T Corp. | Field programmable gate array using look-up tables, multiplexers and decoders |
US5530378A (en) * | 1995-04-26 | 1996-06-25 | Xilinx, Inc. | Cross point interconnect structure with reduced area |
US5723984A (en) * | 1996-06-07 | 1998-03-03 | Advanced Micro Devices, Inc. | Field programmable gate array (FPGA) with interconnect encoding |
US5943242A (en) | 1995-11-17 | 1999-08-24 | Pact Gmbh | Dynamically reconfigurable data processing system |
US7266725B2 (en) * | 2001-09-03 | 2007-09-04 | Pact Xpp Technologies Ag | Method for debugging reconfigurable architectures |
US5677638A (en) * | 1996-02-02 | 1997-10-14 | Xilinx, Inc. | High speed tristate bus with multiplexers for selecting bus driver |
US5936424A (en) * | 1996-02-02 | 1999-08-10 | Xilinx, Inc. | High speed bus with tree structure for selecting bus driver |
US6570404B1 (en) | 1996-03-29 | 2003-05-27 | Altera Corporation | High-performance programmable logic architecture |
US5742181A (en) * | 1996-06-04 | 1998-04-21 | Hewlett-Packard Co. | FPGA with hierarchical interconnect structure and hyperlinks |
US6094066A (en) * | 1996-08-03 | 2000-07-25 | Mission Research Corporation | Tiered routing architecture for field programmable gate arrays |
US6005410A (en) * | 1996-12-05 | 1999-12-21 | International Business Machines Corporation | Interconnect structure between heterogeneous core regions in a programmable array |
DE19651075A1 (en) * | 1996-12-09 | 1998-06-10 | Pact Inf Tech Gmbh | Unit for processing numerical and logical operations, for use in processors (CPU's), multi-computer systems, data flow processors (DFP's), digital signal processors (DSP's) or the like |
US6286093B1 (en) * | 1996-12-10 | 2001-09-04 | Logic Express Systems, Inc. | Multi-bus programmable interconnect architecture |
DE19654593A1 (en) | 1996-12-20 | 1998-07-02 | Pact Inf Tech Gmbh | Reconfiguration procedure for programmable blocks at runtime |
DE19654595A1 (en) * | 1996-12-20 | 1998-07-02 | Pact Inf Tech Gmbh | I0 and memory bus system for DFPs as well as building blocks with two- or multi-dimensional programmable cell structures |
US6338106B1 (en) | 1996-12-20 | 2002-01-08 | Pact Gmbh | I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures |
DE19654846A1 (en) | 1996-12-27 | 1998-07-09 | Pact Inf Tech Gmbh | Process for the independent dynamic reloading of data flow processors (DFPs) as well as modules with two- or multi-dimensional programmable cell structures (FPGAs, DPGAs, etc.) |
EP1329816B1 (en) * | 1996-12-27 | 2011-06-22 | Richter, Thomas | Method for automatic dynamic unloading of data flow processors (dfp) as well as modules with bidimensional or multidimensional programmable cell structures (fpgas, dpgas or the like) |
US5821776A (en) * | 1997-01-31 | 1998-10-13 | Actel Corporation | Field programmable gate array with mask programmed analog function circuits |
US5959466A (en) | 1997-01-31 | 1999-09-28 | Actel Corporation | Field programmable gate array with mask programmed input and output buffers |
DE19704044A1 (en) * | 1997-02-04 | 1998-08-13 | Pact Inf Tech Gmbh | Address generation with systems having programmable modules |
DE19704728A1 (en) * | 1997-02-08 | 1998-08-13 | Pact Inf Tech Gmbh | Method for self-synchronization of configurable elements of a programmable module |
US6542998B1 (en) | 1997-02-08 | 2003-04-01 | Pact Gmbh | Method of self-synchronization of configurable elements of a programmable module |
DE19704742A1 (en) | 1997-02-11 | 1998-09-24 | Pact Inf Tech Gmbh | Internal bus system for DFPs, as well as modules with two- or multi-dimensional programmable cell structures, for coping with large amounts of data with high networking effort |
US6150837A (en) | 1997-02-28 | 2000-11-21 | Actel Corporation | Enhanced field programmable gate array |
US6011744A (en) * | 1997-07-16 | 2000-01-04 | Altera Corporation | Programmable logic device with multi-port memory |
US6034857A (en) | 1997-07-16 | 2000-03-07 | Altera Corporation | Input/output buffer with overcurrent protection circuit |
US6020760A (en) * | 1997-07-16 | 2000-02-01 | Altera Corporation | I/O buffer circuit with pin multiplexing |
US6020755A (en) * | 1997-09-26 | 2000-02-01 | Lucent Technologies Inc. | Hybrid programmable gate arrays |
US8686549B2 (en) | 2001-09-03 | 2014-04-01 | Martin Vorbach | Reconfigurable elements |
US6292930B1 (en) * | 1997-10-09 | 2001-09-18 | Vantis Corporation | Methods for configuring FPGA's having variable grain blocks and shared logic for providing time-shared access to interconnect resources |
US6289494B1 (en) * | 1997-11-12 | 2001-09-11 | Quickturn Design Systems, Inc. | Optimized emulation and prototyping architecture |
DE19861088A1 (en) | 1997-12-22 | 2000-02-10 | Pact Inf Tech Gmbh | Repairing integrated circuits by replacing subassemblies with substitutes |
DE19807872A1 (en) | 1998-02-25 | 1999-08-26 | Pact Inf Tech Gmbh | Method of managing configuration data in data flow processors |
US6243664B1 (en) | 1998-10-27 | 2001-06-05 | Cypress Semiconductor Corporation | Methods for maximizing routability in a programmable interconnect matrix having less than full connectability |
US6262933B1 (en) | 1999-01-29 | 2001-07-17 | Altera Corporation | High speed programmable address decoder |
EP1228440B1 (en) | 1999-06-10 | 2017-04-05 | PACT XPP Technologies AG | Sequence partitioning in cell structures |
GB2351824B (en) | 1999-07-02 | 2004-03-31 | Altera Corp | Embedded memory blocks for programmable logic |
ATE476700T1 (en) | 2000-06-13 | 2010-08-15 | Richter Thomas | PIPELINE CT PROTOCOLS AND COMMUNICATIONS |
US7426665B1 (en) | 2000-09-02 | 2008-09-16 | Actel Corporation | Tileable field-programmable gate array architecture |
US6476636B1 (en) * | 2000-09-02 | 2002-11-05 | Actel Corporation | Tileable field-programmable gate array architecture |
US7015719B1 (en) * | 2000-09-02 | 2006-03-21 | Actel Corporation | Tileable field-programmable gate array architecture |
US6937063B1 (en) | 2000-09-02 | 2005-08-30 | Actel Corporation | Method and apparatus of memory clearing with monitoring RAM memory cells in a field programmable gated array |
US6870396B2 (en) * | 2000-09-02 | 2005-03-22 | Actel Corporation | Tileable field-programmable gate array architecture |
US20040015899A1 (en) * | 2000-10-06 | 2004-01-22 | Frank May | Method for processing data |
US8058899B2 (en) * | 2000-10-06 | 2011-11-15 | Martin Vorbach | Logic cell array and bus system |
US6990555B2 (en) * | 2001-01-09 | 2006-01-24 | Pact Xpp Technologies Ag | Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.) |
US7844796B2 (en) * | 2001-03-05 | 2010-11-30 | Martin Vorbach | Data processing device and method |
US7444531B2 (en) * | 2001-03-05 | 2008-10-28 | Pact Xpp Technologies Ag | Methods and devices for treating and processing data |
US20090210653A1 (en) * | 2001-03-05 | 2009-08-20 | Pact Xpp Technologies Ag | Method and device for treating and processing data |
US20090300262A1 (en) * | 2001-03-05 | 2009-12-03 | Martin Vorbach | Methods and devices for treating and/or processing data |
US9037807B2 (en) * | 2001-03-05 | 2015-05-19 | Pact Xpp Technologies Ag | Processor arrangement on a chip including data processing, memory, and interface elements |
WO2005045692A2 (en) * | 2003-08-28 | 2005-05-19 | Pact Xpp Technologies Ag | Data processing device and method |
US7210129B2 (en) | 2001-08-16 | 2007-04-24 | Pact Xpp Technologies Ag | Method for translating programs for reconfigurable architectures |
US7581076B2 (en) | 2001-03-05 | 2009-08-25 | Pact Xpp Technologies Ag | Methods and devices for treating and/or processing data |
US6630842B1 (en) | 2001-05-06 | 2003-10-07 | Altera Corporation | Routing architecture for a programmable logic device |
US6970014B1 (en) | 2001-05-06 | 2005-11-29 | Altera Corporation | Routing architecture for a programmable logic device |
US6895570B2 (en) | 2001-05-06 | 2005-05-17 | Altera Corporation | System and method for optimizing routing lines in a programmable logic device |
US6653862B2 (en) | 2001-05-06 | 2003-11-25 | Altera Corporation | Use of dangling partial lines for interfacing in a PLD |
US6605962B2 (en) | 2001-05-06 | 2003-08-12 | Altera Corporation | PLD architecture for flexible placement of IP function blocks |
JP2004533691A (en) * | 2001-06-20 | 2004-11-04 | ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト | Methods for processing data |
US7996827B2 (en) | 2001-08-16 | 2011-08-09 | Martin Vorbach | Method for the translation of programs for reconfigurable architectures |
US7139292B1 (en) * | 2001-08-31 | 2006-11-21 | Cypress Semiconductor Corp. | Configurable matrix architecture |
US7434191B2 (en) * | 2001-09-03 | 2008-10-07 | Pact Xpp Technologies Ag | Router |
US8686475B2 (en) | 2001-09-19 | 2014-04-01 | Pact Xpp Technologies Ag | Reconfigurable elements |
US7577822B2 (en) * | 2001-12-14 | 2009-08-18 | Pact Xpp Technologies Ag | Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization |
US20050132344A1 (en) * | 2002-01-18 | 2005-06-16 | Martin Vorbach | Method of compilation |
WO2003060747A2 (en) * | 2002-01-19 | 2003-07-24 | Pact Xpp Technologies Ag | Reconfigurable processor |
AU2003214003A1 (en) | 2002-02-18 | 2003-09-09 | Pact Xpp Technologies Ag | Bus systems and method for reconfiguration |
US8914590B2 (en) * | 2002-08-07 | 2014-12-16 | Pact Xpp Technologies Ag | Data processing method and device |
WO2003081454A2 (en) * | 2002-03-21 | 2003-10-02 | Pact Xpp Technologies Ag | Method and device for data processing |
US6774667B1 (en) | 2002-05-09 | 2004-08-10 | Actel Corporation | Method and apparatus for a flexible chargepump scheme for field-programmable gate arrays |
US6891394B1 (en) * | 2002-06-04 | 2005-05-10 | Actel Corporation | Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers |
US7378867B1 (en) * | 2002-06-04 | 2008-05-27 | Actel Corporation | Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers |
AU2003286131A1 (en) * | 2002-08-07 | 2004-03-19 | Pact Xpp Technologies Ag | Method and device for processing data |
US20110238948A1 (en) * | 2002-08-07 | 2011-09-29 | Martin Vorbach | Method and device for coupling a data processing unit and a data processing array |
US7657861B2 (en) * | 2002-08-07 | 2010-02-02 | Pact Xpp Technologies Ag | Method and device for processing data |
US6765427B1 (en) | 2002-08-08 | 2004-07-20 | Actel Corporation | Method and apparatus for bootstrapping a programmable antifuse circuit |
US7434080B1 (en) * | 2002-09-03 | 2008-10-07 | Actel Corporation | Apparatus for interfacing and testing a phase locked loop in a field programmable gate array |
JP4388895B2 (en) | 2002-09-06 | 2009-12-24 | ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト | Reconfigurable sequencer structure |
US6750674B1 (en) | 2002-10-02 | 2004-06-15 | Actel Corporation | Carry chain for use between logic modules in a field programmable gate array |
US6885218B1 (en) | 2002-10-08 | 2005-04-26 | Actel Corporation | Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA |
US7269814B1 (en) | 2002-10-08 | 2007-09-11 | Actel Corporation | Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA |
US6727726B1 (en) | 2002-11-12 | 2004-04-27 | Actel Corporation | Field programmable gate array architecture including a buffer module and a method of distributing buffer modules in a field programmable gate array |
US6946871B1 (en) * | 2002-12-18 | 2005-09-20 | Actel Corporation | Multi-level routing architecture in a field programmable gate array having transmitters and receivers |
US6891396B1 (en) | 2002-12-27 | 2005-05-10 | Actel Corporation | Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks |
US7385420B1 (en) | 2002-12-27 | 2008-06-10 | Actel Corporation | Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks |
JP2006524850A (en) * | 2003-04-04 | 2006-11-02 | ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト | Data processing method and data processing apparatus |
US7375553B1 (en) | 2003-05-28 | 2008-05-20 | Actel Corporation | Clock tree network in a field programmable gate array |
US6838902B1 (en) | 2003-05-28 | 2005-01-04 | Actel Corporation | Synchronous first-in/first-out block memory for a field programmable gate array |
US6825690B1 (en) | 2003-05-28 | 2004-11-30 | Actel Corporation | Clock tree network in a field programmable gate array |
US6867615B1 (en) * | 2003-05-30 | 2005-03-15 | Actel Corporation | Dedicated input/output first in/first out module for a field programmable gate array |
US7385419B1 (en) | 2003-05-30 | 2008-06-10 | Actel Corporation | Dedicated input/output first in/first out module for a field programmable gate array |
EP1849095B1 (en) * | 2005-02-07 | 2013-01-02 | Richter, Thomas | Low latency massive parallel data processing device |
JP4626490B2 (en) * | 2005-11-07 | 2011-02-09 | ソニー株式会社 | Circuit equipment |
WO2007062327A2 (en) * | 2005-11-18 | 2007-05-31 | Ideal Industries, Inc. | Releasable wire connector |
EP1974265A1 (en) | 2006-01-18 | 2008-10-01 | PACT XPP Technologies AG | Hardware definition method |
US8890567B1 (en) | 2010-09-30 | 2014-11-18 | Altera Corporation | High speed testing of integrated circuits including resistive elements |
US9166598B1 (en) | 2012-05-08 | 2015-10-20 | Altera Corporation | Routing and programming for resistive switch arrays |
US9884435B2 (en) | 2013-02-08 | 2018-02-06 | Johnson & Johnson Vision Care, Inc. | Casting cup assembly for forming an ophthalmic device |
US9954533B2 (en) * | 2014-12-16 | 2018-04-24 | Samsung Electronics Co., Ltd. | DRAM-based reconfigurable logic |
Citations (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3473160A (en) * | 1966-10-10 | 1969-10-14 | Stanford Research Inst | Electronically controlled microelectronic cellular logic array |
GB1444084A (en) * | 1972-06-21 | 1976-07-28 | Honeywell Inf Systems | Generalized logic device |
US4124899A (en) * | 1977-05-23 | 1978-11-07 | Monolithic Memories, Inc. | Programmable array logic circuit |
US4398267A (en) * | 1979-12-11 | 1983-08-09 | Tokyo Shibaura Denki Kabushiki Kaisha | Semiconductor memory device |
US4642487A (en) * | 1984-09-26 | 1987-02-10 | Xilinx, Inc. | Special interconnect for configurable logic array |
US4706216A (en) * | 1985-02-27 | 1987-11-10 | Xilinx, Inc. | Configurable logic element |
US4745579A (en) * | 1986-02-07 | 1988-05-17 | Silicon Communications Corporation | Electrically erasable programmable logic array (EEPLA) |
US4758745A (en) * | 1986-09-19 | 1988-07-19 | Actel Corporation | User programmable integrated circuit interconnect architecture and test method |
US4786904A (en) * | 1986-12-15 | 1988-11-22 | Zoran Corporation | Electronically programmable gate array having programmable interconnect lines |
US4855619A (en) * | 1987-11-17 | 1989-08-08 | Xilinx, Inc. | Buffered routing element for a user programmable logic device |
US4870302A (en) * | 1984-03-12 | 1989-09-26 | Xilinx, Inc. | Configurable electrical circuit having configurable logic elements and configurable interconnects |
US4879481A (en) * | 1988-09-02 | 1989-11-07 | Cypress Semiconductor Corporation | Dual I/O macrocell for high speed synchronous state machine |
US4937475A (en) * | 1988-09-19 | 1990-06-26 | Massachusetts Institute Of Technology | Laser programmable integrated circuit |
US4963768A (en) * | 1985-03-29 | 1990-10-16 | Advanced Micro Devices, Inc. | Flexible, programmable cell array interconnected by a programmable switch matrix |
US5027011A (en) * | 1989-10-31 | 1991-06-25 | Sgs-Thomson Microelectronics, Inc. | Input row drivers for programmable logic devices |
US5122685A (en) * | 1991-03-06 | 1992-06-16 | Quicklogic Corporation | Programmable application specific integrated circuit and logic cell therefor |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4020469A (en) * | 1975-04-09 | 1977-04-26 | Frank Manning | Programmable arrays |
US4409683A (en) * | 1981-11-18 | 1983-10-11 | Burroughs Corporation | Programmable multiplexer |
US4713792A (en) * | 1985-06-06 | 1987-12-15 | Altera Corporation | Programmable macrocell using eprom or eeprom transistors for architecture control in programmable logic circuits |
US4774421A (en) * | 1984-05-03 | 1988-09-27 | Altera Corporation | Programmable logic array device using EPROM technology |
US4617479B1 (en) * | 1984-05-03 | 1993-09-21 | Altera Semiconductor Corp. | Programmable logic array device using eprom technology |
US4609986A (en) * | 1984-06-14 | 1986-09-02 | Altera Corporation | Programmable logic array device using EPROM technology |
US4677318A (en) * | 1985-04-12 | 1987-06-30 | Altera Corporation | Programmable logic storage element for programmable logic devices |
DE3543471C1 (en) * | 1985-12-09 | 1992-01-09 | Nixdorf Computer Ag | Building block made in integrated technology for creating integrated circuits |
EP0317287B1 (en) * | 1987-11-20 | 1992-11-11 | Kawasaki Steel Corporation | Programmable logic device |
US4818988A (en) * | 1988-01-04 | 1989-04-04 | Gte Laboratories Incorporated | Crosspoint switching array |
US4912342A (en) * | 1988-05-05 | 1990-03-27 | Altera Corporation | Programmable logic device with array blocks with programmable clocking |
US4903223A (en) * | 1988-05-05 | 1990-02-20 | Altera Corporation | Programmable logic device with programmable word line connections |
US4871930A (en) * | 1988-05-05 | 1989-10-03 | Altera Corporation | Programmable logic device with array blocks connected via programmable interconnect |
US4899067A (en) * | 1988-07-22 | 1990-02-06 | Altera Corporation | Programmable logic devices with spare circuits for use in replacing defective circuits |
US5212652A (en) * | 1989-08-15 | 1993-05-18 | Advanced Micro Devices, Inc. | Programmable gate array with improved interconnect structure |
US5144166A (en) * | 1990-11-02 | 1992-09-01 | Concurrent Logic, Inc. | Programmable logic cell and array |
US5121006A (en) * | 1991-04-22 | 1992-06-09 | Altera Corporation | Registered logic macrocell with product term allocation and adjacent product term stealing |
US5220214A (en) * | 1991-04-22 | 1993-06-15 | Altera Corporation | Registered logic macrocell with product term allocation and adjacent product term stealing |
US5241224A (en) * | 1991-04-25 | 1993-08-31 | Altera Corporation | High-density erasable programmable logic device architecture using multiplexer interconnections |
US5204556A (en) * | 1991-05-06 | 1993-04-20 | Lattice Semiconductor Corporation | Programmable interconnect structure for logic blocks |
US5260610A (en) * | 1991-09-03 | 1993-11-09 | Altera Corporation | Programmable logic element interconnections for programmable logic array integrated circuits |
US5260611A (en) * | 1991-09-03 | 1993-11-09 | Altera Corporation | Programmable logic array having local and long distance conductors |
US5371422A (en) * | 1991-09-03 | 1994-12-06 | Altera Corporation | Programmable logic device having multiplexers and demultiplexers randomly connected to global conductors for interconnections between logic elements |
US5350954A (en) * | 1993-03-29 | 1994-09-27 | Altera Corporation | Macrocell with flexible product term allocation |
-
1991
- 1991-09-03 US US07/754,017 patent/US5260610A/en not_active Expired - Lifetime
-
1992
- 1992-08-06 EP EP01112375A patent/EP1134896A2/en not_active Withdrawn
- 1992-08-06 DE DE69223010T patent/DE69223010D1/en not_active Expired - Lifetime
- 1992-08-06 EP EP97106242A patent/EP0786871B1/en not_active Expired - Lifetime
- 1992-08-06 EP EP92307217A patent/EP0530985B1/en not_active Expired - Lifetime
- 1992-09-02 JP JP23486892A patent/JP3488258B2/en not_active Expired - Lifetime
-
1993
- 1993-03-29 US US08/039,944 patent/US5376844A/en not_active Expired - Lifetime
-
1994
- 1994-12-15 US US08/356,516 patent/US5485103A/en not_active Expired - Lifetime
Patent Citations (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3473160A (en) * | 1966-10-10 | 1969-10-14 | Stanford Research Inst | Electronically controlled microelectronic cellular logic array |
GB1444084A (en) * | 1972-06-21 | 1976-07-28 | Honeywell Inf Systems | Generalized logic device |
US4124899A (en) * | 1977-05-23 | 1978-11-07 | Monolithic Memories, Inc. | Programmable array logic circuit |
US4124899B1 (en) * | 1977-05-23 | 1987-04-28 | ||
US4398267A (en) * | 1979-12-11 | 1983-08-09 | Tokyo Shibaura Denki Kabushiki Kaisha | Semiconductor memory device |
US4870302A (en) * | 1984-03-12 | 1989-09-26 | Xilinx, Inc. | Configurable electrical circuit having configurable logic elements and configurable interconnects |
US4642487A (en) * | 1984-09-26 | 1987-02-10 | Xilinx, Inc. | Special interconnect for configurable logic array |
US4706216A (en) * | 1985-02-27 | 1987-11-10 | Xilinx, Inc. | Configurable logic element |
US4758985A (en) * | 1985-02-27 | 1988-07-19 | Xilinx, Inc. | Microprocessor oriented configurable logic element |
US4963768A (en) * | 1985-03-29 | 1990-10-16 | Advanced Micro Devices, Inc. | Flexible, programmable cell array interconnected by a programmable switch matrix |
US4745579A (en) * | 1986-02-07 | 1988-05-17 | Silicon Communications Corporation | Electrically erasable programmable logic array (EEPLA) |
US4758745A (en) * | 1986-09-19 | 1988-07-19 | Actel Corporation | User programmable integrated circuit interconnect architecture and test method |
US4873459B1 (en) * | 1986-09-19 | 1995-01-10 | Actel Corp | Programmable interconnect architecture |
US4873459A (en) * | 1986-09-19 | 1989-10-10 | Actel Corporation | Programmable interconnect architecture |
US4758745B1 (en) * | 1986-09-19 | 1994-11-15 | Actel Corp | User programmable integrated circuit interconnect architecture and test method |
US4786904A (en) * | 1986-12-15 | 1988-11-22 | Zoran Corporation | Electronically programmable gate array having programmable interconnect lines |
US4855619A (en) * | 1987-11-17 | 1989-08-08 | Xilinx, Inc. | Buffered routing element for a user programmable logic device |
US4879481A (en) * | 1988-09-02 | 1989-11-07 | Cypress Semiconductor Corporation | Dual I/O macrocell for high speed synchronous state machine |
US4937475A (en) * | 1988-09-19 | 1990-06-26 | Massachusetts Institute Of Technology | Laser programmable integrated circuit |
US4937475B1 (en) * | 1988-09-19 | 1994-03-29 | Massachusetts Inst Technology | Laser programmable integrated circuit |
US5027011A (en) * | 1989-10-31 | 1991-06-25 | Sgs-Thomson Microelectronics, Inc. | Input row drivers for programmable logic devices |
US5122685A (en) * | 1991-03-06 | 1992-06-16 | Quicklogic Corporation | Programmable application specific integrated circuit and logic cell therefor |
Non-Patent Citations (33)
Title |
---|
A. Haines, "Field-programmable gate array with non-volatile configuration", Microprocessors and Microsystems, vol. 13, No. 5, Jun. 1989. |
A. Haines, Field programmable gate array with non volatile configuration , Microprocessors and Microsystems, vol. 13, No. 5, Jun. 1989. * |
Advanced Micro Devices, "The World's Most Versatile Logic Tool AmPAL22V10", May 1984. |
Advanced Micro Devices, The World s Most Versatile Logic Tool AmPAL22V10 , May 1984. * |
Carr et al., MOS/LSI Design and Application , Texas Instruments Electronics Series, McGraw Hill and Co., 1972, pp. 229 258. * |
Carr et al., MOS/LSI Design and Application, Texas Instruments Electronics Series, McGraw-Hill and Co., 1972, pp. 229-258. |
F. Furtek et al., "Labyrinth: a homogeneous computational medium", Proc. IEEE 1990 Custom Integrated circuits Conference. |
F. Furtek et al., Labyrinth: a homogeneous computational medium , Proc. IEEE 1990 Custom Integrated circuits Conference. * |
F. Heutink, "Implications of Busing for Cellular Arrays," Computer Design, pp. 95-100, Nov. 1974. |
F. Heutink, Implications of Busing for Cellular Arrays, Computer Design, pp. 95 100, Nov. 1974. * |
Fleisher et al., "An Introduction to Array Logic", IBM Journal of Research and Development, Mar. 1975, pp. 98-109. |
Fleisher et al., An Introduction to Array Logic , IBM Journal of Research and Development, Mar. 1975, pp. 98 109. * |
H. C. Hsieh, "Third-generation architecture boosts speed and density of field-programmable gate arrays", Proc. IEEE 1990 Custom Integrated Circuits Conference. |
H. C. Hsieh, Third generation architecture boosts speed and density of field programmable gate arrays , Proc. IEEE 1990 Custom Integrated Circuits Conference. * |
Horninger, "A High-Speed ESFI SOS Programmable Logic Array with an MNOS Version", IEEE Journal of Solid State Circuits, vol. SC-10, No. 5, Oct. 1975, pp. 331-336. |
Horninger, A High Speed ESFI SOS Programmable Logic Array with an MNOS Version , IEEE Journal of Solid State Circuits, vol. SC 10, No. 5, Oct. 1975, pp. 331 336. * |
K. A. El Ayat et al., A CMOS electrically configurable gate array , IEEE Journal of Solid State Circuits, vol. 24, No. 3, Jun. 1989. * |
K. A. El-Ayat et al., "A CMOS electrically configurable gate array", IEEE Journal of Solid State Circuits, vol. 24, No. 3, Jun. 1989. |
Kitson et al., "Programmable Logic Chip Rivals Gate Arrays in Flexibility", Electronic Design, Dec. 8, 1983, pp. 95-102. |
Kitson et al., Programmable Logic Chip Rivals Gate Arrays in Flexibility , Electronic Design, Dec. 8, 1983, pp. 95 102. * |
M. Ahrens et al., "An FPGA family optimized for high densities and reduced routing delay", Proc. IEEE 1990 Custom Integrated Circuits Conference. |
M. Ahrens et al., An FPGA family optimized for high densities and reduced routing delay , Proc. IEEE 1990 Custom Integrated Circuits Conference. * |
Monolithic Memories, "Programmable Array Logic PAL20RA10", Jun. 1984. |
Monolithic Memories, Programmable Array Logic PAL20RA10 , Jun. 1984. * |
R. C. Minnick, "A Survey of Microcellular Research," Journal of the Association for Computing Machinery, vol. 14, No. 2, pp. 203-241, Apr. 1967. |
R. C. Minnick, A Survey of Microcellular Research, Journal of the Association for Computing Machinery, vol. 14, No. 2, pp. 203 241, Apr. 1967. * |
Richard G. Shoup, Programmable Cellular Logic Arrays (1970) (Ph.D. dissertation, Carnegie Mellon University (Pittsburgh)). * |
Richard G. Shoup, Programmable Cellular Logic Arrays (1970) (Ph.D. dissertation, Carnegie-Mellon University (Pittsburgh)). |
S. E. Wahlstrom, "Programmable Logic Arrays-Cheaper by the Millions", Electronics, Dec. 11, 1967, pp. 90-95. |
S. E. Wahlstrom, Programmable Logic Arrays Cheaper by the Millions , Electronics, Dec. 11, 1967, pp. 90 95. * |
The Programmable Gate Array Data Book, Xilinx, Inc., 1988. * |
The Programmable Gate Array Data Book, Xilinx, Inc., 1991, pp. 1 3 to 1 5, 2 1 to 2 13 and 2 61 to 2 69. * |
The Programmable Gate Array Data Book, Xilinx, Inc., 1991, pp. 1-3 to 1-5, 2-1 to 2-13 and 2-61 to 2-69. |
Cited By (485)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6160420A (en) | 1986-09-19 | 2000-12-12 | Actel Corporation | Programmable interconnect architecture |
US5451887A (en) * | 1986-09-19 | 1995-09-19 | Actel Corporation | Programmable logic module and architecture for field programmable gate array device |
US5644496A (en) * | 1989-08-15 | 1997-07-01 | Advanced Micro Devices, Inc. | Programmable logic device with internal time-constant multiplexing of signals from external interconnect buses |
US5621650A (en) * | 1989-10-30 | 1997-04-15 | Advanced Micro Devices, Inc. | Programmable logic device with internal time-constant multiplexing of signals from external interconnect buses |
US5598108A (en) * | 1991-04-25 | 1997-01-28 | Altera Corporation | High-density erasable programmable logic device architecture using multiplexer interconnections, and registered macrocell with product term allocation and adjacent product term stealing |
US6707315B2 (en) | 1991-04-25 | 2004-03-16 | Altera Corporation | Registered logic macrocell with product term allocation and adjacent product term stealing |
US5557217A (en) * | 1991-04-25 | 1996-09-17 | Altera Corporation | High-density erasable programmable logic device architecture using multiplexer interconnections |
US6157208A (en) * | 1991-04-25 | 2000-12-05 | Altera Corporation | Programmable logic device macrocell with improved logic capability |
US5861760A (en) * | 1991-04-25 | 1999-01-19 | Altera Corporation | Programmable logic device macrocell with improved capability |
US6366119B1 (en) | 1991-04-25 | 2002-04-02 | Altera Corporation | Programmable logic device macrocell with improved logic capability |
US5848005A (en) * | 1991-09-03 | 1998-12-08 | Altera Corporation | Programmable logic array integrated circuits |
US6064599A (en) * | 1991-09-03 | 2000-05-16 | Altera Corporation | Programmable logic array integrated circuits |
US5485103A (en) * | 1991-09-03 | 1996-01-16 | Altera Corporation | Programmable logic array with local and global conductors |
US20020130681A1 (en) * | 1991-09-03 | 2002-09-19 | Cliff Richard G. | Programmable logic array integrated circuits |
US6028808A (en) * | 1991-09-03 | 2000-02-22 | Altera Corporation | Programmable logic array integrated circuits |
US5668771A (en) * | 1991-09-03 | 1997-09-16 | Altera Corporation | Programmable logic array integrated circuits |
US6023439A (en) * | 1991-09-03 | 2000-02-08 | Altera Corporation | Programmable logic array integrated circuits |
US6897679B2 (en) | 1991-09-03 | 2005-05-24 | Altera Corporation | Programmable logic array integrated circuits |
US6018490A (en) * | 1991-09-03 | 2000-01-25 | Altera Corporation | Programmable logic array integrated circuits |
US6759870B2 (en) | 1991-09-03 | 2004-07-06 | Altera Corporation | Programmable logic array integrated circuits |
US5883850A (en) * | 1991-09-03 | 1999-03-16 | Altera Corporation | Programmable logic array integrated circuits |
US5764583A (en) * | 1991-09-03 | 1998-06-09 | Altera Corporation | Programmable logic array integrated circuits |
US5550782A (en) * | 1991-09-03 | 1996-08-27 | Altera Corporation | Programmable logic array integrated circuits |
US5812479A (en) * | 1991-09-03 | 1998-09-22 | Altera Corporation | Programmable logic array integrated circuits |
US6134173A (en) * | 1991-09-03 | 2000-10-17 | Altera Corporation | Programmable logic array integrated circuits |
US5838628A (en) * | 1991-09-03 | 1998-11-17 | Altera Corporation | Programmable logic array integrated circuits |
US5828229A (en) * | 1991-09-03 | 1998-10-27 | Altera Corporation | Programmable logic array integrated circuits |
EP0767422A1 (en) | 1992-05-08 | 1997-04-09 | Altera Corporation | Look up table implementation of fast carry for adders and counters |
EP0767423A1 (en) | 1992-05-08 | 1997-04-09 | Altera Corporation | Look up table implementation of fast carry for adders and counters |
EP0767421A1 (en) | 1992-05-08 | 1997-04-09 | Altera Corporation | Look up table implementation of fast carry for adders and counters |
US5617042A (en) * | 1992-08-03 | 1997-04-01 | Advanced Micro Devices, Inc. | Multiple array programmable logic device with a plurality of programmable switch matrices |
US5811986A (en) * | 1992-08-03 | 1998-09-22 | Advanced Micro Devices, Inc. | Flexible synchronous/asynchronous cell structure for a high density programmable logic device |
US5457409A (en) * | 1992-08-03 | 1995-10-10 | Advanced Micro Devices, Inc. | Architecture of a multiple array high density programmable logic device with a plurality of programmable switch matrices |
US5594365A (en) * | 1992-08-03 | 1997-01-14 | Advanced Micro Devices, Inc. | Flexible block clock generation circuit for providing clock signals to clocked elements in a multiple array high density programmable logic device |
US5489857A (en) * | 1992-08-03 | 1996-02-06 | Advanced Micro Devices, Inc. | Flexible synchronous/asynchronous cell structure for a high density programmable logic device |
US6292018B1 (en) * | 1992-11-05 | 2001-09-18 | Xilinx, Inc. | Configurable cellular array |
US5485102A (en) * | 1992-11-19 | 1996-01-16 | Altera Corporation | Programmable logic devices with spare circuits for replacement of defects |
US5434514A (en) * | 1992-11-19 | 1995-07-18 | Altera Corporation | Programmable logic devices with spare circuits for replacement of defects |
US5483178A (en) * | 1993-03-29 | 1996-01-09 | Altera Corporation | Programmable logic device with logic block outputs coupled to adjacent logic block output multiplexers |
US5809281A (en) * | 1993-03-30 | 1998-09-15 | Altera Corporation | Field programmable gate array with high speed SRAM based configurable function block configurable as high performance logic or block of SRAM |
US5352940A (en) * | 1993-05-27 | 1994-10-04 | Altera Corporation | Ram convertible look-up table based macrocell for PLDs |
US5523706A (en) * | 1993-07-02 | 1996-06-04 | Altera Corporation | High speed, low power macrocell |
US5444394A (en) * | 1993-07-08 | 1995-08-22 | Altera Corporation | PLD with selective inputs from local and global conductors |
US6597196B2 (en) | 1993-08-03 | 2003-07-22 | Btr, Inc. | Architecture and interconnect scheme for programmable logic circuits |
US7646218B2 (en) | 1993-08-03 | 2010-01-12 | Actel Corporation | Architecture and interconnect scheme for programmable logic circuits |
US7142012B2 (en) | 1993-08-03 | 2006-11-28 | Btr, Inc. | Architecture and interconnect scheme for programmable logic circuits |
US6507217B2 (en) | 1993-08-03 | 2003-01-14 | Btr, Inc. | Architecture and interconnect scheme for programmable logic circuits |
US6462578B2 (en) | 1993-08-03 | 2002-10-08 | Btr, Inc. | Architecture and interconnect scheme for programmable logic circuits |
US7409664B2 (en) | 1993-08-03 | 2008-08-05 | Actel Corporation | Architecture and interconnect scheme for programmable logic circuits |
US20060095886A1 (en) * | 1993-08-03 | 2006-05-04 | Ting Beniamin S | Architecture and interconnect scheme for programmable logic circuits |
US5457410A (en) * | 1993-08-03 | 1995-10-10 | Btr, Inc. | Architecture and interconnect scheme for programmable logic circuits |
US7078933B2 (en) | 1993-08-03 | 2006-07-18 | Btr, Inc. | Architecture and interconnect scheme for programmable logic circuits |
US6051991A (en) * | 1993-08-03 | 2000-04-18 | Btr, Inc. | Architecture and interconnect scheme for programmable logic circuits |
US20080265938A1 (en) * | 1993-08-03 | 2008-10-30 | Ting Benjamin S | Architecture and interconnect scheme for programmable logic circuits |
US20060202717A1 (en) * | 1993-08-03 | 2006-09-14 | Ting Benjamin S | Architecture and interconnect scheme for programmable logic circuits |
US7017136B2 (en) | 1993-08-03 | 2006-03-21 | Btr, Inc. | Architecture and interconnect scheme for programmable logic circuits |
US6747482B2 (en) | 1993-08-03 | 2004-06-08 | Btr. Inc. | Architecture and interconnect scheme for programmable logic circuits |
US6703861B2 (en) | 1993-08-03 | 2004-03-09 | Btr, Inc. | Architecture and interconnect scheme for programmable logic circuits |
US8289047B2 (en) | 1993-08-03 | 2012-10-16 | Actel Corporation | Architecture and interconnect scheme for programmable logic circuits |
US20040088672A1 (en) * | 1993-08-03 | 2004-05-06 | Ting Benjamin S. | Architecture and interconnect scheme for programmable logic circuits |
US6989688B2 (en) | 1993-08-03 | 2006-01-24 | Btr, Inc. | Architecture and interconnect scheme for programmable logic circuits |
US20100073024A1 (en) * | 1993-08-03 | 2010-03-25 | Ting Benjamin S | Architecture and interconnect scheme for programmable logic circuits |
US20110050282A1 (en) * | 1993-08-03 | 2011-03-03 | Ting Benjamin S | Architecture and interconnect scheme for programmable logic circuits |
US20060076974A1 (en) * | 1993-08-03 | 2006-04-13 | Ting Benjamin S | Architecture and interconnect scheme for programmable logic circuits |
US6433580B1 (en) | 1993-08-03 | 2002-08-13 | Btr, Inc. | Architecture and interconnect scheme for programmable logic circuits |
US5386156A (en) * | 1993-08-27 | 1995-01-31 | At&T Corp. | Programmable function unit with programmable fast ripple logic |
US5563592A (en) * | 1993-11-22 | 1996-10-08 | Altera Corporation | Programmable logic device having a compressed configuration file and associated decompression |
US5455525A (en) * | 1993-12-06 | 1995-10-03 | Intelligent Logic Systems, Inc. | Hierarchically-structured programmable logic array and system for interconnecting logic elements in the logic array |
WO1995022205A1 (en) * | 1994-02-15 | 1995-08-17 | Xilinx, Inc. | Tile based architecture for fpga |
US5682107A (en) * | 1994-04-01 | 1997-10-28 | Xilinx, Inc. | FPGA architecture with repeatable tiles including routing matrices and logic matrices |
US5883525A (en) * | 1994-04-01 | 1999-03-16 | Xilinx, Inc. | FPGA architecture with repeatable titles including routing matrices and logic matrices |
US6181162B1 (en) | 1994-04-10 | 2001-01-30 | Altera Corporation | Programmable logic device with highly routable interconnect |
US5594366A (en) * | 1994-05-04 | 1997-01-14 | Atmel Corporation | Programmable logic device with regional and universal signal routing |
WO1995030952A1 (en) * | 1994-05-04 | 1995-11-16 | Atmel Corporation | Programmable logic device with regional and universal signal routing |
US6128692A (en) * | 1994-05-18 | 2000-10-03 | Altera Corporation | Programming and verification address generation for random access memory blocks in programmable logic array integrated circuit devices |
USRE38651E1 (en) * | 1994-05-18 | 2004-11-09 | Altera Corporation | Variable depth and width memory device |
US5615126A (en) * | 1994-08-24 | 1997-03-25 | Lsi Logic Corporation | High-speed internal interconnection technique for integrated circuits that reduces the number of signal lines through multiplexing |
US5714890A (en) * | 1994-09-26 | 1998-02-03 | Philips Electronics North America Corporation | Programmable logic device with fixed and programmable memory |
US6160347A (en) * | 1994-10-17 | 2000-12-12 | Canon Kabushiki Kaisha | Electron source and image forming apparatus as well as method of providing the same with means for maintaining activated state thereof |
US6122720A (en) * | 1994-11-04 | 2000-09-19 | Altera Corporation | Coarse-grained look-up table architecture |
US5815726A (en) * | 1994-11-04 | 1998-09-29 | Altera Corporation | Coarse-grained look-up table architecture |
US5761099A (en) * | 1994-11-04 | 1998-06-02 | Altera Corporation | Programmable logic array integrated circuits with enhanced carry routing |
WO1996016480A1 (en) * | 1994-11-23 | 1996-05-30 | Virtual Machine Works, Inc. | Pipe-lined static router for configurable logic system |
US5850537A (en) * | 1994-11-23 | 1998-12-15 | Virtual Machine Works, Inc. | Pipe lined static router and scheduler for configurable logic system performing simultaneous communications and computation |
US5659716A (en) * | 1994-11-23 | 1997-08-19 | Virtual Machine Works, Inc. | Pipe-lined static router and scheduler for configurable logic system performing simultaneous communications and computation |
US5850365A (en) * | 1994-12-16 | 1998-12-15 | Altera Corporation | Sense amplifier with individually optimized high and low power modes |
US5525917A (en) * | 1994-12-16 | 1996-06-11 | Altera Corporation | Sense amplifier with feedback and stabilization |
US5537057A (en) * | 1995-02-14 | 1996-07-16 | Altera Corporation | Programmable logic array device with grouped logic regions and three types of conductors |
US5598109A (en) * | 1995-02-14 | 1997-01-28 | Altera Corporation | Programmable logic array device with grouped logic regions and three types of conductors |
US5572148A (en) * | 1995-03-22 | 1996-11-05 | Altera Corporation | Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory |
US6218860B1 (en) | 1995-03-22 | 2001-04-17 | Altera Corporation | Programmable logic array integrated circuit incorporating a first-in first-out memory |
US5570040A (en) * | 1995-03-22 | 1996-10-29 | Altera Corporation | Programmable logic array integrated circuit incorporating a first-in first-out memory |
US6340897B1 (en) * | 1995-03-22 | 2002-01-22 | Altera Corporation | Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory |
US5757207A (en) * | 1995-03-22 | 1998-05-26 | Altera Corporation | Programmable logic array integrated circuit incorporating a first-in first-out memory |
US6134166A (en) * | 1995-03-22 | 2000-10-17 | Altera Corporation | Programmable logic array integrated circuit incorporating a first-in first-out memory |
US6049223A (en) * | 1995-03-22 | 2000-04-11 | Altera Corporation | Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory |
US6300793B1 (en) | 1995-05-03 | 2001-10-09 | Btr, Inc. | Scalable multiple level tab oriented interconnect architecture |
US5850564A (en) * | 1995-05-03 | 1998-12-15 | Btr, Inc, | Scalable multiple level tab oriented interconnect architecture |
US20020070756A1 (en) * | 1995-05-03 | 2002-06-13 | Ting Benjamins S. | Floor plan for scalable multiple level tab oriented interconnect architecture |
US7009422B2 (en) | 1995-05-03 | 2006-03-07 | Btr, Inc. | Floor plan for scalable multiple level tab oriented interconnect architecture |
US6417690B1 (en) | 1995-05-03 | 2002-07-09 | Btr, Inc. | Floor plan for scalable multiple level tab oriented interconnect architecture |
US20060114023A1 (en) * | 1995-05-03 | 2006-06-01 | Ting Benjamin S | Floor plan for scalable multiple level tab oriented interconnect architecture |
US7126375B2 (en) | 1995-05-03 | 2006-10-24 | Btr, Inc. | Floor plan for scalable multiple level tab oriented interconnect architecture |
US5541530A (en) * | 1995-05-17 | 1996-07-30 | Altera Corporation | Programmable logic array integrated circuits with blocks of logic regions grouped into super-blocks |
US5986470A (en) * | 1995-05-17 | 1999-11-16 | Altera Corporation | Programmable logic array integrated circuit devices |
US5909126A (en) * | 1995-05-17 | 1999-06-01 | Altera Corporation | Programmable logic array integrated circuit devices with interleaved logic array blocks |
US6154055A (en) * | 1995-05-17 | 2000-11-28 | Altera Corporation | Programmable logic array integrated circuit devices |
US5936425A (en) * | 1995-05-17 | 1999-08-10 | Altera Corporation | Tri-statable input/output circuitry for programmable logic |
US6204688B1 (en) | 1995-05-17 | 2001-03-20 | Altera Corporation | Programmable logic array integrated circuit devices with interleaved logic array blocks |
US6366121B2 (en) | 1995-05-17 | 2002-04-02 | Altera Corporation | Programmable logic array integrated circuit architectures |
US5614840A (en) * | 1995-05-17 | 1997-03-25 | Altera Corporation | Programmable logic array integrated circuits with segmented, selectively connectable, long interconnection conductors |
US6127846A (en) * | 1995-05-17 | 2000-10-03 | Altera Corporation | Programmable logic array devices with interconnect lines of various lengths |
US6191608B1 (en) | 1995-05-17 | 2001-02-20 | Altera Corporation | Techniques for programming programmable logic array devices |
US5900743A (en) * | 1995-05-17 | 1999-05-04 | Altera Corporation | Programmable logic array devices with interconnect lines of various lengths |
US5680061A (en) * | 1995-05-17 | 1997-10-21 | Altera Corporation | Techniques for programming programmable logic array devices |
US5963049A (en) * | 1995-05-17 | 1999-10-05 | Altera Corporation | Programmable logic array integrated circuit architectures |
US6815981B2 (en) | 1995-05-17 | 2004-11-09 | Altera Corporation | Programmable logic array integrated circuit devices |
US5689195A (en) * | 1995-05-17 | 1997-11-18 | Altera Corporation | Programmable logic array integrated circuit devices |
US5796267A (en) * | 1995-05-17 | 1998-08-18 | Altera Corporation | Tri-Statable input/output circuitry for programmable logic |
US5543732A (en) * | 1995-05-17 | 1996-08-06 | Altera Corporation | Programmable logic array devices with interconnect lines of various lengths |
US5850151A (en) * | 1995-05-17 | 1998-12-15 | Altera Corporation | Programmable logic array intergrated circuit devices |
US6278291B1 (en) | 1995-05-17 | 2001-08-21 | Altera Corporation | Programmable logic array devices with interconnect lines of various lengths |
US5850152A (en) * | 1995-05-17 | 1998-12-15 | Altera Corporation | Programmable logic array integrated circuit devices |
US6392438B1 (en) | 1995-05-17 | 2002-05-21 | Altera Corporation | Programmable logic array integrated circuit devices |
US5543730A (en) * | 1995-05-17 | 1996-08-06 | Altera Corporation | Techniques for programming programmable logic array devices |
US5592106A (en) * | 1995-05-17 | 1997-01-07 | Altera Corporation | Programmable logic array integrated circuits with interconnection conductors of overlapping extent |
US6184705B1 (en) | 1995-05-17 | 2001-02-06 | Altera Corporation | Techniques for programming programmable logic array devices |
US6396304B2 (en) | 1995-05-17 | 2002-05-28 | Altera Corporation | Programmable logic array integrated circuits with blocks of logic regions grouped into super-blocks |
US6259272B1 (en) | 1995-05-17 | 2001-07-10 | Altera Corporation | Programmable logic array integrated circuit architectures |
US5717901A (en) * | 1995-05-17 | 1998-02-10 | Altera Corporation | Variable depth and width memory device |
US5705939A (en) * | 1995-05-17 | 1998-01-06 | Altera Corporation | Programmable logic array integrated circuits with segmented, selectively connectable, long interconnection conductors |
US5789939A (en) * | 1995-06-02 | 1998-08-04 | Advanced Micro Devices, Inc. | Method for providing a plurality of hierarchical signal paths in a very high-density programmable logic device |
US5521529A (en) * | 1995-06-02 | 1996-05-28 | Advanced Micro Devices, Inc. | Very high-density complex programmable logic devices with a multi-tiered hierarchical switch matrix and optimized flexible logic allocation |
US5818254A (en) * | 1995-06-02 | 1998-10-06 | Advanced Micro Devices, Inc. | Multi-tiered hierarchical high speed switch matrix structure for very high-density complex programmable logic devices |
US6028446A (en) * | 1995-06-06 | 2000-02-22 | Advanced Micro Devices, Inc. | Flexible synchronous and asynchronous circuits for a very high density programmable logic device |
US5659717A (en) * | 1995-07-31 | 1997-08-19 | Altera Corporation | Methods for partitioning circuits in order to allocate elements among multiple circuit groups |
US5812450A (en) * | 1995-08-17 | 1998-09-22 | Altera Corporation | Nonvolatile SRAM cells and cell arrays |
US5581501A (en) * | 1995-08-17 | 1996-12-03 | Altera Corporation | Nonvolatile SRAM cells and cell arrays |
US5565793A (en) * | 1995-08-22 | 1996-10-15 | Altera Corporation | Programmable logic array integrated circuit devices with regions of enhanced interconnectivity |
US5764080A (en) * | 1995-08-24 | 1998-06-09 | Altera Corporation | Input/output interface circuitry for programmable logic array integrated circuit devices |
US6049225A (en) * | 1995-08-24 | 2000-04-11 | Altera Corporation | Input/output interface circuitry for programmable logic array integrated circuit devices |
US5631576A (en) * | 1995-09-01 | 1997-05-20 | Altera Corporation | Programmable logic array integrated circuit devices with flexible carry chains |
US5821773A (en) * | 1995-09-06 | 1998-10-13 | Altera Corporation | Look-up table based logic element with complete permutability of the inputs to the secondary signals |
US5805516A (en) * | 1995-09-29 | 1998-09-08 | Altera Corporation | Dynamic nonvolatile memory cell |
US5898630A (en) * | 1995-09-29 | 1999-04-27 | Altera Corporation | Dynamic nonvolatile memory cell |
US5729495A (en) * | 1995-09-29 | 1998-03-17 | Altera Corporation | Dynamic nonvolatile memory cell |
US5740110A (en) * | 1995-09-29 | 1998-04-14 | Altera Corporation | Dynamic nonvolatile memory cell |
US6130552A (en) * | 1995-10-16 | 2000-10-10 | Altera Corporation | Programmable logic integrated circuit with on-chip DLL or PLL for clock distribution |
US5970255A (en) * | 1995-10-16 | 1999-10-19 | Altera Corporation | System for coupling programmable logic device to external circuitry which selects a logic standard and uses buffers to modify output and input signals accordingly |
US5963069A (en) * | 1995-10-16 | 1999-10-05 | Altera Corporation | System for distributing clocks using a delay lock loop in a programmable logic circuit |
USRE40011E1 (en) | 1995-10-16 | 2008-01-22 | Altera Corporation | System for coupling programmable logic device to external circuitry which selects a logic standard and uses buffers to modify output and input signals accordingly |
US5744991A (en) * | 1995-10-16 | 1998-04-28 | Altera Corporation | System for distributing clocks using a delay lock loop in a programmable logic circuit |
US5825197A (en) * | 1995-10-19 | 1998-10-20 | Altera Corporation | Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices |
US5592102A (en) * | 1995-10-19 | 1997-01-07 | Altera Corporation | Means and apparatus to minimize the effects of silicon processing defects in programmable logic devices |
US5670895A (en) * | 1995-10-19 | 1997-09-23 | Altera Corporation | Routing connections for programmable logic array integrated circuits |
US5793246A (en) * | 1995-11-08 | 1998-08-11 | Altera Corporation | High voltage pump scheme incorporating an overlapping clock |
US6236260B1 (en) | 1995-11-08 | 2001-05-22 | Altera Corporation | High voltage pump scheme incorporating an overlapping clock |
US5672985A (en) * | 1995-12-18 | 1997-09-30 | Altera Corporation | Programmable logic array integrated circuits with carry and/or cascade rings |
US5767734A (en) * | 1995-12-21 | 1998-06-16 | Altera Corporation | High-voltage pump with initiation scheme |
US6882177B1 (en) | 1996-01-10 | 2005-04-19 | Altera Corporation | Tristate structures for programmable logic devices |
US6239613B1 (en) | 1996-01-10 | 2001-05-29 | Altera Corporation | Tristate structures for programmable logic devices |
US5894228A (en) * | 1996-01-10 | 1999-04-13 | Altera Corporation | Tristate structures for programmable logic devices |
US5691653A (en) * | 1996-01-16 | 1997-11-25 | Altera Corporation | Product term based programmable logic array devices with reduced control memory requirements |
US6045252A (en) * | 1996-02-20 | 2000-04-04 | Altera Corporation | Methods for allocating circuit design portions among physical circuit portions |
US5768372A (en) * | 1996-03-13 | 1998-06-16 | Altera Corporation | Method and apparatus for securing programming data of a programmable logic device |
US5915017A (en) * | 1996-03-13 | 1999-06-22 | Altera Corporation | Method and apparatus for securing programming data of programmable logic device |
US6366498B1 (en) | 1996-03-14 | 2002-04-02 | Altera Corporation | Nonvolatile configuration cells and cell arrays |
US6532170B1 (en) | 1996-03-14 | 2003-03-11 | Altera Corporation | Nonvolatile configuration cells and cell arrays |
US6295230B1 (en) | 1996-03-14 | 2001-09-25 | Altera Coporation | Nonvolatile configuration cells and cell arrays |
US6052309A (en) * | 1996-03-14 | 2000-04-18 | Altera Corporation | Nonvolatile configuration cells and cell arrays |
US6005806A (en) * | 1996-03-14 | 1999-12-21 | Altera Corporation | Nonvolatile configuration cells and cell arrays |
US6226201B1 (en) | 1996-03-14 | 2001-05-01 | Altera Corporation | Techniques to configure nonvolatile cells and cell arrays |
US5694058A (en) * | 1996-03-20 | 1997-12-02 | Altera Corporation | Programmable logic array integrated circuits with improved interconnection conductor utilization |
US5835998A (en) * | 1996-04-04 | 1998-11-10 | Altera Corporation | Logic cell for programmable logic devices |
US5872463A (en) * | 1996-04-04 | 1999-02-16 | Altera Corporation | Routing in programmable logic devices using shared distributed programmable logic connectors |
US6414514B1 (en) | 1996-04-05 | 2002-07-02 | Altera Corporation | Logic device architecture and method of operation |
US6208162B1 (en) | 1996-04-05 | 2001-03-27 | Altera Corporation | Technique for preconditioning I/Os during reconfiguration |
US5869979A (en) * | 1996-04-05 | 1999-02-09 | Altera Corporation | Technique for preconditioning I/Os during reconfiguration |
US6294928B1 (en) | 1996-04-05 | 2001-09-25 | Altera Corporation | Programmable logic device with highly routable interconnect |
US6184706B1 (en) | 1996-04-05 | 2001-02-06 | Altera Corporation | Logic device architecture and method of operation |
US6492834B1 (en) | 1996-04-05 | 2002-12-10 | Altera Corporation | Programmable logic device with highly routable interconnect |
US5986465A (en) * | 1996-04-09 | 1999-11-16 | Altera Corporation | Programmable logic integrated circuit architecture incorporating a global shareable expander |
US6359469B1 (en) | 1996-04-09 | 2002-03-19 | Altera Corporation | Logic element for a programmable logic integrated circuit |
US6275065B1 (en) | 1996-04-09 | 2001-08-14 | Altera Corporation | Programmable logic integrated circuit architecture incorporating a lonely register |
US6271680B1 (en) | 1996-04-09 | 2001-08-07 | Altera Corporation | Logic element for a programmable logic integrated circuit |
US6246260B1 (en) | 1996-04-09 | 2001-06-12 | Altera Corporation | Programmable logic integrated circuit architecture incorporating a global shareable expander |
US6107822A (en) * | 1996-04-09 | 2000-08-22 | Altera Corporation | Logic element for a programmable logic integrated circuit |
US5939790A (en) * | 1996-04-09 | 1999-08-17 | Altera Corporation | Integrated circuit pad structures |
US20030197218A1 (en) * | 1996-04-10 | 2003-10-23 | Altera Corporation | Nonvolatile memory cell with low doping region |
US6122209A (en) * | 1996-04-10 | 2000-09-19 | Altera Corporation | Method of margin testing programmable interconnect cell |
US5998295A (en) * | 1996-04-10 | 1999-12-07 | Altera Corporation | Method of forming a rough region on a substrate |
US6573138B1 (en) | 1996-04-10 | 2003-06-03 | Altera Corporation | Nonvolatile memory cell with low doping region |
US6624524B1 (en) | 1996-04-10 | 2003-09-23 | Altera Corporation | Laser alignment target |
US6828620B2 (en) | 1996-04-10 | 2004-12-07 | Altera Corporation | Nonvolatile memory cell with low doping region |
US6002182A (en) * | 1996-04-10 | 1999-12-14 | Altera Corporation | Laser alignment target |
US5949710A (en) * | 1996-04-10 | 1999-09-07 | Altera Corporation | Programmable interconnect junction |
US5977791A (en) * | 1996-04-15 | 1999-11-02 | Altera Corporation | Embedded memory block with FIFO mode for programmable logic device |
US6242946B1 (en) | 1996-04-15 | 2001-06-05 | Altera Corporation | Embedded memory block with FIFO mode for programmable logic device |
US5939930A (en) * | 1996-04-17 | 1999-08-17 | Xilinx, Inc. | Interconnect structure for FPGA using a multiplexer |
US6014509A (en) * | 1996-05-20 | 2000-01-11 | Atmel Corporation | Field programmable gate array having access to orthogonal and diagonal adjacent neighboring cells |
US5894565A (en) * | 1996-05-20 | 1999-04-13 | Atmel Corporation | Field programmable gate array with distributed RAM and increased cell utilization |
US6292021B1 (en) | 1996-05-20 | 2001-09-18 | Atmel Corporation | FPGA structure having main, column and sector reset lines |
US6026227A (en) * | 1996-05-20 | 2000-02-15 | Atmel Corporation | FPGA logic cell internal structure including pair of look-up tables |
US6167559A (en) * | 1996-05-20 | 2000-12-26 | Atmel Corporation | FPGA structure having main, column and sector clock lines |
US6147511A (en) * | 1996-05-28 | 2000-11-14 | Altera Corporation | Overvoltage-tolerant interface for integrated circuits |
US6433585B1 (en) | 1996-05-28 | 2002-08-13 | Altera Corporation | Overvoltage-tolerant interface for integrated circuits |
US6563343B1 (en) | 1996-05-28 | 2003-05-13 | Altera Corporation | Circuitry for a low internal voltage |
US6252422B1 (en) | 1996-05-28 | 2001-06-26 | Altera Corporation | Overvoltage-tolerant interface for intergrated circuits |
US6583646B1 (en) | 1996-05-28 | 2003-06-24 | Altera Corporation | Overvoltage-tolerant interface for integrated circuits |
US6118302A (en) * | 1996-05-28 | 2000-09-12 | Altera Corporation | Interface for low-voltage semiconductor devices |
US6342794B1 (en) | 1996-05-28 | 2002-01-29 | Altera Corporation | Interface for low-voltage semiconductor devices |
US6344758B1 (en) | 1996-05-28 | 2002-02-05 | Altera Corporation | Interface for low-voltage semiconductor devices |
US6724222B2 (en) | 1996-05-28 | 2004-04-20 | Altera Corporation | Programmable logic with lower internal voltage circuitry |
US6384630B2 (en) | 1996-06-05 | 2002-05-07 | Altera Corporation | Techniques for programming programmable logic array devices |
USRE40423E1 (en) | 1996-07-29 | 2008-07-08 | Xilinx, Inc. | Multiport RAM with programmable data port configuration |
US6031763A (en) * | 1996-08-16 | 2000-02-29 | Altera Corporation | Evaluation of memory cell characteristics |
US5959891A (en) * | 1996-08-16 | 1999-09-28 | Altera Corporation | Evaluation of memory cell characteristics |
US6282122B1 (en) | 1996-08-16 | 2001-08-28 | Altera Corporation | Evaluation of memory cell characteristics |
US5771264A (en) * | 1996-08-29 | 1998-06-23 | Altera Corporation | Digital delay lock loop for clock signal frequency multiplication |
US6975138B2 (en) | 1996-09-04 | 2005-12-13 | Advantage Logic, Inc. | Method and apparatus for universal program controlled bus architecture |
US20110043248A1 (en) * | 1996-09-04 | 2011-02-24 | Pani Peter M | Method and apparatus for universal program controlled bus architecture |
US6504399B2 (en) | 1996-09-04 | 2003-01-07 | Advantage Logic, Inc. | Method and apparatus for universal program controlled bus architecture |
US20040178822A1 (en) * | 1996-09-04 | 2004-09-16 | Pani Peter M. | Method and apparatus for universal program controlled bus architecture |
US6034547A (en) * | 1996-09-04 | 2000-03-07 | Advantage Logic, Inc. | Method and apparatus for universal program controlled bus |
US7915918B2 (en) | 1996-09-04 | 2011-03-29 | Actel Corporation | Method and apparatus for universal program controlled bus architecture |
US7382156B2 (en) | 1996-09-04 | 2008-06-03 | Actel Corporation | Method and apparatus for universal program controlled bus architecture |
US7830173B2 (en) | 1996-09-04 | 2010-11-09 | Actel Corporation | Method and apparatus for universal program controlled bus architecture |
US6329839B1 (en) | 1996-09-04 | 2001-12-11 | Advantage Logic, Inc. | Method and apparatus for universal program controlled bus architecture |
US20080191739A1 (en) * | 1996-09-04 | 2008-08-14 | Pani Peter M | Method and apparatus for universal program controlled bus architecture |
US20060202716A1 (en) * | 1996-09-04 | 2006-09-14 | Pani Peter M | Method and apparatus for universal program controlled bus architecture |
US6018476A (en) * | 1996-09-16 | 2000-01-25 | Altera Corporation | Nonvolatile configuration cells and cell arrays |
US6078521A (en) * | 1996-09-16 | 2000-06-20 | Altera Corporation | Nonvolatile configuration cells and cell arrays |
US6442073B1 (en) | 1996-09-16 | 2002-08-27 | Altera Corporation | Nonvolatile memory cell with multiple gate oxide thicknesses |
US6236597B1 (en) | 1996-09-16 | 2001-05-22 | Altera Corporation | Nonvolatile memory cell with multiple gate oxide thicknesses |
US5880597A (en) * | 1996-09-18 | 1999-03-09 | Altera Corporation | Interleaved interconnect for programmable logic array devices |
US5844854A (en) * | 1996-09-18 | 1998-12-01 | Altera Corporation | Programmable logic device with two dimensional memory addressing |
US6301694B1 (en) | 1996-09-25 | 2001-10-09 | Altera Corporation | Hierarchical circuit partitioning using sliding windows |
US5914904A (en) * | 1996-10-01 | 1999-06-22 | Altera Corporation | Compact electrically erasable memory cells and arrays |
US6243296B1 (en) | 1996-10-01 | 2001-06-05 | Altera Corporation | Compact electrically erasable memory cells and arrays |
US5796268A (en) * | 1996-10-02 | 1998-08-18 | Kaplinsky; Cecil H. | Programmable logic device with partial switch matrix and bypass mechanism |
US20030201794A1 (en) * | 1996-10-10 | 2003-10-30 | Altera Corporation | Programmable logic device with hierarchical interconnection resources |
US6798242B2 (en) | 1996-10-10 | 2004-09-28 | Altera Corporation | Programmable logic device with hierarchical interconnection resources |
US5999016A (en) * | 1996-10-10 | 1999-12-07 | Altera Corporation | Architectures for programmable logic devices |
US6300794B1 (en) | 1996-10-10 | 2001-10-09 | Altera Corporation | Programmable logic device with hierarchical interconnection resources |
US5977793A (en) * | 1996-10-10 | 1999-11-02 | Altera Corporation | Programmable logic device with hierarchical interconnection resources |
US6417694B1 (en) | 1996-10-10 | 2002-07-09 | Altera Corporation | Programmable logic device with hierarchical interconnection resources |
US6577160B2 (en) | 1996-10-10 | 2003-06-10 | Altera Corporation | Programmable logic device with hierarchical interconnection resources |
US5942914A (en) * | 1996-10-25 | 1999-08-24 | Altera Corporation | PLD with split multiplexed inputs from global conductors |
US6025737A (en) * | 1996-11-27 | 2000-02-15 | Altera Corporation | Circuitry for a low internal voltage integrated circuit |
US6029236A (en) * | 1997-01-28 | 2000-02-22 | Altera Corporation | Field programmable gate array with high speed SRAM based configurable function block configurable as high performance logic or block of SRAM |
US6091258A (en) * | 1997-02-05 | 2000-07-18 | Altera Corporation | Redundancy circuitry for logic circuits |
US6166559A (en) * | 1997-02-05 | 2000-12-26 | Altera Corporation | Redundancy circuitry for logic circuits |
US6034536A (en) * | 1997-02-05 | 2000-03-07 | Altera Corporation | Redundancy circuitry for logic circuits |
US5999015A (en) * | 1997-02-20 | 1999-12-07 | Altera Corporation | Logic region resources for programmable logic devices |
US5982195A (en) * | 1997-02-20 | 1999-11-09 | Altera Corporation | Programmable logic device architectures |
US6646467B1 (en) | 1997-02-20 | 2003-11-11 | Altera Corporation | PCI-compatible programmable logic devices |
US7148722B1 (en) | 1997-02-20 | 2006-12-12 | Altera Corporation | PCI-compatible programmable logic devices |
US6271681B1 (en) | 1997-02-20 | 2001-08-07 | Altera Corporation | PCI-compatible programmable logic devices |
US6127844A (en) * | 1997-02-20 | 2000-10-03 | Altera Corporation | PCI-compatible programmable logic devices |
US6124731A (en) * | 1997-02-26 | 2000-09-26 | Xilinx, Inc. | Configurable logic element with ability to evaluate wide logic functions |
US6448808B2 (en) * | 1997-02-26 | 2002-09-10 | Xilinx, Inc. | Interconnect structure for a programmable logic device |
US6201410B1 (en) | 1997-02-26 | 2001-03-13 | Xilinx, Inc. | Wide logic gate implemented in an FPGA configurable logic element |
US5907248A (en) * | 1997-02-26 | 1999-05-25 | Xilinx, Inc. | FPGA interconnect structure with high-speed high fanout capability |
US6292022B2 (en) | 1997-02-26 | 2001-09-18 | Xilinx, Inc. | Interconnect structure for a programmable logic device |
US6107827A (en) * | 1997-02-26 | 2000-08-22 | Xilinx, Inc. | FPGA CLE with two independent carry chains |
US5963050A (en) * | 1997-02-26 | 1999-10-05 | Xilinx, Inc. | Configurable logic element with fast feedback paths |
US6051992A (en) * | 1997-02-26 | 2000-04-18 | Xilinx, Inc. | Configurable logic element with ability to evaluate five and six input functions |
US6204690B1 (en) | 1997-02-26 | 2001-03-20 | Xilinx, Inc. | FPGA architecture with offset interconnect lines |
US6204689B1 (en) | 1997-02-26 | 2001-03-20 | Xilinx, Inc. | Input/output interconnect circuit for FPGAs |
US5920202A (en) * | 1997-02-26 | 1999-07-06 | Xilinx, Inc. | Configurable logic element with ability to evaluate five and six input functions |
US5889411A (en) * | 1997-02-26 | 1999-03-30 | Xilinx, Inc. | FPGA having logic element carry chains capable of generating wide XOR functions |
US5942913A (en) * | 1997-03-20 | 1999-08-24 | Xilinx, Inc. | FPGA repeatable interconnect structure with bidirectional and unidirectional interconnect lines |
US6184710B1 (en) | 1997-03-20 | 2001-02-06 | Altera Corporation | Programmable logic array devices with enhanced interconnectivity between adjacent logic regions |
US6320411B1 (en) | 1997-03-20 | 2001-11-20 | Altera Corporation | Programmable logic array devices with enhanced interconnectivity between adjacent logic regions |
US6034540A (en) * | 1997-04-08 | 2000-03-07 | Altera Corporation | Programmable logic integrated circuit architecture incorporating a lonely register |
US5883526A (en) * | 1997-04-17 | 1999-03-16 | Altera Corporation | Hierarchical interconnect for programmable logic devices |
US6337578B2 (en) | 1997-05-23 | 2002-01-08 | Altera Corporation | Redundancy circuitry for programmable logic devices with interleaved input circuits |
US6107820A (en) * | 1997-05-23 | 2000-08-22 | Altera Corporation | Redundancy circuitry for programmable logic devices with interleaved input circuits |
US6222382B1 (en) | 1997-05-23 | 2001-04-24 | Altera Corporation | Redundancy circuitry for programmable logic devices with interleaved input circuits |
US6128215A (en) * | 1997-08-19 | 2000-10-03 | Altera Corporation | Static random access memory circuits |
US6353551B1 (en) | 1997-08-19 | 2002-03-05 | Altera Corporation | Static random access memory circuits |
US6239612B1 (en) | 1997-08-20 | 2001-05-29 | Altera Corporation | Programmable I/O cells with multiple drivers |
US6417692B2 (en) | 1997-08-20 | 2002-07-09 | Altera Corporation | Programmable I/O cells with multiple drivers |
US6545505B1 (en) * | 1997-09-30 | 2003-04-08 | Cypress Semiconductor Corporation | Hybrid routing architecture for high density complex programmable logic devices |
US6097212A (en) * | 1997-10-09 | 2000-08-01 | Lattice Semiconductor Corporation | Variable grain architecture for FPGA integrated circuits |
US6130555A (en) * | 1997-10-13 | 2000-10-10 | Altera Corporation | Driver circuitry for programmable logic devices |
US6052327A (en) * | 1997-10-14 | 2000-04-18 | Altera Corporation | Dual-port programmable logic device variable depth and width memory array |
US6392954B2 (en) | 1997-10-14 | 2002-05-21 | Altera Corporation | Dual port programmable logic device variable depth and width memory array |
US6072332A (en) * | 1997-10-14 | 2000-06-06 | Altera Corporation | Variable depth memories for programmable logic devices |
US6121790A (en) * | 1997-10-16 | 2000-09-19 | Altera Corporation | Programmable logic device with enhanced multiplexing capabilities in interconnect resources |
US6278288B1 (en) | 1997-10-16 | 2001-08-21 | Altera Corporation | Programmable logic device with enhanced multiplexing capabilities in interconnect resources |
US6191998B1 (en) | 1997-10-16 | 2001-02-20 | Altera Corporation | Programmable logic device memory array circuit having combinable single-port memory arrays |
US6288970B1 (en) | 1997-10-16 | 2001-09-11 | Altera Corporation | Programmable logic device memory array circuit having combinable single-port memory arrays |
US6107824A (en) * | 1997-10-16 | 2000-08-22 | Altera Corporation | Circuitry and methods for internal interconnection of programmable logic devices |
US6255846B1 (en) | 1997-10-16 | 2001-07-03 | Altera Corporation | Programmable logic devices with enhanced multiplexing capabilities |
US6225823B1 (en) | 1997-10-16 | 2001-05-01 | Altera Corporation | Input/output circuitry for programmable logic devices |
US6335634B1 (en) | 1997-10-16 | 2002-01-01 | Srinivas T. Reddy | Circuitry and methods for internal interconnection of programmable logic devices |
US6107825A (en) * | 1997-10-16 | 2000-08-22 | Altera Corporation | Input/output circuitry for programmable logic devices |
US6384625B1 (en) | 1997-10-16 | 2002-05-07 | Altera Corporation | Programmable logic devices with enhanced multiplexing capabilities |
US6255850B1 (en) | 1997-10-28 | 2001-07-03 | Altera Corporation | Integrated circuit with both clamp protection and high impedance protection from input overshoot |
US6185724B1 (en) | 1997-12-02 | 2001-02-06 | Xilinx, Inc. | Template-based simulated annealing move-set that improves FPGA architectural feature utilization |
US6069490A (en) * | 1997-12-02 | 2000-05-30 | Xilinx, Inc. | Routing architecture using a direct connect routing mesh |
US6127843A (en) * | 1997-12-22 | 2000-10-03 | Vantis Corporation | Dual port SRAM memory for run time use in FPGA integrated circuits |
US6130551A (en) * | 1998-01-19 | 2000-10-10 | Vantis Corporation | Synthesis-friendly FPGA architecture with variable length and variable timing interconnect |
US6084427A (en) * | 1998-05-19 | 2000-07-04 | Altera Corporation | Programmable logic devices with enhanced multiplexing capabilities |
US6265926B1 (en) | 1998-05-27 | 2001-07-24 | Altera Corporation | Programmable PCI overvoltage input clamp |
US6467017B1 (en) | 1998-06-23 | 2002-10-15 | Altera Corporation | Programmable logic device having embedded dual-port random access memory configurable as single-port memory |
US6344755B1 (en) | 1998-07-14 | 2002-02-05 | Altera Corporation | Programmable logic device with redundant circuitry |
US6201404B1 (en) | 1998-07-14 | 2001-03-13 | Altera Corporation | Programmable logic device with redundant circuitry |
US6184707B1 (en) | 1998-10-07 | 2001-02-06 | Altera Corporation | Look-up table based logic element with complete permutability of the inputs to the secondary signals |
US6507216B1 (en) | 1998-11-18 | 2003-01-14 | Altera Corporation | Efficient arrangement of interconnection resources on programmable logic devices |
US6879183B2 (en) | 1998-11-18 | 2005-04-12 | Altera Corporation | Programmable logic device architectures with super-regions having logic regions and a memory region |
US6480028B2 (en) | 1998-11-18 | 2002-11-12 | Altera Corporation | Programmable logic device architectures with super-regions having logic regions and memory region |
US6670825B1 (en) | 1998-11-18 | 2003-12-30 | Altera Corporation | Efficient arrangement of interconnection resources on programmable logic devices |
US6624658B2 (en) | 1999-02-04 | 2003-09-23 | Advantage Logic, Inc. | Method and apparatus for universal program controlled bus architecture |
US20030210073A1 (en) * | 1999-03-04 | 2003-11-13 | Tony Ngai | Interconnection and input/output resources for programmable logic integrated circuit devices |
US6989689B2 (en) | 1999-03-04 | 2006-01-24 | Altera Corporation | Interconnection and input/output resources for programmable logic integrated circuit devices |
US7839167B2 (en) | 1999-03-04 | 2010-11-23 | Altera Corporation | Interconnection and input/output resources for programmable logic integrated circuit devices |
US6407576B1 (en) | 1999-03-04 | 2002-06-18 | Altera Corporation | Interconnection and input/output resources for programmable logic integrated circuit devices |
US7317332B2 (en) | 1999-03-04 | 2008-01-08 | Altera Corporation | Interconnection and input/output resources for programmable logic integrated circuit devices |
US7492188B2 (en) | 1999-03-04 | 2009-02-17 | Altera Corporation | Interconnection and input/output resources for programmable logic integrated circuit devices |
US20040251930A1 (en) * | 1999-03-04 | 2004-12-16 | Altera Corporation | Interconnection and input/output resources for programmable logic integrated circuit devices |
US6894533B2 (en) | 1999-03-04 | 2005-05-17 | Altera Corporation | Interconnection and input/output resources for programmable logic integrated circuit devices |
US6614261B2 (en) | 1999-03-04 | 2003-09-02 | Altera Corp | Interconnection and input/output resources for programable logic integrated circuit devices |
EP2288030A1 (en) | 1999-03-24 | 2011-02-23 | Altera Corporation | I/O cell configuration for multiple I/O standards |
US6424567B1 (en) | 1999-07-07 | 2002-07-23 | Philips Electronics North America Corporation | Fast reconfigurable programmable device |
US6320412B1 (en) | 1999-12-20 | 2001-11-20 | Btr, Inc. C/O Corporate Trust Co. | Architecture and interconnect for programmable logic circuits |
US6633181B1 (en) | 1999-12-30 | 2003-10-14 | Stretch, Inc. | Multi-scale programmable array |
US7062520B2 (en) | 1999-12-30 | 2006-06-13 | Stretch, Inc. | Multi-scale programmable array |
US20010049816A1 (en) * | 1999-12-30 | 2001-12-06 | Adaptive Silicon, Inc. | Multi-scale programmable array |
US6657457B1 (en) | 2000-03-15 | 2003-12-02 | Intel Corporation | Data transfer on reconfigurable chip |
US7446561B2 (en) | 2000-06-12 | 2008-11-04 | Altera Corporation | I/O circuitry shared between processor and programmable logic portions of an integrated circuit |
US6980024B1 (en) | 2000-06-12 | 2005-12-27 | Altera Corporation | I/O circuitry shared between processor and programmable logic portions of an integrated circuit |
US6803785B1 (en) | 2000-06-12 | 2004-10-12 | Altera Corporation | I/O circuitry shared between processor and programmable logic portions of an integrated circuit |
US6961884B1 (en) | 2000-06-12 | 2005-11-01 | Altera Corporation | JTAG mirroring circuitry and methods |
US7340596B1 (en) | 2000-06-12 | 2008-03-04 | Altera Corporation | Embedded processor with watchdog timer for programmable logic |
US20060186917A1 (en) * | 2000-06-12 | 2006-08-24 | Altera Corporation, A Corporation Of Delaware | I/O circuitry shared between processor and programmable logic portions of an integrated circuit |
US7350178B1 (en) | 2000-06-12 | 2008-03-25 | Altera Corporation | Embedded processor with watchdog timer for programmable logic |
US7484081B1 (en) | 2000-10-10 | 2009-01-27 | Altera Corporation | Method and apparatus for protecting designs in SRAM-based programmable logic devices |
US6720796B1 (en) | 2001-05-06 | 2004-04-13 | Altera Corporation | Multiple size memories in a programmable logic device |
US6531887B2 (en) | 2001-06-01 | 2003-03-11 | Macronix International Co., Ltd. | One cell programmable switch using non-volatile cell |
US6788111B2 (en) | 2001-06-01 | 2004-09-07 | Macronix International Co., Ltd. | One cell programmable switch using non-volatile cell |
US6577161B2 (en) | 2001-06-01 | 2003-06-10 | Macronix International Co., Ltd. | One cell programmable switch using non-volatile cell with unidirectional and bidirectional states |
US6545504B2 (en) | 2001-06-01 | 2003-04-08 | Macronix International Co., Ltd. | Four state programmable interconnect device for bus line and I/O pad |
US9473145B2 (en) | 2001-08-29 | 2016-10-18 | Altera Corporation | Programmable high-speed I/O interface |
US8487665B2 (en) | 2001-08-29 | 2013-07-16 | Altera Corporation | Programmable high-speed interface |
US8829948B2 (en) | 2001-08-29 | 2014-09-09 | Altera Corporation | Programmable high-speed I/O interface |
US6594810B1 (en) | 2001-10-04 | 2003-07-15 | M2000 | Reconfigurable integrated circuit with a scalable architecture |
US6874136B2 (en) | 2002-01-10 | 2005-03-29 | M2000 | Crossbar device with reduced parasitic capacitive loading and usage of crossbar devices in reconfigurable circuits |
EP2110948A1 (en) | 2002-01-10 | 2009-10-21 | M 2000 Parc Burospace | Reconfigurable circuit comprising a plurality of crossbar devices |
US7424658B1 (en) | 2002-07-01 | 2008-09-09 | Altera Corporation | Method and apparatus for testing integrated circuits |
US20050127944A1 (en) * | 2002-10-24 | 2005-06-16 | Altera Corporation | Versatile logic element and logic array block |
US7671626B1 (en) | 2002-10-24 | 2010-03-02 | Altera Corporation | Versatile logic element and logic array block |
US20070252617A1 (en) * | 2002-10-24 | 2007-11-01 | Altera Corporation | Versatile logic element and logic array block |
US7432734B2 (en) | 2002-10-24 | 2008-10-07 | Altera Corporation | Versatile logic element and logic array block |
US7218133B2 (en) | 2002-10-24 | 2007-05-15 | Altera Corporation | Versatile logic element and logic array block |
US6937064B1 (en) | 2002-10-24 | 2005-08-30 | Altera Corporation | Versatile logic element and logic array block |
US7111110B1 (en) | 2002-12-10 | 2006-09-19 | Altera Corporation | Versatile RAM for programmable logic device |
US7480763B2 (en) | 2002-12-10 | 2009-01-20 | Altera Corporation | Versatile RAM for a programmable logic device |
US6798240B1 (en) | 2003-01-24 | 2004-09-28 | Altera Corporation | Logic circuitry with shared lookup table |
US20050030062A1 (en) * | 2003-01-24 | 2005-02-10 | Bruce Pedersen | Logic circuitry with shared lookup table |
US7317330B2 (en) | 2003-01-24 | 2008-01-08 | Altera Corporation | Logic circuitry with shared lookup table |
US20060017460A1 (en) * | 2003-02-10 | 2006-01-26 | Altera Corporation | Fracturable lookup table and logic element |
US20070222477A1 (en) * | 2003-02-10 | 2007-09-27 | Altera Corporation | Fracturable lookup table and logic element |
US7312632B2 (en) | 2003-02-10 | 2007-12-25 | Altera Corporation | Fracturable lookup table and logic element |
US8217678B1 (en) | 2003-02-10 | 2012-07-10 | Altera Corporation | Fracturable lookup table and logic element |
US6943580B2 (en) | 2003-02-10 | 2005-09-13 | Altera Corporation | Fracturable lookup table and logic element |
US7323902B2 (en) | 2003-02-10 | 2008-01-29 | Altera Corporation | Fracturable lookup table and logic element |
US7800401B1 (en) | 2003-02-10 | 2010-09-21 | Altera Corporation | Fracturable lookup table and logic element |
US6888373B2 (en) | 2003-02-11 | 2005-05-03 | Altera Corporation | Fracturable incomplete look up table for area efficient logic elements |
US20040155676A1 (en) * | 2003-02-11 | 2004-08-12 | Sinan Kaptanoglu | Fracturable incomplete look up table for area efficient logic elements |
US7030650B1 (en) | 2003-02-11 | 2006-04-18 | Altera Corporation | Fracturable incomplete look up table area efficient logic elements |
US20040193852A1 (en) * | 2003-03-31 | 2004-09-30 | Johnson Scott D. | Extension adapter |
US20050114565A1 (en) * | 2003-03-31 | 2005-05-26 | Stretch, Inc. | Systems and methods for selecting input/output configuration in an integrated circuit |
US8001266B1 (en) | 2003-03-31 | 2011-08-16 | Stretch, Inc. | Configuring a multi-processor system |
US7581081B2 (en) | 2003-03-31 | 2009-08-25 | Stretch, Inc. | Systems and methods for software extensible multi-processing |
US7590829B2 (en) | 2003-03-31 | 2009-09-15 | Stretch, Inc. | Extension adapter |
US7613900B2 (en) | 2003-03-31 | 2009-11-03 | Stretch, Inc. | Systems and methods for selecting input/output configuration in an integrated circuit |
US20040194048A1 (en) * | 2003-03-31 | 2004-09-30 | Arnold Jeffrey M. | System and method for efficiently mapping heterogeneous objects onto an array of heterogeneous programmable logic resources |
US7000211B2 (en) | 2003-03-31 | 2006-02-14 | Stretch, Inc. | System and method for efficiently mapping heterogeneous objects onto an array of heterogeneous programmable logic resources |
US6954845B2 (en) | 2003-07-29 | 2005-10-11 | Stretch, Inc. | Reconfigurable instruction set computing |
US20050027970A1 (en) * | 2003-07-29 | 2005-02-03 | Arnold Jeffrey Mark | Reconfigurable instruction set computing |
US7421561B2 (en) | 2003-07-29 | 2008-09-02 | Stretch, Inc. | Instruction set for efficient bit stream and byte stream I/O |
US20050169550A1 (en) * | 2003-07-29 | 2005-08-04 | Arnold Jeffrey M. | Video processing system with reconfigurable instructions |
US20050273581A1 (en) * | 2003-07-29 | 2005-12-08 | Stretch, Inc. | Programmable logic configuration for instruction extensions |
US7610475B2 (en) | 2003-07-29 | 2009-10-27 | Stretch, Inc. | Programmable logic configuration for instruction extensions |
US20060259747A1 (en) * | 2003-07-29 | 2006-11-16 | Stretch, Inc. | Long instruction word processing with instruction extensions |
US20050027944A1 (en) * | 2003-07-29 | 2005-02-03 | Williams Kenneth Mark | Instruction set for efficient bit stream and byte stream I/O |
US7373642B2 (en) | 2003-07-29 | 2008-05-13 | Stretch, Inc. | Defining instruction extensions in a standard programming language |
US7418575B2 (en) | 2003-07-29 | 2008-08-26 | Stretch, Inc. | Long instruction word processing with instruction extensions |
US7284114B2 (en) | 2003-07-29 | 2007-10-16 | Stretch, Inc. | Video processing system with reconfigurable instructions |
US20050027971A1 (en) * | 2003-07-29 | 2005-02-03 | Williams Kenneth M. | Defining instruction extensions in a standard programming language |
WO2005036353A3 (en) * | 2003-10-07 | 2005-06-16 | Univ Florida | Method and apparatus for a chaotic computing module |
US20060091905A1 (en) * | 2003-10-07 | 2006-05-04 | University Of Florida Research Foundation, Inc. | Method and apparatus for a chaotic computing module |
US7096437B2 (en) | 2003-10-07 | 2006-08-22 | University Of Florida Research Foundation, Inc. | Method and apparatus for a chaotic computing module using threshold reference signal implementation |
US8091062B2 (en) | 2003-10-07 | 2012-01-03 | University Of Florida Research Foundation, Inc. | Logic circuits having dynamically configurable logic gate arrays |
US20100318506A1 (en) * | 2003-10-07 | 2010-12-16 | Control Dynamics, Inc. | Non-linear dynamical search engine |
US20080278196A1 (en) * | 2003-10-07 | 2008-11-13 | Ditto William L | Logic circuits having dynamically configurable logic gate arrays |
US20050073337A1 (en) * | 2003-10-07 | 2005-04-07 | University Of Florida | Method and apparatus for a chaotic computing module |
US8250055B2 (en) | 2003-10-07 | 2012-08-21 | University Of Florida Research Foundation, Inc. | Non-linear dynamical search engine |
US7863937B2 (en) | 2003-10-07 | 2011-01-04 | University Of Florida Research Foundation, Inc. | Logic based on the evolution of nonlinear dynamical systems |
US7415683B2 (en) | 2003-10-07 | 2008-08-19 | University Of Florida Research Foundation, Inc. | Method and apparatus for a chaotic computing module |
US20100219858A1 (en) * | 2003-10-07 | 2010-09-02 | University Of Florida Research Foundation, Inc. | Logic based on the evolution of nonlinear dynamical systems |
US20080278678A1 (en) * | 2003-10-09 | 2008-11-13 | Howell Thomas A | Eyeglasses with user monitoring |
US7185035B1 (en) | 2003-10-23 | 2007-02-27 | Altera Corporation | Arithmetic structures for programmable logic devices |
US7565388B1 (en) | 2003-11-21 | 2009-07-21 | Altera Corporation | Logic cell supporting addition of three binary words |
US8237465B1 (en) | 2004-03-25 | 2012-08-07 | Altera Corporation | Omnibus logic element for packing or fracturing |
US9496875B1 (en) | 2004-03-25 | 2016-11-15 | Altera Corporation | Omnibus logic element |
US8878567B1 (en) | 2004-03-25 | 2014-11-04 | Altera Corporation | Omnibus logic element |
US8593174B1 (en) | 2004-03-25 | 2013-11-26 | Altera Corporation | Omnibus logic element for packing or fracturing |
US7671625B1 (en) | 2004-03-25 | 2010-03-02 | Altera Corporation | Omnibus logic element |
US10177766B1 (en) | 2004-03-25 | 2019-01-08 | Altera Corporation | Omnibus logic element |
US7911230B1 (en) | 2004-03-25 | 2011-03-22 | Altera Corporation | Omnibus logic element for packing or fracturing |
US7256614B2 (en) | 2004-03-30 | 2007-08-14 | Advantage Logic, Inc. | Scalable non-blocking switching network for programmable logic |
US7557613B2 (en) | 2004-03-30 | 2009-07-07 | Advantage Logic, Inc. | Scalable non-blocking switching network for programmable logic |
US7986163B2 (en) | 2004-03-30 | 2011-07-26 | Advantage Logic, Inc. | Scalable non-blocking switching network for programmable logic |
US20090273368A1 (en) * | 2004-03-30 | 2009-11-05 | Pani Peter M | Scalable non-blocking switching network for programmable logic |
US6975139B2 (en) | 2004-03-30 | 2005-12-13 | Advantage Logic, Inc. | Scalable non-blocking switching network for programmable logic |
US8242807B2 (en) | 2004-03-30 | 2012-08-14 | Advantage Logic, Inc. | Scalable non-blocking switching network for programmable logic |
US7863932B2 (en) | 2004-03-30 | 2011-01-04 | Advantage Logic, Inc. | Scalable non-blocking switching network for programmable logic |
US20050218928A1 (en) * | 2004-03-30 | 2005-10-06 | Pani Peter M | Scalable non-blocking switching network for programmable logic |
US7768302B2 (en) | 2004-03-30 | 2010-08-03 | Advantage Logic, Inc. | Scalable non-blocking switching network for programmable logic |
US20070268041A1 (en) * | 2004-03-30 | 2007-11-22 | Pani Peter M | Scalable non-blocking switching network for programmable logic |
US8698519B2 (en) | 2004-03-30 | 2014-04-15 | Advantage Logic, Inc. | Scalable non-blocking switching network for programmable logic |
US20100244895A1 (en) * | 2004-03-30 | 2010-09-30 | Pani Peter M | Scalable non-blocking switching network for programmable logic |
US7417457B2 (en) | 2004-03-30 | 2008-08-26 | Advantage Logic, Inc. | Scalable non-blocking switching network for programmable logic |
US7030652B1 (en) | 2004-04-23 | 2006-04-18 | Altera Corporation | LUT-based logic element with support for Shannon decomposition and associated method |
US20060023704A1 (en) * | 2004-07-29 | 2006-02-02 | Pani Peter M | Interconnection fabric using switching networks in hierarchy |
US7460529B2 (en) | 2004-07-29 | 2008-12-02 | Advantage Logic, Inc. | Interconnection fabric using switching networks in hierarchy |
US8566616B1 (en) | 2004-09-10 | 2013-10-22 | Altera Corporation | Method and apparatus for protecting designs in SRAM-based programmable logic devices and the like |
US8612772B1 (en) | 2004-09-10 | 2013-12-17 | Altera Corporation | Security core using soft key |
US7368944B1 (en) | 2005-01-21 | 2008-05-06 | Altera Corporation | Organizations of logic modules in programmable logic devices |
US7176718B1 (en) | 2005-01-21 | 2007-02-13 | Altera Corporation | Organizations of logic modules in programmable logic devices |
US7478261B2 (en) | 2005-09-13 | 2009-01-13 | M2000 | Reconfigurable circuit with redundant reconfigurable cluster(s) |
US20070057693A1 (en) * | 2005-09-13 | 2007-03-15 | M2000 | Reconfigurable circuit with redundant reconfigurable cluster(S) |
US8010826B2 (en) | 2005-09-13 | 2011-08-30 | Meta Systems | Reconfigurable circuit with redundant reconfigurable cluster(s) |
US20100095147A1 (en) * | 2005-09-13 | 2010-04-15 | Abound Logic, S.A.S. | Reconfigurable circuit with redundant reconfigurable cluster(s) |
US7529998B2 (en) | 2005-11-23 | 2009-05-05 | M2000 Sa. | Runtime reconfiguration of reconfigurable circuits |
US7275196B2 (en) | 2005-11-23 | 2007-09-25 | M2000 S.A. | Runtime reconfiguration of reconfigurable circuits |
US20070118783A1 (en) * | 2005-11-23 | 2007-05-24 | M2000 Inc. | Runtime reconfiguration of reconfigurable circuits |
US7679401B1 (en) * | 2005-12-01 | 2010-03-16 | Tabula, Inc. | User registers implemented with routing circuits in a configurable IC |
US8089300B2 (en) * | 2005-12-01 | 2012-01-03 | Tabula, Inc. | Users registers implemented with routing circuits in a configurable IC |
US8674723B2 (en) * | 2005-12-01 | 2014-03-18 | Tabula, Inc. | User registers implemented with routing circuits in a configurable IC |
US20120139580A1 (en) * | 2005-12-01 | 2012-06-07 | Jason Redgrave | User registers implemented with routing circuits in a configurable ic |
US7423453B1 (en) | 2006-01-20 | 2008-09-09 | Advantage Logic, Inc. | Efficient integrated circuit layout scheme to implement a scalable switching network used in interconnection fabric |
US7453285B2 (en) | 2006-12-22 | 2008-11-18 | Chaologix, Inc. | Dynamically configurable logic gate using a non-linear element |
US20080150578A1 (en) * | 2006-12-22 | 2008-06-26 | Chaologix, Inc. | Dynamically configurable logic gate using a non-linear element |
US7508231B2 (en) | 2007-03-09 | 2009-03-24 | Altera Corporation | Programmable logic device having redundancy with logic element granularity |
US7456653B2 (en) | 2007-03-09 | 2008-11-25 | Altera Corporation | Programmable logic device having logic array block interconnect lines that can interconnect logic elements in different logic blocks |
US20080218208A1 (en) * | 2007-03-09 | 2008-09-11 | Altera Corporation | Programmable logic device having logic array block interconnect lines that can interconnect logic elements in different logic blocks |
US20090256590A1 (en) * | 2008-04-10 | 2009-10-15 | Silicon Storage Technology, Inc. | Storage element for controlling a logic circuit, and a logic device having an array of such storage elements |
US7701248B2 (en) | 2008-04-10 | 2010-04-20 | Silicon Storage Technology, Inc. | Storage element for controlling a logic circuit, and a logic device having an array of such storage elements |
US20100134143A1 (en) * | 2008-12-03 | 2010-06-03 | Pani Peter M | Permutable switching network with enhanced multicasting signals routing for interconnection fabric |
US7714611B1 (en) | 2008-12-03 | 2010-05-11 | Advantage Logic, Inc. | Permutable switching network with enhanced multicasting signals routing for interconnection fabric |
US8106682B2 (en) | 2008-12-03 | 2012-01-31 | Advantage Logic, Inc. | Permutable switching network with enhanced interconnectivity for multicasting signals |
US7876126B2 (en) | 2008-12-03 | 2011-01-25 | Advantage Logic, Inc. | Permutable switching network with enhanced interconnectivity for multicasting signals |
US20110084728A1 (en) * | 2008-12-03 | 2011-04-14 | Pani Peter M | Permutable switching network with enhanced interconnectivity for multicasting signals |
US20100141298A1 (en) * | 2008-12-03 | 2010-06-10 | Pani Peter M | Permutable switching network with enhanced multicasting signals routing for interconnection fabric |
US7705629B1 (en) | 2008-12-03 | 2010-04-27 | Advantage Logic, Inc. | Permutable switching network with enhanced interconnectivity for multicasting signals |
US8456192B2 (en) | 2008-12-03 | 2013-06-04 | Advantage Logic, Inc. | Permutable switching network with enhanced interconnectivity for multicasting signals |
US20100156461A1 (en) * | 2008-12-03 | 2010-06-24 | Pani Peter M | Permutable switching network with enhanced interconnectivity for multicasting signals |
US8981814B2 (en) | 2008-12-03 | 2015-03-17 | Advantage Logic, Inc. | Permutable switching network with enhanced interconnectivity for multicasting signals |
US7777519B2 (en) | 2008-12-03 | 2010-08-17 | Advantage Logic, Inc. | Permutable switching network with enhanced multicasting signals routing for interconnection fabric |
US7973566B2 (en) | 2009-02-27 | 2011-07-05 | University Of Florida Research Foundation, Inc. | Logic based on the evolution of nonlinear dynamical systems |
US20110062986A1 (en) * | 2009-02-27 | 2011-03-17 | University Of Florida Research Foundation, Inc. | Logic based on the evolution of nonlinear dynamical systems |
US7924059B2 (en) | 2009-02-27 | 2011-04-12 | University Of Florida Research Foundation, Inc. | Reconfigurable and reliable logic circuit elements that exploit nonlinearity and noise |
US20100219862A1 (en) * | 2009-02-27 | 2010-09-02 | University Of Florida Research Foundation, Inc. | Reconfigurable and reliable logic circuit elements that exploit nonlinearity and noise |
US20100327907A1 (en) * | 2009-06-24 | 2010-12-30 | Ting Benjamin S | Enhanced permutable switching network with multicasting signals for interconnection fabric |
US8395415B2 (en) | 2009-06-24 | 2013-03-12 | Advantage Logic, Inc. | Enhanced permutable switching network with multicasting signals for interconnection fabric |
US7999570B2 (en) | 2009-06-24 | 2011-08-16 | Advantage Logic, Inc. | Enhanced permutable switching network with multicasting signals for interconnection fabric |
US9312861B2 (en) | 2009-10-14 | 2016-04-12 | Chaologix, Inc. | Protecting data from decryption from power signature analysis in secure applications |
US8330493B2 (en) | 2009-10-14 | 2012-12-11 | Chaologix, Inc. | High utilization universal logic array with variable circuit topology and logistic map circuit to realize a variety of logic gates with constant power signatures |
US8860465B2 (en) | 2009-10-14 | 2014-10-14 | Chaologix, Inc. | Protecting data from decryption from power signature analysis in secure applications |
US20110085662A1 (en) * | 2009-10-14 | 2011-04-14 | Chaologix, Inc. | High utilization universal logic array with variable circuit topology and logistic map circuit to realize a variety of logic gates with constant power signatures |
US8736299B1 (en) | 2011-04-29 | 2014-05-27 | Altera Corporation | Setting security features of programmable logic devices |
US9111121B2 (en) | 2011-04-29 | 2015-08-18 | Altera Corporation | Method and apparatus for securing a programmable device using a kill switch |
US9152822B2 (en) | 2011-04-29 | 2015-10-06 | Altera Corporation | Method and apparatus for securing programming data of a programmable device |
US8461863B2 (en) | 2011-04-29 | 2013-06-11 | Altera Corporation | Method and apparatus for securing a programmable device using a kill switch |
US8719957B2 (en) | 2011-04-29 | 2014-05-06 | Altera Corporation | Systems and methods for detecting and mitigating programmable logic device tampering |
US9767321B1 (en) | 2011-04-29 | 2017-09-19 | Altera Corporation | Setting security features of programmable logic devices |
US9852315B2 (en) | 2011-04-29 | 2017-12-26 | Altera Corporation | Systems and methods for detecting and mitigating programmable logic device tampering |
US8627105B2 (en) | 2011-04-29 | 2014-01-07 | Altera Corporation | Method and apparatus for securing programming data of a programmable device |
US10592699B2 (en) | 2011-04-29 | 2020-03-17 | Altera Corporation | Systems and methods for detecting and mitigating of programmable logic device tampering |
US11436382B2 (en) | 2011-04-29 | 2022-09-06 | Altera Corporation | Systems and methods for detecting and mitigating programmable logic device tampering |
US9026873B2 (en) | 2013-07-23 | 2015-05-05 | Altera Coporation | Method and apparatus for securing configuration scan chains of a programmable device |
Also Published As
Publication number | Publication date |
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DE69223010D1 (en) | 1997-12-11 |
EP0530985A2 (en) | 1993-03-10 |
EP0786871A3 (en) | 1998-02-04 |
EP0530985A3 (en) | 1993-12-08 |
EP0786871B1 (en) | 2001-12-19 |
JPH06318638A (en) | 1994-11-15 |
US5376844A (en) | 1994-12-27 |
EP1134896A2 (en) | 2001-09-19 |
JP3488258B2 (en) | 2004-01-19 |
US5485103A (en) | 1996-01-16 |
EP0786871A2 (en) | 1997-07-30 |
EP0530985B1 (en) | 1997-11-05 |
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