Búsqueda Imágenes Maps Play YouTube Noticias Gmail Drive Más »
Iniciar sesión
Usuarios de lectores de pantalla: deben hacer clic en este enlace para utilizar el modo de accesibilidad. Este modo tiene las mismas funciones esenciales pero funciona mejor con el lector.

Patentes

  1. Búsqueda avanzada de patentes
Número de publicaciónUS5330617 A
Tipo de publicaciónConcesión
Número de solicitudUS 07/792,262
Fecha de publicación19 Jul 1994
Fecha de presentación15 Nov 1991
Fecha de prioridad16 Nov 1990
TarifaPagadas
También publicado comoDE69119871D1, DE69119871T2, EP0487380A1, EP0487380B1
Número de publicación07792262, 792262, US 5330617 A, US 5330617A, US-A-5330617, US5330617 A, US5330617A
InventoresMichel Haond
Cesionario originalFrance Telecom
Exportar citaBiBTeX, EndNote, RefMan
Enlaces externos: USPTO, Cesión de USPTO, Espacenet
Method for etching integrated-circuit layers to a fixed depth and corresponding integrated circuit
US 5330617 A
Resumen
The invention relates to a method for etching an integrated-circuit layer to a fixed depth. The method consists in depositing onto the layer to be etched a protective layer forming a stop layer and then onto the latter a reference layer made of a material compatible with that of the layer to be etched the thickness of the reference layer being proportional to the depth of the etch to be produced. A mask is applied to the reference layer and the etching of this layer is carried out by chemical attack until encountering the stop layer. After removal of the mask and of the stop layer, in the etching zone, the reference layer and the layer of material to be etched 1 are simultaneously subjected to a chemical attack until encountering the stop layer. An etch having the plane dimensions of the etch of the reference layer and a depth proportional to the thickness of the reference layer is thus created. Application to the etching of integrated-circuit layers or to the creation of inverted-T-shaped elements.
Imágenes(4)
Previous page
Next page
Reclamaciones(6)
I claim:
1. A method for etching a layer of material of an integrated circuit, over a fixed depth, said method consisting of:
a) depositing onto said layer of material designated as the layer to be etched, a protective layer forming a stop layer,
b) depositing onto said stop layer a reference layer made of a material identical to that of the layer to be etched and whose thickness is made substantially equal to the depth of the etch to be produced in said layer to be etched,
c) applying to said reference layer an etch mask having the plane dimensions of the etch to be produced in said layer to be etched,
d) carrying out the etching by chemical attack, dry or wet, of said reference layer by the intermediary of the etch mask until encountering and exposing a portion of the stop layer in a zone for etching the reference layer,
e) removing said mask and said exposed stop layer;
f) simultaneously subjecting the reference layer, remaining stop layer and the layer of material to be etched in the region of said zone liberated by the removal of the exposed stop layer to a chemical attack, dry or wet, until the remaining stop layer underneath said reference layer is exposed, the reference layer and the remaining stop layer forming an auxiliary mask for the layer to be etched so as to create, in the layer to be etched, an etch having the plane dimensions of the etch of the reference layer and a depth substantially proportional to the thickness of this reference layer.
2. The method as claimed in claim 1,
wherein the layer to be etched in constituted by a material included in the group SiO.sub.2, Si.sub.3 N.sub.4, Si.
3. The method as claimed in claim 1,
wherein the thickness dimension of the reference layer is made equal to a value proportional to the dimension, in the same direction, of the etch to be produced, the ratio of proportionality of these dimensions being made equal, for compatible materials constituting said reference layer, and for appropriate etch modes or etchants with respect to the layer of material to be etched and to the reference layer, to the ratio of the corresponding etch rates.
4. The method as claimed in claim 3, wherein, when the layer to be etched and the reference layer are made of identical material, said dimensions are identical, said reference layer and said layer to be etched being subjected, with a view to their etching, to the same etch modes or etchants.
5. The method as claimed in either of claims 3 and 4, wherein the etch modes or etchants are chosen from among the agents SF.sub.6, C.sub.2 F.sub.6, HCl, Cl.sub.2, CHF.sub.3, CF.sub.4, O.sub.2.
6. A method for providing a raised element into a layer of material of an integrated circuit comprising:
a) depositing onto said layer of material designated as the layer to be etched, a protective layer forming a lower stop layer,
b) depositing onto said lower stop layer a lower reference layer made of a material identical to that of the layer to be etched and whose thickness is made substantially equal to the depth of the etch to be produced in said layer to be etched,
c) depositing onto said lower reference layer an upper stop layer,
d) depositing onto said second stop layer an upper reference layer of the same type and same thickness as said lower reference layer,
e) applying to said upper reference layer an etch mask,
f) carrying out etching by chemical attack, dry or wet, of said upper reference layer by the intermediary of the etch mask until the lower reference layer is exposed,
g) removing the etch mask, and
h) simultaneously subjecting the remaining upper reference layer, remaining upper stop layer and the exposed lower reference layer to a chemical attack, dry or wet, until the remaining upper stop layer underneath said upper reference layer is exposed so as to form said raised element from said lower reference layer underneath said remaining upper stop layer.
Descripción

The invention relates to a process for etching integrated-circuit layers to a fixed depth and to the corresponding integrated circuit.

The manufacture of an integrated circuit results from a sequence of elementary steps such as, for example, photolithography, etching, ion implantation and thermal treatment steps.

As the processes for the manufacture of ever denser and smaller and smaller integrated circuits have evolved, the implementation of each elementary step becomes more delicate and requires increased precision and reproducibility capability.

In sub-micron processes, the fixed-time pattern etching operations, that is to say the etching processes in which the etch depth is determined by the time for implementing the etching process for a material of specified nature and for a given etch mode or chemical etchant with respect to this material, multiply. This is the case, especially, for isolation trench etching operations or for the manufacture of polycrystalline silicon grids called "inverted T"-type grids.

Despite all the precautions taken for implementing the abovementioned processes, the latter cannot expect to achieve the accuracy and reproducibility qualities mentioned hereinabove, in particular because of the inadequacy of this type of process in switching or passing from etch state to non-etch state, it being impossible to expect such switching to be instantaneous, which has the effect of introducing a zone of uncertainty, which is non-zero, in the depth effectively achieved by the etching operation, with risk of local or general non-uniformity of the physical characteristics of the materials to be etched and therefore of their etch rates from one integrated circuit to another, it being well known that these etch parameters depend on the operating conditions even in the case of integrated circuits of the same type.

The object of the present invention is to overcome the abovementioned drawbacks and, especially, to increase substantially the precision of the etching of integrated-circuit layers in the sub-micron domain.

Another object of the present invention is to increase substantially the reproducibility capability from one integrated circuit to another of the same type.

A further object of the present invention is to implement a method for etching a layer of material of an integrated circuit to a fixed depth and of the corresponding integrated circuit.

The method for etching a layer of material of an integrated circuit, the layer to be etched, over a fixed depth, which is a subject of the present invention, is noteworthy in that it consists in depositing onto the layer of material, the layer to be etched, a protective layer forming a stop layer and in depositing onto this stop layer a reference layer made of a material compatible with that of the layer to be etched and whose thickness is made substantially proportional to the thickness of the etch to be produced in said layer to be etched. An etch mask having the plane dimensions of the etch to be produced in the layer to be etched is applied to the reference layer and the etching of this layer is carried out by chemical attack by the intermediary of the etch mask, until encountering the stop layer in the zone for etching the reference layer. The mask and the stop layer in the zone for etching the reference layer are removed, and the reference layer and the layer of material to be etched are simultaneously subjected to a chemical attack until encountering the stop layer, the reference layer and the stop layer forming an auxiliary mask for the layer to be etched so as to create, in the layer to be etched, an etch having the plane dimensions of the etch of the reference layer and a depth substantially proportional to the thickness of this reference layer.

According to a first embodiment, the integrated circuit, which is a subject of the present invention, is noteworthy in that it comprises at least, in a substrate of specified material, one channel-type zone, the free surface of said substrate in the vicinity of said channel-type zone comprising a covering of a layer made of a different material from that of the substrate.

According to a second embodiment, the integrated circuit, which is a subject of the invention, is note-worthy in that it comprises, at least on a substrate of specified material, one projection-type zone, this projection-type zone being formed by the same material superposed on the surface of the substrate and having substantially the shape of an inverted T.

BRIEF DESCRIPTION OF THE DRAWINGS

A more detailed description of the subject of the present invention will now be given in conjunction with the description and with the drawings hereinbelow in which:

FIGS. 1(a)-1(e) illustrates the implementation of the method, which is a subject of the invention, for etching to a fixed depth,

FIGS. 2(a)-2(d) illustrate the implementation of the method, which is a subject of the invention, more particularly intended for producing inverted T-shaped elements,

FIG. 3 shows a view, in cross-section, of an integrated circuit in which the etching to a fixed depth has been carried out in accordance with the method according to the invention,

FIG. 4 shows a view, in cross-section, of an integrated circuit in which an inverted T-shaped element has been produced in accordance with the method according to the invention,

FIGS. 5(a) and 5(b) shows a view, in cross-section, of an integrated circuit in which an element has been produced by means of a variant of the method according to the invention such as illustrated in FIG. 2.

DETAILED DESCRIPTION OF THE INVENTION

The method for etching a layer of material of an integrated circuit to a fixed depth, according to the present invention, will first of all be described in conjunction with FIGS. 1(a)-1(e). According to the abovementioned Figure, the method according to the invention consists, as shown in of FIG. 1(a), in depositing a protective layer forming a stop layer, designated by 2, on the layer of material constituting the layer tobe etched 1.

Subsequently, as shown in FIG. 1b, the method according to the invention consists in depositing, on the stop layer 2, a layer called the reference layer, designated by 3, made of a material compatible with that of the layer to be etched 1. By material compatible with that of the layer to be etched 1, is understood any type of material capable of being simultaneously etched with the layer to be etched 1, under similar or identical operating conditions, as will be described later in the description.

According to a particular aspect of the method which is a subject of the invention, the thickness of the reference layer 3 is made substantially proportional to the depth of the etch to be produced in the layer to be etched 1. Of course, as will be described later in the description, it will be understood that the coefficient of proportionality connecting the values of the two respective thicknesses of the reference layer 3 and the depth of the etch to be produced is determined as a function of the operating conditions of the respective etching operations of these layers.

As has been furthermore shown FIG. 1(d), the method which is a subject of the invention then consists successively in applying to the reference layer 3 an etch mask 4 having the plane dimensions of the etch to be produced in the layer to be etched 1, and then in carrying out the etchingby chemical attack, dry or wet, of the reference layer 3 by the intermediary of the etch mask 4 until encountering the stop layer 2. The encounter with the stop layer is meant the encounter, in the zone for etching, of the reference layer 3.

As has then been shown by FIG. 1(d), the method according to the invention then consists in removing the etch mask 4 and the stop layer 2 in the zonefor etching the reference layer 3. The removal of the stop layer 2 may be carried out by chemical attack, dry or wet.

Subsequently, as shown by FIG. 1(e), the method which is a subject of the invention then consists in simultaneously subjecting the reference layer 3and the layer of material to be etched 1, in the region of the zone liberated by the removal of the stop layer 2 at the preceding step (e), toa simultaneous chemical attack. The simultaneous chemical attack of the reference layer 3 and of the layer of material to be etched 1 is continueduntil encountering the stop layer 2, subjacent to the reference layer 3, after disappearance of the latter.

During the operation carried out, as illustrated in FIG. 1(e), for the implementation of the method which is a subject of the invention, the reference layer 3 and the stop layer 2 form an auxiliary mask for the layer to be etched 1, so as to create in the abovementioned layer to be etched 1 an etch having the plane dimensions of the etch of the reference layer 3 and a depth substantially proportional to the thickness of the abovementioned reference layer 3.

In FIG. 1(f), there is shown the layer etched to a fixed depth of an integrated circuit, obtained by the implementation of the method represented by the steps shown in FIGS. 1(a)-1(e).

It will, of course, be understood that the operating conditions for etchingand for chemical attack of the reference layer 3 and of the layer to be etched 1 may then be chosen so as to obtain an etch depth of the layer to be etched 1 proportional to the thickness of the reference layer 3, this, for example, by fixing the relative etch rates of the reference layer 3 and of the layer to be etched 1 by a judicious choice of the etchants and of the operating conditions of these etchants.

In a simplified embodiment of the method which is a subject of the invention, the reference layer 3 may advantageously be constituted by a material identical to that of the layer to be etch 1. In this case, the reference layer 3 then has a thickness e substantially equal to the etch depth to be produced in the layer to be etched 1. Of course, the simultaneous etching of the reference layer 3 and of the layer to be etched 1 is carried out by the intermediary of the same etchants under substantially identical operating conditions.

A second embodiment of the method which is a subject of the invention will be advantageously described in the case where this method is implemented with a view to adding onto a layer of material of an integrated circuit a raised element of specified height. In general, the raised element of specified height added onto the layer of material of an integrated circuitis an inverted-T-type element, according to the usual terminology for this type of raised element in the technical domain of the production of integrated circuits.

As has been shown in FIG. 2(a), the method which is a subject of the invention then consists in successively repeating the steps a) previously described in conjunction with FIGS. 1(a) and 1(b), so as to form on the layer to be etched 1 a reference layer 31 and then a upper reference layer32. It will be noted that the reference layer 31 and the upper reference layer 32 are preferably layers of the same type and of the same thickness.Likewise, by repeating the preceding steps described in conjunction with Figures (a) and (b), the reference layer 31 and the upper reference layer 32 are associated respectively with their stop layer 21 and upper stop layer 22.

The method which is a subject of the present invention, as shown in FIG. 2(b), then consists in carrying out the steps previously described in relation with FIGS. 1(c) and (f), relative to the upper reference layer 32and to the upper stop layer 22, so as to form, in the region of the reference layer 31, a raised element to be added which forms an auxiliary mask for the reference layer 31.

The operation as shown by FIG. 2(b) is then followed, as shown by FIG. 2(c), by an operation then consisting in simultaneously subjecting the reference layer 31 and the raised element of the upper reference layer 32 forming an auxiliary mask, to a chemical attack until encountering the stop layer 21 so as to form in the region of the reference layer 31 the raised element added onto the layer of material to be etched 1.

It will, of course, be understood that the method which is a subject of thepresent invention, as much in its first embodiment such as illustrated in FIGS. 1(a)-1(f) as in its second embodiment such as illustrated in FIGS. 2(a) and 2(c), may be implemented in relation to any type of material normally used for the manufacture of integrated circuits and especially for layers to be etched 1 constituted by a material such as silicon oxide SiO.sub.2, silicon nitride Si.sub.3 N.sub.4 or single crystal or polycrystalline silicon Si.

Furthermore it will be noted that, in the case for implementing the method which is a subject of the invention such as illustratively shown by FIG. 2, the reference layer 31 and the upper reference layer 32 may be of the same type or of a different type.

In every case for implementing the method which is a subject of the invention, the thickness dimension of the reference layer with respect to the layer to be etched 1 or of the upper reference layer with respect to the reference layer 31 is made equal to a value proportional to the dimension in the same direction either of the etch to be produced in the layer to be etched 1 or, respectively, of the inverted-T element 31 to be added onto the layer to be etched 1. The proportionality ratio of these dimensions is then made equal, for compatible materials constituting the reference layer 3 or upper reference layer 32, for appropriate etch modes or chemical etchants with respect to the layer of material to be etched 1 and of the reference layer 3 or of the reference layer 31 and of the upperreference layer 32, to the ratio of the corresponding etch rates.

It will, of course, be understood that when the layer to be etched 1 and the reference layer 3, respectively, the reference layer 31 and the upper reference layer 32 are made from identical materials, the thickness dimensions e are then substantially identical. The reference layer and thelayer to be etched 1 or upper reference layer 32 and reference layer 31 arethen subjected, with a view to their etching, to the same etch modes or chemical etchants.

It will, in particular, be noted that, for materials constituting layers tobe etched or reference layers or upper reference layers previously described, the chemical etchants may be chosen from among the group hereinbelow:

______________________________________Materials (1) and/or (3)            Dry etch gas                        Liquid______________________________________Single crystal Si            CF.sub.4 --Cl.sub.2                        KOHPolycrystalline Si            SF.sub.6 --Cl.sub.2                        HF--HNO.sub.3Amorphous Si     HCl--Cl.sub.2Silicon nitride  HCl--Cl.sub.2Thermal SiO.sub.2            C.sub.2 F.sub.6 --CHF.sub.3                        HFDeposited SiO.sub.2            SF.sub.6 --CHF.sub.3                        HF, dilute                        or buffered______________________________________

Furthermore, it is pointed out that the chemical agent may be constituted by a mixture of SF.sub.6 or C.sub.2 F.sub.6 with CHF.sub.3 in specified proportions. The etch modes or chemical etchants may comprise CF.sub.4 andO.sub.2.

As regards the practical implementation of the method which is a subject ofthe invention, such as shown in FIGS. 1(a)-1(f), the latter may be implemented under the conditions hereinbelow.

The deposition of the reference layer 3 onto the stop layer 2 may advantageously be carried out, in the case where the layer to be etched 1 is a silicon layer, by the deposition onto the stop layer 2 of a silicon thickness which is slightly less than but in the vicinity of the depth of the etch or trench to be produced, in order to constitute the reference layer 3. The deposition of the etch mask 4, as shown by FIG. 1(c), may then be carried out by depositing onto the reference layer 3 a resin in which an opening is made, for example by a photolithographic process, having the plane dimensions of the etch to be produced.

The etching of the reference layer 3, such as shown in of FIG. 1(d), may then be carried out by means of an anisotropic etching process by using the stop layer 2, constituted for example by a silicon oxide layer, as a stop layer with end-of-etch detection. The resin mask 4 may then be removed or not.

The stop layer 2 may then be etched in the region of the opening or zone made in the reference layer 3 by using either the resin mask 4 over the reference layer 3 or the reference layer 3 itself as a mask.

The resin forming the etch mask 4 having been removed, if the latter was still present, the simultaneous etching of the reference layer 3 and of the layer to be etched 1 is carried out, as shown by FIG. 1(e), with the aid of an anisotropic etching processing. Of course, it is understood thatthe simultaneous etching of the reference layer 3 and of the layer to be etched 1 is then continued until encountering the stop layer 2 subjacent to the reference layer 3, which makes it possible, by end-of-etch detection on encountering this stop layer 2, to stop likewise the etching of the layer to be etched 1.

Of course, it will be understood that a slight overetching may be carried out in order to be certain of having completely removed the reference layer 3 on the stop layer 2. Thus, the depth of the etch on the layer to be etched 1 is equal to the thickness of the reference layer 3 initially deposited plus a slight portion corresponding to the abovementioned overetching, this overetching being, of course, easily calibratable and corresponding generally to a very short time compared to the total etchingtime.

In accordance with the embodiment such as shown in FIG. 2 of the method which is the subject of the invention, in the case of the production inverted-T-type raised elements, the method such as illustrated in Figure (a) and (b), are successively repeated so as to deposit onto the layer called the layer to be etched, although the latter is not etched as such, a reference layer designated by 31 and an upper reference layer designatedby 32, and their respective stop layers 21 and 22. Preferably, when the reference layer 31 and the upper reference layer 32 are constituted by thesame material such as silicon, the reference layer 31 may have a thickness e1 and the upper reference layer 32 a thickness e2 different from e1. The thickness e2 is then less than but in the vicinity of the height desired for the vertical portion of the inverted T, constituting in fact a step added onto the layer to be etched 1.

Then, in accordance with FIG. 2(b), an etch mask 4 constituted by a resin is applied, this mask being fashioned by a photolithographic process so asto keep the mask 4 in the region of the surfaces corresponding to the top of the steps, that is to say at the vertical portion of the inverted T.

As has been shown by FIG. 2(c), the upper reference level 32 is then subjected to an etching process in the presence of the mask 4 until reaching the upper stop layer 22, with end-of-etch detection and stopping of the process for etching the upper layer 32. The abovementioned etching is carried out, of course, by means of an anisotropic etching operation. The resin mask 4 may then be removed or not.

The assembly such as shown by FIG. 2(c) is then, in the presence or not of the etch mask 4, subjected to an etching process, so as to carry out the simultaneous etching of the reference layer 31 and of the raised element 32 resulting from the previous etching. In this operation, the raised element 32 serves as an auxiliary mask for the etching of the reference layer 31 and the formation of the vertical element at the top of the inverted-T-shaped step 31, such as shown by FIG. 2(d), after implementing the steps g), h) and i) of the method described in relation to FIGS. 2(a)-2(c) which is a subject according to the invention in its second embodiment. Of course, it will be understood that the etching is finally stopped by end-of-etch detection on the upper stop layer 22 when all the silicon of the upper reference layer 32 has been removed.

Of course, a slight overetching is always necessary so as to be certain to have completely removed the silicon on the upper stop layer 22.

A more detailed description of an integrated circuit comprising at least one etched layer in accordance with one or other of the embodiments of themethod which is a subject of the invention, such as described in conjunction with the preceding FIGS. 1(a)-1(f) and 2(a)-2(d), will now be given in conjunction with FIGS. 3 and 4, respectively.

According to FIG. 3, the integrated circuit obtained following the implementation of the method which is a subject of the invention such as illustrated in FIG. 1, comprises at least in a substrate 1 of specified material, one channel-type zone. The free surface of the substrate in the vicinity of the channel-type zone comprises a covering of a layer 2, made of a material different from that of the substrate, forming a stop layer. In one embodiment, the substrate 1 constituting a layer to be etched will be constituted by silicon and the stop layer will be constituted by silicon oxide SiO.sub.2.

Furthermore, as shown in FIG. 4, the integrated circuit obtained by the implementation of the method such as illustrated in FIG. 2 comprises, at least on a substrate 1 of specified material, one projection-type zone 31,this projection-type zone being formed by the same material superposed on the surface of the substrate 1 and having substantially the shape of an inverted T. Most often, the substrate 1 made of a specified material is constituted by silicon Si, the inverted-T-shaped projection-type element being constituted by this same material.

As has been shown in FIG. 4, the projection-type zone 31 is made between its distal part and its base part between two layers 21-22 of the same material, different from that of the substrate and forming a stop layer. Most often, the layers 21-22 are produced from silicon dioxide SiO.sub.2, whereas the substrate 1 is itself made from silicon Si.

Furthermore, as has been shown in FIG. 4, the thickness of the layer 22 covering the distal part of the inverted-T-shaped projection-type zone is substantially equal to that of the part 310 forming the base of the projection-type zone.

The embodiment of the method which is a subject of the invention such as shown in FIGS. 2(a)-2(d) is not limited to the production of elements having strictly an inverted-T shape. In fact, the abovementioned method makes it possible to etch a total thickness in two steps:

starting the etching process by a chemical attack, and then

continuing, after detection of the stop layer 22, with a chemical attack ofanother type.

Such a variant of the abovementioned method then makes it possible to produce a final shape different from that of an inverted T in the strict sense, the etch edges being able to be totally or partially slanting or curved as shown in FIGS. 5(a) and 5(b).

Thus, there has been described a method for etching to a fixed depth in which, by virtue of the addition of a reference layer onto a stop layer, the reference layer being made of a similar material from the point of view of the etching of the material constituting the layer to be etched, afixed-time etch is connected to a fixed-depth etch.

It will be noted that the method which is the subject of the invention, in its first and in its second embodiment, renders the etching between integrated-circuit wafers of the same batch totally reproducible. This etching also becomes insensitive to a process variation or to a change of machine, provided that the reference layer and indeed the upper reference layer, have the same etching properties as the layer to be etched. Such insensitivity is explained as follows: if the etching slows down, it is the same for the layers to be etched, that is to say the reference layer and the effective layer to be etched. Because of this, the final etched thickness in the layer to be etched is the same. However, the method whichis the subject of the present invention remains sensitive to the etching inhomogeneities which are connected to the etching method itself, it not being method for these inhomogeneities themselves to be avoided. However, it will be noted that the introduction of a short overetching time makes it possible to be certain that the etching of the reference layer or of the upper reference layer has been really completed.

Citas de patentes
Patente citada Fecha de presentación Fecha de publicación Solicitante Título
US4142926 *12 Jun 19786 Mar 1979Intel CorporationSelf-aligning double polycrystalline silicon etching process
US4174252 *26 Jul 197813 Nov 1979Rca CorporationMethod of defining contact openings in insulating layers on semiconductor devices without the formation of undesirable pinholes
US4268951 *13 Nov 197826 May 1981Rockwell International CorporationSubmicron semiconductor devices
US4436593 *13 Jul 198113 Mar 1984Memorex CorporationSelf-aligned pole tips
US4576834 *20 May 198518 Mar 1986Ncr CorporationMethod for forming trench isolation structures
US4589952 *9 Nov 198420 May 1986International Business Machines CorporationMethod of making trenches with substantially vertical sidewalls in silicon through reactive ion etching
US4634495 *26 Abr 19856 Ene 1987Bbc Brown, Boveri & Company LimitedDry etching process
US4648937 *30 Oct 198510 Mar 1987International Business Machines CorporationMethod of preventing asymmetric etching of lines in sub-micrometer range sidewall images transfer
US4801554 *26 Feb 198631 Ene 1989Bbc Brown, Boveri & Company, LimitedProcess for manufacturing a power semiconductor component
US4832788 *21 May 198723 May 1989Unisys CorporationMethod of fabricating a tapered via hole in polyimide
US4832789 *8 Abr 198823 May 1989American Telephone And Telegrph Company, At&T Bell LaboratoriesSemiconductor devices having multi-level metal interconnects
US4837180 *9 Jul 19876 Jun 1989Industrial Technology Research InstituteLadder gate LDDFET
US5047117 *26 Sep 199010 Sep 1991Micron Technology, Inc.Method of forming a narrow self-aligned, annular opening in a masking layer
US5118384 *10 Dic 19912 Jun 1992International Business Machines CorporationReactive ion etching buffer mask
EP0314522A2 *31 Oct 19883 May 1989Fujitsu LimitedTrench etching process
Otras citas
Referencia
1 *C. C. Beatty et al., 1987 Proceedings Fourth International IEEE VLSI Multilevel Interconn. Conference, Multilevel Tungsten.
2 *Integrated Circuit Metallization with Chromium Non Erodible Mask and Etch Stop Layers , Jun. 15 16, 1987, pp. 163 168 (& cvr).
3Integrated Circuit Metallization with Chromium Non-Erodible Mask and Etch Stop Layers, Jun. 15-16, 1987, pp. 163-168 (& cvr).
Citada por
Patente citante Fecha de presentación Fecha de publicación Solicitante Título
US5663101 *7 Feb 19962 Sep 1997International Business Machines CorporationSemiconductor structure having multiple levels of self-aligned interconnection metallization, and methods for its preparation
US5960254 *10 Abr 199728 Sep 1999International Business Machines CorporationMethods for the preparation of a semiconductor structure having multiple levels of self-aligned interconnection metallization
US725031514 Sep 200431 Jul 2007Idc, LlcMethod for fabricating a structure for a microelectromechanical system (MEMS) device
US729192129 Mar 20046 Nov 2007Qualcomm Mems Technologies, Inc.Structure of a micro electro mechanical system and the manufacturing method thereof
US729747115 Abr 200320 Nov 2007Idc, LlcMethod for manufacturing an array of interferometric modulators
US73214571 Jun 200622 Ene 2008Qualcomm IncorporatedProcess and structure for fabrication of MEMS device having isolated edge posts
US734913627 May 200525 Mar 2008Idc, LlcMethod and device for a display having transparent components integrated therein
US73692923 May 20066 May 2008Qualcomm Mems Technologies, Inc.Electrode and interconnect materials for MEMS devices
US73692965 Ago 20056 May 2008Idc, LlcDevice and method for modifying actuation voltage thresholds of a deformable membrane in an interferometric modulator
US73730261 Jul 200513 May 2008Idc, LlcMEMS device fabricated on a pre-patterned substrate
US738251518 Ene 20063 Jun 2008Qualcomm Mems Technologies, Inc.Silicon-rich silicon nitrides as etch stops in MEMS manufacture
US74058612 May 200529 Jul 2008Idc, LlcMethod and device for protecting interferometric modulators from electrostatic discharge
US74058631 Jun 200629 Jul 2008Qualcomm Mems Technologies, Inc.Patterning of mechanical layer in MEMS to reduce stresses at supports
US74177831 Jul 200526 Ago 2008Idc, LlcMirror and mirror layer for optical modulator and method
US741778419 Abr 200626 Ago 2008Qualcomm Mems Technologies, Inc.Microelectromechanical device and method utilizing a porous surface
US742072825 Mar 20052 Sep 2008Idc, LlcMethods of fabricating interferometric modulators by selectively removing a material
US742933425 Mar 200530 Sep 2008Idc, LlcMethods of fabricating interferometric modulators by selectively removing a material
US74502952 Mar 200611 Nov 2008Qualcomm Mems Technologies, Inc.Methods for producing MEMS with protective coatings using multi-component sacrificial layers
US7485236 *9 Sep 20053 Feb 2009Qualcomm Mems Technologies, Inc.Interference display cell and fabrication method thereof
US74925025 Ago 200517 Feb 2009Idc, LlcMethod of fabricating a free-standing microstructure
US752799619 Abr 20065 May 2009Qualcomm Mems Technologies, Inc.Non-planar surface structures and process for microelectromechanical systems
US753464021 Jul 200619 May 2009Qualcomm Mems Technologies, Inc.Support structure for MEMS device and methods therefor
US754756520 May 200516 Jun 2009Qualcomm Mems Technologies, Inc.Method of manufacturing optical interference color display
US754756822 Feb 200616 Jun 2009Qualcomm Mems Technologies, Inc.Electrical conditioning of MEMS device and insulating layer thereof
US755079420 Sep 200223 Jun 2009Idc, LlcMicromechanical systems device comprising a displaceable electrode and a charge-trapping layer
US755368417 Jun 200530 Jun 2009Idc, LlcMethod of fabricating interferometric devices using lift-off processing techniques
US75537706 Jun 200730 Jun 2009Micron Technology, Inc.Reverse masking profile improvements in high aspect ratio etch
US75646139 Oct 200721 Jul 2009Qualcomm Mems Technologies, Inc.Microelectromechanical device and method utilizing a porous surface
US761636931 Mar 200610 Nov 2009Idc, LlcFilm stack for manufacturing micro-electromechanical systems (MEMS) devices
US762328719 Abr 200624 Nov 2009Qualcomm Mems Technologies, Inc.Non-planar surface structures and process for microelectromechanical systems
US763011428 Oct 20058 Dic 2009Idc, LlcDiffusion barrier layer for MEMS devices
US764211030 Jul 20075 Ene 2010Qualcomm Mems Technologies, Inc.Method for fabricating a structure for a microelectromechanical systems (MEMS) device
US764320310 Abr 20065 Ene 2010Qualcomm Mems Technologies, Inc.Interferometric optical display system with broadband characteristics
US768410422 Ago 200523 Mar 2010Idc, LlcMEMS using filler material and method
US770604428 Abr 200627 Abr 2010Qualcomm Mems Technologies, Inc.Optical interference display cell and method of making the same
US771123919 Abr 20064 May 2010Qualcomm Mems Technologies, Inc.Microelectromechanical device and method utilizing nanoparticles
US771975430 Sep 200818 May 2010Qualcomm Mems Technologies, Inc.Multi-thickness layers for MEMS and mask-saving sequence for same
US77635462 Ago 200627 Jul 2010Qualcomm Mems Technologies, Inc.Methods for reducing surface charges during the manufacture of microelectromechanical systems devices
US778185025 Mar 200524 Ago 2010Qualcomm Mems Technologies, Inc.Controlling electromechanical behavior of structures within a microelectromechanical systems device
US779506129 Dic 200514 Sep 2010Qualcomm Mems Technologies, Inc.Method of creating MEMS device cavities by a non-etching process
US790635329 Jun 200915 Mar 2011Qualcomm Mems Technologies, Inc.Method of fabricating interferometric devices using lift-off processing techniques
US791048712 Jun 200922 Mar 2011Micron Technology, Inc.Reverse masking profile improvements in high aspect ratio etch
EP0854510A2 *22 Dic 199722 Jul 1998International Business Machines CorporationMask removal for etching a DRAM capacitor trench
Clasificaciones
Clasificación de EE.UU.216/13, 257/E21.37, 216/79, 257/E21.232, 216/47, 216/99, 257/E21.234, 257/E21.205
Clasificación internacionalH01L21/28, H01L21/033, H01L21/308, H01L21/3065, H01L21/302
Clasificación cooperativaH01L21/28114, H01L21/3085, H01L21/3081, H01L21/0335
Clasificación europeaH01L21/308D2, H01L21/28E2B20, H01L21/033F2, H01L21/308B
Eventos legales
FechaCódigoEventoDescripción
22 Jul 2010ASAssignment
Owner name: FAHRENHEIT THERMOSCOPE LLC,NEVADA
Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED ON REEL 018022 FRAME 0941. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNOR NAME IS FRANCE TELECOM S.A., NOT FRANCE TELECOM INC;ASSIGNOR:FRANCE TELECOM S.A.;REEL/FRAME:24723/327
Effective date: 20041203
Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED ON REEL 018022 FRAME 0941. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNOR NAME IS FRANCE TELECOM S.A., NOT FRANCE TELECOM INC;ASSIGNOR:FRANCE TELECOM S.A.;REEL/FRAME:024723/0327
Owner name: FAHRENHEIT THERMOSCOPE LLC, NEVADA
15 Mar 2006ASAssignment
Owner name: FAHRENHEIT THERMOSCOPE, LLC, NEVADA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FRANCE TELECOM INC.;REEL/FRAME:018022/0941
Effective date: 20041203
5 Ago 2005FPAYFee payment
Year of fee payment: 12
31 Dic 2001FPAYFee payment
Year of fee payment: 8
16 Ene 1998FPAYFee payment
Year of fee payment: 4
10 Ene 1992ASAssignment
Owner name: FRANCE TELECOM, FRANCE
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:HAOND, MICHEL;REEL/FRAME:005967/0340
Effective date: 19911120