US5428248A - Resin molded semiconductor package - Google Patents

Resin molded semiconductor package Download PDF

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Publication number
US5428248A
US5428248A US08/290,398 US29039894A US5428248A US 5428248 A US5428248 A US 5428248A US 29039894 A US29039894 A US 29039894A US 5428248 A US5428248 A US 5428248A
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Prior art keywords
connection leads
chip
semiconductor package
board connection
semiconductor chip
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US08/290,398
Inventor
Gi Bon Cha
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SK Hynix Inc
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Goldstar Electron Co Ltd
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Priority to US08/290,398 priority Critical patent/US5428248A/en
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    • HELECTRICITY
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    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49503Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
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    • H01L23/49541Geometry of the lead-frame
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Definitions

  • the present invention relates in general to a semiconductor package, and more particularly to a resin molded semiconductor package of which a predetermined volume is hermetically sealed by a mold resin to form a package body.
  • Each of the semiconductor packages of the prior art comprises a semiconductor chip 1 having a predetermined shape and mounted on a paddle 2 of a lead frame.
  • the lead frame further comprises a plurality of inner leads 3, connected to the semiconductor chip 1 through a plurality of metal wires 5 which will be described later herein, and a plurality of outer leads 4 outwardly extending from individual inner leads 3.
  • the semiconductor chip 1 is electrically connected to the inner leads 3 of the lead frame through the plurality of metal wires 5.
  • a predetermined volume including the semiconductor chip 1 and the inner leads 3 electrically connected to the chip 1 is packaged or hermetically sealed by a mold resin 6 to form a package body.
  • the reference numeral 7 denotes chip bonding material for bonding the semiconductor chip 1 to the surface of the paddle 2 of the lead frame.
  • FIG. 3 shows in a plan view a structure of a conventional lead frame of the semiconductor package.
  • the paddle 2 of the lead frame is supported by a pair of connection bars 9 and 9' which connect the opposite ends of the paddle 2 to an opposed pair of side rails 8 and 8', respectively.
  • the plurality of inner leads 3 and the plurality of outer leads 4 are integrally formed with each other and arranged on opposite sides of the paddle 2.
  • Each of the leads, comprising an inner lead 3 and an outer lead 4 is connected to the other leads and supported by dambars 10.
  • the semiconductor chip 1 which is provided by sawing the wafer is first bonded to the surface of the paddle 2 of the lead frame using the chip bonding material 7.
  • the lead frame having the semiconductor chip 1 bonded to the surface of the paddle 2 is, thereafter, subjected to a high temperature curing so as to cure the bonding material 7.
  • a wire bonding step is carried out to electrically connect the inner leads 3 of the lead frame to individual bond pads of the semiconductor chip 1 using the metal wires 5, such as gold wires or aluminum wires.
  • the predetermined volume including the semiconductor chip 1 and the inner leads 3 of the lead frame is hermetically sealed by the mold resin 6 to form the package body. Thereafter, the remnant of the mold resin 6 is removed from the package body prior to plating of the outer leads 4 of the lead frame using tin and lead.
  • a trimming step and a forming step are carried out in series.
  • the dambars 10 connecting the leads to each other and the connection bars 9 and 9' connecting the paddle 2 to the side rails 8 and 8' are cut off to separate the packages from each other.
  • the outer leads 4 of the lead frame protruding out of the package body are bent to a predetermined bent shape, thereby preparing a desired semiconductor package such as shown in FIG. 1 or 2.
  • the known semiconductor packages are conventionally classified into several types in accordance with the bent shape of the outer leads 4 of the lead frame. Otherwise stated, the known semiconductor packages are generally classified into a small outline J-lead package such as shown in FIG. 1, a small outline package (SOP) package such as shown in FIG. 2 and a dual inline package (not shown).
  • SOP small outline package
  • the semiconductor packages prepared by the process described above should be subjected to an electric performance test prior to practical use.
  • the semiconductor package is mounted on a printed circuit board (not shown) by a surface mounting technique or an insert mounting technique and gives its predetermined function to an electronic equipment provided with it.
  • each of the known semiconductor packages requires a substantial mounting area on the printed circuit board due to its outer leads protruding out of the package body while there is some difference in the mounting area in accordance with the types of the semiconductor packages.
  • each of the known semiconductor packages has a problem that it causes deterioration of space efficiency of the printed circuit board and this results in deterioration of package mounting efficiency.
  • Another problem of the known semiconductor packages is that the outer leads are apt to be undesirably bent when the packages are mounted on the printed circuit board or transported, thereby causing quality inferiority.
  • the metal paddle of the lead frame is different in the thermal expansion coefficient from the semiconductor chip, so that the known semiconductor package is easily broken during its mounting on the printed circuit board and there easily occurs separation of the interface between the semiconductor chip and the metal paddle.
  • the preparation process of the known semiconductor package comprises several complex steps and this causes increase of manufacturing cost of the packages as well as installation cost of the package manufacturing equipment.
  • the outer leads protruding out of the package body may result in deterioration of lead contact during the electric performance test, thus deteriorating limit of error of the testing.
  • an object of the present invention to provide a resin molded semiconductor package in which the aforementioned problems can be overcome and which requires minimum mounting area on the printed circuit board and prevents its outer leads from being undesirably bent and prevents breakage of its package body during its mounting on the printed circuit board.
  • the present invention provides a resin molded semiconductor package comprising a semiconductor chip having a predetermined shape; a lead frame comprising a plurality of board connection leads and a plurality of chip connection leads, the board connection leads being connected to a circuit board and supporting the semiconductor chip bonded to their surfaces, the chip connection leads extending from individual board connection leads and being electrically connected to the semiconductor chip through a plurality of metal wires; an adhesive for attaching the semiconductor chip to the surfaces of the board connection leads; the plurality of metal wires electrically connecting a plurality bond pads of the semiconductor chip to the chip connection leads of the lead frame, respectively; and a mold resin hermetically sealing a predetermined volume of the package, including the semiconductor chip and the board connection leads and the chip connection leads, to form a package body such that the lower surfaces of the board connection leads are leveled with the lower surface of the package body.
  • the lower surfaces of the board connection leads are exposed to the outside of the lower surface of the package body.
  • each of the chip connection leads of the lead frame is provided about a periphery of the package body with an opposed pair of V-shaped cutting slots for causing an unnecessary part of the chip connection lead to be easily cut off, and the board connection leads and the chip connection leads are arranged between an opposed pair of side rails at regular intervals and supported by dambars.
  • the adhesive is selected from an insulating double-faced tape and an insulating adhesive of the paste type.
  • the semiconductor package is subjected to an electric performance test prior to its practical use.
  • the semiconductor package is mounted on a printed circuit board by a surface mounting technique or an insert mounting technique and gives its predetermined function to an electronic equipment in such a manner that data of the semiconductor chip is transmitted to the circuit board through the metal wires and the board connection leads of the lead frame.
  • FIG. 1 is a sectional view of a resin molded semiconductor package of the small outline J-lead type in accordance with the prior art
  • FIG. 2 is a sectional view of a resin molded semiconductor package of the small outline type in accordance with the prior art
  • FIG. 3 is a plan view showing a structure of a lead frame of a known resin molded semiconductor package
  • FIG. 4 is a sectional view of a resin molded semiconductor package in accordance with a primary embodiment of the present invention.
  • FIG. 5 is a sectional view of a resin molded semiconductor package in accordance with a second embodiment of the present invention.
  • FIG. 6 is a plan view showing a structure of a lead frame of a resin molded semiconductor package of the present invention.
  • FIGS. 4 and 5 show resin molded semiconductor packages in accordance with a primary embodiment and with a second embodiment of the present invention, respectively, and FIG. 6 shows in a plan view a structure of a lead frame of the resin molded semiconductor package of the present invention.
  • the semiconductor package of the present invention includes a semiconductor chip 11 having a predetermined shape.
  • the lead frame 12 of this package comprises a plurality of board connection leads 12a and a plurality of semiconductor chip connection leads 12b.
  • the board connection leads 12a support the semiconductor chip 11 bonded to their surfaces and are connected to a circuit board (not shown).
  • the chip connection leads 12b extend from the board connection leads 12a, respectively, and are electrically connected to the semiconductor chip 11 by a plurality of metal wires 14. Bonding of the semiconductor chip 11 on the surfaces of the board connection leads 12a of the lead frame 12 is achieved by a pair of chip bonding materials 13.
  • a plurality of bond pads of the semiconductor chip 11 are electrically connected to the chip connection leads 12b of the lead frame through the plurality of metal wires 14, respectively.
  • a predetermined volume including the semiconductor chip 11 and the board connection leads 12a and the chip connection leads 12b of the lead frame is hermetically sealed by a mold resin 15 to form a package body.
  • the lower surfaces of the board connection leads 12a are leveled with the lower surface of the package body and exposed to the outside of the lower surface of the package body.
  • a down-set of predetermined depths ranged from 8 to 50 mils is given to the board connection leads 12a of the lead frame 12.
  • the chip connection leads 12b of the lead frame are horizontally formed. However, in the second embodiment of FIG. 5, they are bent downwardly to show a reversed U-shaped section. Because of the reversed U-shaped section of each of the leads 12b, the second embodiment prevents the leads 12b from being moistened during a package body molding step. In addition, the semiconductor package according to this second embodiment increases the contact surface between the leads 12 and the mold resin 15, so that it reduces the mechanical stress during the molding step.
  • Each of the chip connection leads 12b of the lead frame 12 is provided at the periphery of the package body with an opposed pair of V-shaped cutting slots 16 for facilitating cutting off the unnecessary part of the lead 12b.
  • the cutting off step is carried out when the assembly of the semiconductor package is finished.
  • the board connection leads 12a and the chip connection leads 12b of the lead frame 12 are horizontally arranged between the opposite side rails 17 and 17' at regular intervals and supported by dambars 18 as shown in FIG. 6.
  • provision of the V-shaped cutting slots 16 for each of the chip connection leads 12b is achieved by an etching or a mechanical stamping.
  • the adhesive 13 is preferably selected from an insulating double-faced tape and an insulating adhesive of the paste type and polyimide based tapes and epoxy based tapes.
  • a thermosetting material is used as the adhesive 13
  • a thermoplastic material is used as the adhesive 13
  • the adhesive 13 are preferably cured at a high temperature ranged from 175° to 450° C.
  • a die bonding step is first carried out to bond the semiconductor chip 11 to the surfaces of the board connection leads 12a of the lead frame.
  • the semiconductor chip 11 is attached to the surfaces of the board connection leads 12a of the lead frame using the adhesive 13, such as an insulating double-faced tape.
  • the lead frame 12 has no conventional paddle but comprises the plurality of board connection leads 12a and the plurality of chip connection leads 12b, both leads 12a and 12b being arranged at regular intervals between the opposite side rails 17 and 17' as shown in FIG. 6.
  • the die boding step is followed by a curing step carried out at a predetermined temperature for curing the adhesive 13 attaching the semiconductor chip 11 to the surfaces of the board connection leads 12a.
  • a wire bonding step is carried out to electrically connect the chip connection leads 12b of the lead frame to individual bond pads of the semiconductor chip 11 using metal wires 14, such as gold wires or aluminum wires.
  • a molding step is carried out to hermetically seal the predetermined volume, including the semiconductor chip 11 and the leads 12a and 12b of the lead frame 12, by the mold resin 15 such that the lower surfaces of the board connection leads 12a are leveled with the lower surface of the mold resin 15 and exposed to the outside of the lower surface of the mold resin 15, thus forming the package body.
  • the molding step is followed by a trimming step for cutting the V-shaped slots 16 of the chip connection leads 12b for cutting off the unnecessary parts of the leads 12b and for providing the desired semiconductor package of the present invention.
  • the remnant of the mold resin 15 is removed from the package body, especially from the lower surface of the package body, by a conventional mechanical abrasive blasting or by a conventional chemical treatment.
  • the lower surfaces of the board connection leads 12a of the lead frame are exposed to the outside of lower surface of the package body.
  • the resultant semiconductor package is, thereafter, inserted in a tray or in a tube to be subjected to an electric performance test.
  • the semiconductor package on the electric performance test is mounted on a printed circuit board by surface mounting technique to be practically used.
  • the semiconductor package of the present invention removes the metal paddle from the lead frame and, as a result, prevents breakage of the package body during its mounting on a circuit board due to difference in thermal expansion coefficient between the semiconductor chip and the metal paddle.
  • the semiconductor package of this invention has a plurality of board connection leads of which the lower surfaces are exposed to the outside of the lower surface of the package body. Hence, this semiconductor package requires minimum mounting area of the printed circuit board and prevents undesirable bending of its leads during its mounting on the circuit board or its transportation.
  • the semiconductor package of this invention has no outer leads to be bent in a desired bent shape, thus requiring no forming step in its preparation process.
  • the preparation process of this semiconductor package is remarkably simplified, thus reducing the manufacturing cost of the packages as well as the installation cost of the package manufacturing equipment.
  • the package of this invention make it possible to use a probe tip in testing its electric performance, so that it prevents the lead contact deterioration in the electric performance test and this achieves a desired precise testing results.

Abstract

A resin molded semiconductor package of which the semiconductor chip is bonded to leads instead of a paddle. This package comprises a semiconductor chip and a lead frame comprising a plurality of board connection leads and a plurality of chip connection leads. The board connection leads are connected to a circuit board and support the semiconductor chip bonded to their surfaces. The chip connection leads extend from individual board connection leads and are electrically connected to the semiconductor chip through a plurality of metal wires. A pair of chip bonding materials bond the semiconductor chip to the surfaces of the board connection leads. A predetermined volume of the package, including the semiconductor chip and the board connection leads and the chip connection leads, is hermetically sealed by a mold resin to form a package body in which the lower surfaces of the board connection leads are exposed to the outside of the lower surface of the package body. The chip bonding material is selected from an insulating double-faced tape and an insulating adhesive of the paste type.

Description

This is a continuation of application Ser. No. 109,227 filed on Aug. 19, 1993, now abandoned.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a semiconductor package, and more particularly to a resin molded semiconductor package of which a predetermined volume is hermetically sealed by a mold resin to form a package body.
2. Background of the Prior Art
With reference to FIGS. 1 and 2, there are shown a small outline J-lead package and a small outline package in accordance with the prior art, respectively. Each of the semiconductor packages of the prior art comprises a semiconductor chip 1 having a predetermined shape and mounted on a paddle 2 of a lead frame. The lead frame further comprises a plurality of inner leads 3, connected to the semiconductor chip 1 through a plurality of metal wires 5 which will be described later herein, and a plurality of outer leads 4 outwardly extending from individual inner leads 3. The semiconductor chip 1 is electrically connected to the inner leads 3 of the lead frame through the plurality of metal wires 5. In the known package, a predetermined volume including the semiconductor chip 1 and the inner leads 3 electrically connected to the chip 1 is packaged or hermetically sealed by a mold resin 6 to form a package body.
In the drawings, the reference numeral 7 denotes chip bonding material for bonding the semiconductor chip 1 to the surface of the paddle 2 of the lead frame.
FIG. 3 shows in a plan view a structure of a conventional lead frame of the semiconductor package. As shown in this drawing, the paddle 2 of the lead frame is supported by a pair of connection bars 9 and 9' which connect the opposite ends of the paddle 2 to an opposed pair of side rails 8 and 8', respectively. The plurality of inner leads 3 and the plurality of outer leads 4 are integrally formed with each other and arranged on opposite sides of the paddle 2. Each of the leads, comprising an inner lead 3 and an outer lead 4, is connected to the other leads and supported by dambars 10.
In order to assembly the semiconductor package having the construction described above, the semiconductor chip 1 which is provided by sawing the wafer is first bonded to the surface of the paddle 2 of the lead frame using the chip bonding material 7. The lead frame having the semiconductor chip 1 bonded to the surface of the paddle 2 is, thereafter, subjected to a high temperature curing so as to cure the bonding material 7.
Thereafter, a wire bonding step is carried out to electrically connect the inner leads 3 of the lead frame to individual bond pads of the semiconductor chip 1 using the metal wires 5, such as gold wires or aluminum wires.
Upon finishing the wire bonding step, the predetermined volume including the semiconductor chip 1 and the inner leads 3 of the lead frame is hermetically sealed by the mold resin 6 to form the package body. Thereafter, the remnant of the mold resin 6 is removed from the package body prior to plating of the outer leads 4 of the lead frame using tin and lead.
After the plating of the outer leads 4, a trimming step and a forming step are carried out in series. In the trimming step, the dambars 10 connecting the leads to each other and the connection bars 9 and 9' connecting the paddle 2 to the side rails 8 and 8' are cut off to separate the packages from each other. In the forming step, the outer leads 4 of the lead frame protruding out of the package body are bent to a predetermined bent shape, thereby preparing a desired semiconductor package such as shown in FIG. 1 or 2. The known semiconductor packages are conventionally classified into several types in accordance with the bent shape of the outer leads 4 of the lead frame. Otherwise stated, the known semiconductor packages are generally classified into a small outline J-lead package such as shown in FIG. 1, a small outline package (SOP) package such as shown in FIG. 2 and a dual inline package (not shown).
The semiconductor packages prepared by the process described above should be subjected to an electric performance test prior to practical use. In practical use, the semiconductor package is mounted on a printed circuit board (not shown) by a surface mounting technique or an insert mounting technique and gives its predetermined function to an electronic equipment provided with it.
However, each of the known semiconductor packages requires a substantial mounting area on the printed circuit board due to its outer leads protruding out of the package body while there is some difference in the mounting area in accordance with the types of the semiconductor packages. Thus, each of the known semiconductor packages has a problem that it causes deterioration of space efficiency of the printed circuit board and this results in deterioration of package mounting efficiency. Another problem of the known semiconductor packages is that the outer leads are apt to be undesirably bent when the packages are mounted on the printed circuit board or transported, thereby causing quality inferiority.
In addition, since the metal paddle of the lead frame is different in the thermal expansion coefficient from the semiconductor chip, so that the known semiconductor package is easily broken during its mounting on the printed circuit board and there easily occurs separation of the interface between the semiconductor chip and the metal paddle. Furthermore, the preparation process of the known semiconductor package comprises several complex steps and this causes increase of manufacturing cost of the packages as well as installation cost of the package manufacturing equipment. The outer leads protruding out of the package body may result in deterioration of lead contact during the electric performance test, thus deteriorating limit of error of the testing.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a resin molded semiconductor package in which the aforementioned problems can be overcome and which requires minimum mounting area on the printed circuit board and prevents its outer leads from being undesirably bent and prevents breakage of its package body during its mounting on the printed circuit board.
It is another object of the present invention to provide a resin molded semiconductor package which requires no forming step in its preparation process, thereby simplifying the preparation process and reducing the manufacturing cost of the packages as well as installation cost of the package manufacturing equipment.
To accomplish the above object, the present invention provides a resin molded semiconductor package comprising a semiconductor chip having a predetermined shape; a lead frame comprising a plurality of board connection leads and a plurality of chip connection leads, the board connection leads being connected to a circuit board and supporting the semiconductor chip bonded to their surfaces, the chip connection leads extending from individual board connection leads and being electrically connected to the semiconductor chip through a plurality of metal wires; an adhesive for attaching the semiconductor chip to the surfaces of the board connection leads; the plurality of metal wires electrically connecting a plurality bond pads of the semiconductor chip to the chip connection leads of the lead frame, respectively; and a mold resin hermetically sealing a predetermined volume of the package, including the semiconductor chip and the board connection leads and the chip connection leads, to form a package body such that the lower surfaces of the board connection leads are leveled with the lower surface of the package body. Thus, the lower surfaces of the board connection leads are exposed to the outside of the lower surface of the package body.
Here, a down-set of a predetermined depth is given to the board connection leads of the lead frame, each of the chip connection leads of the lead frame is provided about a periphery of the package body with an opposed pair of V-shaped cutting slots for causing an unnecessary part of the chip connection lead to be easily cut off, and the board connection leads and the chip connection leads are arranged between an opposed pair of side rails at regular intervals and supported by dambars.
The adhesive is selected from an insulating double-faced tape and an insulating adhesive of the paste type.
In the same manner as the conventional semiconductor packages, the semiconductor package is subjected to an electric performance test prior to its practical use. In practical use, the semiconductor package is mounted on a printed circuit board by a surface mounting technique or an insert mounting technique and gives its predetermined function to an electronic equipment in such a manner that data of the semiconductor chip is transmitted to the circuit board through the metal wires and the board connection leads of the lead frame.
BRIEF DESCRIPTION OF THE DRAWINGS
The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a sectional view of a resin molded semiconductor package of the small outline J-lead type in accordance with the prior art;
FIG. 2 is a sectional view of a resin molded semiconductor package of the small outline type in accordance with the prior art;
FIG. 3 is a plan view showing a structure of a lead frame of a known resin molded semiconductor package;
FIG. 4 is a sectional view of a resin molded semiconductor package in accordance with a primary embodiment of the present invention;
FIG. 5 is a sectional view of a resin molded semiconductor package in accordance with a second embodiment of the present invention; and
FIG. 6 is a plan view showing a structure of a lead frame of a resin molded semiconductor package of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
With reference to the drawings, FIGS. 4 and 5 show resin molded semiconductor packages in accordance with a primary embodiment and with a second embodiment of the present invention, respectively, and FIG. 6 shows in a plan view a structure of a lead frame of the resin molded semiconductor package of the present invention.
As shown in these drawings, the semiconductor package of the present invention includes a semiconductor chip 11 having a predetermined shape. The lead frame 12 of this package comprises a plurality of board connection leads 12a and a plurality of semiconductor chip connection leads 12b. The board connection leads 12a support the semiconductor chip 11 bonded to their surfaces and are connected to a circuit board (not shown). The chip connection leads 12b extend from the board connection leads 12a, respectively, and are electrically connected to the semiconductor chip 11 by a plurality of metal wires 14. Bonding of the semiconductor chip 11 on the surfaces of the board connection leads 12a of the lead frame 12 is achieved by a pair of chip bonding materials 13. A plurality of bond pads of the semiconductor chip 11 are electrically connected to the chip connection leads 12b of the lead frame through the plurality of metal wires 14, respectively. In the semiconductor package of this invention, a predetermined volume including the semiconductor chip 11 and the board connection leads 12a and the chip connection leads 12b of the lead frame is hermetically sealed by a mold resin 15 to form a package body. When the packaged body is formed, the lower surfaces of the board connection leads 12a are leveled with the lower surface of the package body and exposed to the outside of the lower surface of the package body.
A down-set of predetermined depths ranged from 8 to 50 mils is given to the board connection leads 12a of the lead frame 12.
In the primary embodiment of FIG. 4, the chip connection leads 12b of the lead frame are horizontally formed. However, in the second embodiment of FIG. 5, they are bent downwardly to show a reversed U-shaped section. Because of the reversed U-shaped section of each of the leads 12b, the second embodiment prevents the leads 12b from being moistened during a package body molding step. In addition, the semiconductor package according to this second embodiment increases the contact surface between the leads 12 and the mold resin 15, so that it reduces the mechanical stress during the molding step.
Each of the chip connection leads 12b of the lead frame 12 is provided at the periphery of the package body with an opposed pair of V-shaped cutting slots 16 for facilitating cutting off the unnecessary part of the lead 12b. The cutting off step is carried out when the assembly of the semiconductor package is finished. The board connection leads 12a and the chip connection leads 12b of the lead frame 12 are horizontally arranged between the opposite side rails 17 and 17' at regular intervals and supported by dambars 18 as shown in FIG. 6.
In the present invention, provision of the V-shaped cutting slots 16 for each of the chip connection leads 12b is achieved by an etching or a mechanical stamping.
The adhesive 13 is preferably selected from an insulating double-faced tape and an insulating adhesive of the paste type and polyimide based tapes and epoxy based tapes. When a thermosetting material is used as the adhesive 13, it is preferred to cure the adhesive 13 attaching the chip 11 to the surfaces of board connection leads 12a in an oven. However, when a thermoplastic material is used as the adhesive 13, the adhesive 13 are preferably cured at a high temperature ranged from 175° to 450° C.
In order to prepare the semiconductor package having the construction described above, a die bonding step is first carried out to bond the semiconductor chip 11 to the surfaces of the board connection leads 12a of the lead frame. In the die bonding step, the semiconductor chip 11 is attached to the surfaces of the board connection leads 12a of the lead frame using the adhesive 13, such as an insulating double-faced tape. Here, the lead frame 12 has no conventional paddle but comprises the plurality of board connection leads 12a and the plurality of chip connection leads 12b, both leads 12a and 12b being arranged at regular intervals between the opposite side rails 17 and 17' as shown in FIG. 6. The die boding step is followed by a curing step carried out at a predetermined temperature for curing the adhesive 13 attaching the semiconductor chip 11 to the surfaces of the board connection leads 12a.
Thereafter, a wire bonding step is carried out to electrically connect the chip connection leads 12b of the lead frame to individual bond pads of the semiconductor chip 11 using metal wires 14, such as gold wires or aluminum wires.
Upon finishing the wire bonding step, a molding step is carried out to hermetically seal the predetermined volume, including the semiconductor chip 11 and the leads 12a and 12b of the lead frame 12, by the mold resin 15 such that the lower surfaces of the board connection leads 12a are leveled with the lower surface of the mold resin 15 and exposed to the outside of the lower surface of the mold resin 15, thus forming the package body.
The molding step is followed by a trimming step for cutting the V-shaped slots 16 of the chip connection leads 12b for cutting off the unnecessary parts of the leads 12b and for providing the desired semiconductor package of the present invention.
In the preparation process of the package of this invention, the remnant of the mold resin 15 is removed from the package body, especially from the lower surface of the package body, by a conventional mechanical abrasive blasting or by a conventional chemical treatment. As a result of the remnant removal from the lower surface of the package body, the lower surfaces of the board connection leads 12a of the lead frame are exposed to the outside of lower surface of the package body.
The resultant semiconductor package is, thereafter, inserted in a tray or in a tube to be subjected to an electric performance test. The semiconductor package on the electric performance test is mounted on a printed circuit board by surface mounting technique to be practically used.
As described above, the semiconductor package of the present invention removes the metal paddle from the lead frame and, as a result, prevents breakage of the package body during its mounting on a circuit board due to difference in thermal expansion coefficient between the semiconductor chip and the metal paddle. The semiconductor package of this invention has a plurality of board connection leads of which the lower surfaces are exposed to the outside of the lower surface of the package body. Hence, this semiconductor package requires minimum mounting area of the printed circuit board and prevents undesirable bending of its leads during its mounting on the circuit board or its transportation.
In addition, the semiconductor package of this invention has no outer leads to be bent in a desired bent shape, thus requiring no forming step in its preparation process. In this regard, the preparation process of this semiconductor package is remarkably simplified, thus reducing the manufacturing cost of the packages as well as the installation cost of the package manufacturing equipment. Furthermore, the package of this invention make it possible to use a probe tip in testing its electric performance, so that it prevents the lead contact deterioration in the electric performance test and this achieves a desired precise testing results.
Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.

Claims (10)

What is claimed is:
1. A resin molded semiconductor package comprising:
a semiconductor chip having a plurality of bond pads and a lower surface;
a lead frame comprising a plurality of board connection leads having upper surfaces and lower surfaces, and a plurality of chip connection leads having horizontally flat upper surfaces, said lower surfaces of said board connection leads electrically contacting metal patterns of a printed circuit board and said upper surfaces of said board connection leads supporting said semiconductor chip which is bonded to said upper surfaces of said board connection leads, said chip connection leads extending from individual board connection leads and being electrically connected to said semiconductor chip through a plurality of metal wires, with the horizontally flat upper surfaces of said chip connection leads being positioned above the lower surface of said semiconductor chip;
an adhesive for bonding said semiconductor chip to the upper surfaces of said board connection leads;
said plurality of metal wires electrically connecting a plurality of bond pads of said semiconductor chip to the horizontally flat upper surfaces of said chip connection leads of said lead frame, respectively; and
a mold resin hermetically sealing a predetermined volume of said molded semiconductor package, including said semiconductor chip, said board connection leads and said chip connection leads, to form a molded semiconductor package body having a lower surface wherein the lower surfaces of said board connection leads are exposed at the lower surface of said molded semiconductor package body.
2. A resin molded semiconductor package according to claim 1, wherein said adhesive is an insulating double-faced tape.
3. A resin molded semiconductor package according to claim 1, wherein said adhesive is an insulating paste adhesive.
4. A resin molded semiconductor package according to claim 1, wherein said adhesive is a polyimide based adhesive tape.
5. A resin molded semiconductor package according to claim 1, wherein said adhesive is an epoxy based adhesive tape.
6. A resin molded semiconductor package comprising:
a semiconductor chip having a plurality of bond pads and a lower surface;
a lead frame comprising a plurality of board connection leads having upper surfaces and lower surfaces, and a plurality of chip connection leads having horizontally flat upper surfaces, said lower surfaces of said board connection leads electrically contacting metal patterns of a printed circuit board and said upper surfaces of said board connection leads supporting said semiconductor chip which is bonded to said upper surfaces of said board connection leads, said chip connection leads extending from individual board connection leads and being electrically connected to said semiconductor chip through a plurality of metal wires, with the horizontally flat upper surfaces of said chip connection leads being positioned above the lower surface of said semiconductor chip;
an adhesive for bonding said semiconductor chip to the upper surfaces of said board connection leads;
said plurality of metal wires electrically connecting a plurality of bond pads of said semiconductor chip to the horizontally flat upper surfaces of said chip connection leads of said lead frame, respectively; and
a mold resin hermetically sealing a predetermined volume of said molded semiconductor package, including said semiconductor chip, said board connection leads and said chip connection leads, to form a molded semiconductor package body having a lower surface wherein the lower surfaces of said board connection leads are exposed at the lower surface of said molded semiconductor package body, and said semiconductor package also having a side surface wherein said surfaces of said chip connection leads are exposed.
7. A resin molded semiconductor package according to claim 6, wherein said adhesive is an insulating double-faced tape.
8. A resin molded semiconductor package according to claim 6, wherein said adhesive is an insulating paste adhesive.
9. A resin molded semiconductor package according to claim 6, wherein said adhesive is a polyimide based adhesive tape.
10. A resin molded semiconductor package according to claim 6, wherein said adhesive is an epoxy based adhesive tape.
US08/290,398 1992-08-21 1994-08-15 Resin molded semiconductor package Expired - Lifetime US5428248A (en)

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KR2019920015766U KR0128251Y1 (en) 1992-08-21 1992-08-21 Lead exposed type semiconductor device
US10922793A 1993-08-19 1993-08-19
US08/290,398 US5428248A (en) 1992-08-21 1994-08-15 Resin molded semiconductor package

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Cited By (164)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5594234A (en) * 1994-11-14 1997-01-14 Texas Instruments Incorporated Downset exposed die mount pad leadframe and package
US5693573A (en) * 1996-06-14 1997-12-02 Lg Semicon Co., Ltd. Semiconductor package lead deflash method
US5770888A (en) * 1995-12-29 1998-06-23 Lg Semicon Co., Ltd. Integrated chip package with reduced dimensions and leads exposed from the top and bottom of the package
US5861668A (en) * 1996-06-14 1999-01-19 Lg Semicon Co., Ltd. Semiconductor package
US5863805A (en) * 1996-07-08 1999-01-26 Industrial Technology Research Institute Method of packaging semiconductor chips based on lead-on-chip (LOC) architecture
US5866939A (en) * 1996-01-21 1999-02-02 Anam Semiconductor Inc. Lead end grid array semiconductor package
US5886404A (en) * 1996-06-18 1999-03-23 Lg Semicon Co., Ltd. Bottom lead semiconductor package having folded leads
DE19716668C2 (en) * 1996-05-17 1999-05-27 Lg Semicon Co Ltd Semiconductor chip stack housing with leads underneath
US5942794A (en) * 1996-10-22 1999-08-24 Matsushita Electronics Corporation Plastic encapsulated semiconductor device and method of manufacturing the same
US5963433A (en) * 1996-12-28 1999-10-05 Lg Semicon Co., Ltd. Bottom lead semiconductor package with recessed leads and fabrication method thereof
US5998877A (en) * 1996-08-29 1999-12-07 Oki Electric Industry Co., Ltd. Semiconductor device packaged in plastic and mold employable for production thereof
US6045369A (en) * 1996-07-29 2000-04-04 Lg Semicon Co., Ltd. Device for mounting semiconductor package and method of fabricating same
WO2000024056A1 (en) * 1998-10-22 2000-04-27 Azimuth Industrial Company, Inc. Semiconductor package for high frequency performance
US6118174A (en) * 1996-12-28 2000-09-12 Lg Semicon Co., Ltd. Bottom lead frame and bottom lead semiconductor package using the same
US6122822A (en) * 1998-06-23 2000-09-26 Vanguard International Semiconductor Corporation Method for balancing mold flow in encapsulating devices
US6157074A (en) * 1997-07-16 2000-12-05 Hyundai Electronics Industries Co., Ltd. Lead frame adapted for variable sized devices, semiconductor package with such lead frame and method for using same
US6168975B1 (en) * 1998-06-24 2001-01-02 St Assembly Test Services Pte Ltd Method of forming extended lead package
US6177718B1 (en) * 1998-04-28 2001-01-23 Kabushiki Kaisha Toshiba Resin-sealed semiconductor device
US6265761B1 (en) * 1999-05-07 2001-07-24 Maxim Integrated Products, Inc. Semiconductor devices with improved lead frame structures
US6410363B1 (en) 1997-03-10 2002-06-25 Sanyo Electric Co., Ltd. Semiconductor device and method of manufacturing same
US6421248B1 (en) * 1997-01-15 2002-07-16 Infineon Technologies Ag Chip card module
US6420779B1 (en) 1999-09-14 2002-07-16 St Assembly Test Services Ltd. Leadframe based chip scale package and method of producing the same
US6427976B1 (en) * 1999-12-14 2002-08-06 Siliconware Precision Industries Co., Ltd. Lead-frame-based chip-scale package and method of manufacturing the same
US20020105061A1 (en) * 2001-02-08 2002-08-08 Shunichi Abe Semiconductor device and manufacturing method thereof
US6469369B1 (en) 1999-06-30 2002-10-22 Amkor Technology, Inc. Leadframe having a mold inflow groove and method for making
US6475827B1 (en) 1999-10-15 2002-11-05 Amkor Technology, Inc. Method for making a semiconductor package having improved defect testing and increased production yield
US6483177B1 (en) 2000-10-09 2002-11-19 St Assembly Test Services Ltd Leaded semiconductor packages and method of trimming and singulating such packages
US6501161B1 (en) 1999-10-15 2002-12-31 Amkor Technology, Inc. Semiconductor package having increased solder joint strength
US20030020146A1 (en) * 1998-11-20 2003-01-30 Yee Jae Hak Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant
US6525406B1 (en) 1999-10-15 2003-02-25 Amkor Technology, Inc. Semiconductor device having increased moisture path and increased solder joint strength
US6555899B1 (en) 1999-10-15 2003-04-29 Amkor Technology, Inc. Semiconductor package leadframe assembly and method of manufacture
CN1107349C (en) * 1997-04-21 2003-04-30 日本电气株式会社 Semiconductor device, lead frame, and lead bonding
US6603196B2 (en) * 2001-03-28 2003-08-05 Siliconware Precision Industries Co., Ltd. Leadframe-based semiconductor package for multi-media card
US6605866B1 (en) 1999-12-16 2003-08-12 Amkor Technology, Inc. Stackable semiconductor package and method for manufacturing same
US6616436B1 (en) 1999-10-15 2003-09-09 Amkor Technology, Inc. Apparatus for manufacturing semiconductor packages
US6627976B1 (en) 1999-10-15 2003-09-30 Amkor Technology, Inc. Leadframe for semiconductor package and mold for molding the same
US6627977B1 (en) 2002-05-09 2003-09-30 Amkor Technology, Inc. Semiconductor package including isolated ring structure
US6630728B2 (en) * 1998-06-24 2003-10-07 Amkor Technology, Inc. Plastic integrated circuit package and leadframe for making the package
US6646339B1 (en) 1999-10-15 2003-11-11 Amkor Technology, Inc. Thin and heat radiant semiconductor package and method for manufacturing
US6677663B1 (en) 1999-12-30 2004-01-13 Amkor Technology, Inc. End grid array semiconductor package
US6677662B1 (en) 1999-10-15 2004-01-13 Amkor Technology, Inc. Clamp and heat block assembly for wire bonding a semiconductor package assembly
US6686258B2 (en) 2000-11-02 2004-02-03 St Assembly Test Services Ltd. Method of trimming and singulating leaded semiconductor packages
US6696747B1 (en) 1999-10-15 2004-02-24 Amkor Technology, Inc. Semiconductor package having reduced thickness
US20040041250A1 (en) * 2002-08-29 2004-03-04 Hitachi, Ltd. Semiconductor device and a method of manufacturing the same
DE19651549B4 (en) * 1996-06-14 2004-03-18 LG Semicon Co., Ltd., Cheongju Connection frame and chip housing
US20040056338A1 (en) * 1999-12-16 2004-03-25 Crowley Sean Timothy Near chip size semiconductor package
US6730544B1 (en) 1999-12-20 2004-05-04 Amkor Technology, Inc. Stackable semiconductor package and method for manufacturing same
US20040104457A1 (en) * 2002-11-27 2004-06-03 United Test And Assembly Test Center Ltd. High density chip scale leadframe package and method of manufacturing the package
US6750545B1 (en) 2003-02-28 2004-06-15 Amkor Technology, Inc. Semiconductor package capable of die stacking
US6753597B1 (en) 1999-12-16 2004-06-22 Amkor Technology, Inc. Encapsulated semiconductor package including chip paddle and leads
US20040124508A1 (en) * 2002-11-27 2004-07-01 United Test And Assembly Test Center Ltd. High performance chip scale leadframe package and method of manufacturing the package
US6777789B1 (en) 2001-03-20 2004-08-17 Amkor Technology, Inc. Mounting for a package containing a chip
US6794740B1 (en) 2003-03-13 2004-09-21 Amkor Technology, Inc. Leadframe package for semiconductor devices
US6798047B1 (en) 2002-12-26 2004-09-28 Amkor Technology, Inc. Pre-molded leadframe
US6818973B1 (en) 2002-09-09 2004-11-16 Amkor Technology, Inc. Exposed lead QFP package fabricated through the use of a partial saw process
US20040227217A1 (en) * 1999-10-15 2004-11-18 Jang Sung Sik Semiconductor package having improved adhesiveness and ground bonding
US6841414B1 (en) 2002-06-19 2005-01-11 Amkor Technology, Inc. Saw and etch singulation method for a chip package
US20050012186A1 (en) * 2003-01-29 2005-01-20 Quantum Leap Packaging, Inc. Lead for integrated circuit package
US6846704B2 (en) 2001-03-27 2005-01-25 Amkor Technology, Inc. Semiconductor package and method for manufacturing the same
US20050029636A1 (en) * 2000-12-29 2005-02-10 Paek Jong Sik Semiconductor package including flip chip
US20050054141A1 (en) * 2003-08-23 2005-03-10 Jin-Ho Kim Thin semiconductor package having stackable lead frame and method of manufacturing the same
US6867071B1 (en) 2002-07-12 2005-03-15 Amkor Technology, Inc. Leadframe including corner leads and semiconductor package using same
US20050062139A1 (en) * 2003-09-24 2005-03-24 Chung-Hsing Tzu Reinforced die pad support structure
US20050062148A1 (en) * 2000-03-25 2005-03-24 Seo Seong Min Semiconductor package
US6873041B1 (en) 2001-11-07 2005-03-29 Amkor Technology, Inc. Power semiconductor package with strap
US6879034B1 (en) 2003-05-01 2005-04-12 Amkor Technology, Inc. Semiconductor package including low temperature co-fired ceramic substrate
US6893900B1 (en) 1998-06-24 2005-05-17 Amkor Technology, Inc. Method of making an integrated circuit package
US6897550B1 (en) 2003-06-11 2005-05-24 Amkor Technology, Inc. Fully-molded leadframe stand-off feature
US20050127532A1 (en) * 2003-12-09 2005-06-16 Leeshawn Luo Inverted J-lead package for power devices
US6919620B1 (en) 2002-09-17 2005-07-19 Amkor Technology, Inc. Compact flash memory card with clamshell leadframe
US20050156292A1 (en) * 2001-01-15 2005-07-21 Paek Jong S. Reduced size semiconductor package with stacked dies
US6927483B1 (en) 2003-03-07 2005-08-09 Amkor Technology, Inc. Semiconductor package exhibiting efficient lead placement
US6965157B1 (en) 1999-11-09 2005-11-15 Amkor Technology, Inc. Semiconductor package with exposed die pad and body-locking leadframe
US6965159B1 (en) 2001-09-19 2005-11-15 Amkor Technology, Inc. Reinforced lead-frame assembly for interconnecting circuits within a circuit module
US6967395B1 (en) 2001-03-20 2005-11-22 Amkor Technology, Inc. Mounting for a package containing a chip
DE19827237B4 (en) * 1998-02-10 2006-02-02 LG Semicon Co., Ltd., Cheongju A printed circuit board substrate for a semiconductor device package and a semiconductor device package using the same, and a manufacturing method thereof
US7001799B1 (en) 2003-03-13 2006-02-21 Amkor Technology, Inc. Method of making a leadframe for semiconductor devices
US7005326B1 (en) 1998-06-24 2006-02-28 Amkor Technology, Inc. Method of making an integrated circuit package
US7008825B1 (en) 2003-05-27 2006-03-07 Amkor Technology, Inc. Leadframe strip having enhanced testability
US7030474B1 (en) 1998-06-24 2006-04-18 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
US20060099789A1 (en) * 2004-10-22 2006-05-11 Tessera, Inc. Micro lead frame packages and methods of manufacturing the same
US7045883B1 (en) 2001-04-04 2006-05-16 Amkor Technology, Inc. Thermally enhanced chip scale lead on chip semiconductor package and method of making same
US7057268B1 (en) 2004-01-27 2006-06-06 Amkor Technology, Inc. Cavity case with clip/plug for use on multi-media card
US7064009B1 (en) 2001-04-04 2006-06-20 Amkor Technology, Inc. Thermally enhanced chip scale lead on chip semiconductor package and method of making same
KR100592784B1 (en) * 2000-01-14 2006-06-26 삼성전자주식회사 Multi chip package
US7071541B1 (en) 1998-06-24 2006-07-04 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
US20060151858A1 (en) * 2000-04-27 2006-07-13 Ahn Byung H Leadframe and semiconductor package made using the leadframe
US7091594B1 (en) 2004-01-28 2006-08-15 Amkor Technology, Inc. Leadframe type semiconductor package having reduced inductance and its manufacturing method
US7095103B1 (en) 2003-05-01 2006-08-22 Amkor Technology, Inc. Leadframe based memory card
US7102208B1 (en) 1999-10-15 2006-09-05 Amkor Technology, Inc. Leadframe and semiconductor package with improved solder joint strength
US7112474B1 (en) 1998-06-24 2006-09-26 Amkor Technology, Inc. Method of making an integrated circuit package
US7138707B1 (en) 2003-10-21 2006-11-21 Amkor Technology, Inc. Semiconductor package including leads and conductive posts for providing increased functionality
US7144517B1 (en) 2003-11-07 2006-12-05 Amkor Technology, Inc. Manufacturing method for leadframe and for semiconductor package using the leadframe
US20060289973A1 (en) * 2001-03-27 2006-12-28 Lee Hyung J Lead frame for semiconductor package
US7190062B1 (en) 2004-06-15 2007-03-13 Amkor Technology, Inc. Embedded leadframe semiconductor package
US7192807B1 (en) 2002-11-08 2007-03-20 Amkor Technology, Inc. Wafer level package and fabrication method
US7202554B1 (en) 2004-08-19 2007-04-10 Amkor Technology, Inc. Semiconductor package and its manufacturing method
US7211879B1 (en) 2003-11-12 2007-05-01 Amkor Technology, Inc. Semiconductor package with chamfered corners and method of manufacturing the same
US7217991B1 (en) 2004-10-22 2007-05-15 Amkor Technology, Inc. Fan-in leadframe semiconductor package
US7245007B1 (en) 2003-09-18 2007-07-17 Amkor Technology, Inc. Exposed lead interposer leadframe package
US20070176287A1 (en) * 1999-11-05 2007-08-02 Crowley Sean T Thin integrated circuit device packages for improved radio frequency performance
US7253503B1 (en) 1999-11-05 2007-08-07 Amkor Technology, Inc. Integrated circuit device packages and substrates for making the packages
US20080003722A1 (en) * 2004-04-15 2008-01-03 Chun David D Transfer mold solution for molded multi-media card
US7332375B1 (en) 1998-06-24 2008-02-19 Amkor Technology, Inc. Method of making an integrated circuit package
US7361533B1 (en) 2002-11-08 2008-04-22 Amkor Technology, Inc. Stacked embedded leadframe
US20080230876A1 (en) * 2007-03-22 2008-09-25 Stats Chippac, Ltd. Leadframe Design for QFN Package with Top Terminal Leads
US7485952B1 (en) 2001-09-19 2009-02-03 Amkor Technology, Inc. Drop resistant bumpers for fully molded memory cards
US7507603B1 (en) 2005-12-02 2009-03-24 Amkor Technology, Inc. Etch singulated semiconductor package
US7572681B1 (en) 2005-12-08 2009-08-11 Amkor Technology, Inc. Embedded electronic component package
US7598598B1 (en) 2003-02-05 2009-10-06 Amkor Technology, Inc. Offset etched corner leads for semiconductor package
US7687899B1 (en) 2007-08-07 2010-03-30 Amkor Technology, Inc. Dual laminate package structure with embedded elements
US7687893B2 (en) 2006-12-27 2010-03-30 Amkor Technology, Inc. Semiconductor package having leadframe with exposed anchor pads
US7723210B2 (en) 2002-11-08 2010-05-25 Amkor Technology, Inc. Direct-write wafer level chip scale package
US7723852B1 (en) 2008-01-21 2010-05-25 Amkor Technology, Inc. Stacked semiconductor package and method of making same
US7768135B1 (en) 2008-04-17 2010-08-03 Amkor Technology, Inc. Semiconductor package with fast power-up cycle and method of making same
US7777351B1 (en) 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
US7808084B1 (en) 2008-05-06 2010-10-05 Amkor Technology, Inc. Semiconductor package with half-etched locking features
US7829990B1 (en) 2007-01-18 2010-11-09 Amkor Technology, Inc. Stackable semiconductor package including laminate interposer
US7847386B1 (en) 2007-11-05 2010-12-07 Amkor Technology, Inc. Reduced size stacked semiconductor package and method of making the same
US7847392B1 (en) 2008-09-30 2010-12-07 Amkor Technology, Inc. Semiconductor device including leadframe with increased I/O
US7875963B1 (en) 2008-11-21 2011-01-25 Amkor Technology, Inc. Semiconductor device including leadframe having power bars and increased I/O
US7902660B1 (en) 2006-05-24 2011-03-08 Amkor Technology, Inc. Substrate for semiconductor device and manufacturing method thereof
US7956453B1 (en) 2008-01-16 2011-06-07 Amkor Technology, Inc. Semiconductor package with patterning layer and method of making same
US7960818B1 (en) 2009-03-04 2011-06-14 Amkor Technology, Inc. Conformal shield on punch QFN semiconductor package
US7968998B1 (en) 2006-06-21 2011-06-28 Amkor Technology, Inc. Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package
US7977774B2 (en) 2007-07-10 2011-07-12 Amkor Technology, Inc. Fusion quad flat semiconductor package
US7982297B1 (en) 2007-03-06 2011-07-19 Amkor Technology, Inc. Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same
US7982298B1 (en) 2008-12-03 2011-07-19 Amkor Technology, Inc. Package in package semiconductor device
US7989933B1 (en) 2008-10-06 2011-08-02 Amkor Technology, Inc. Increased I/O leadframe and semiconductor device including same
US8008758B1 (en) 2008-10-27 2011-08-30 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe
US8026589B1 (en) 2009-02-23 2011-09-27 Amkor Technology, Inc. Reduced profile stackable semiconductor package
US8058715B1 (en) 2009-01-09 2011-11-15 Amkor Technology, Inc. Package in package device for RF transceiver module
US8067821B1 (en) 2008-04-10 2011-11-29 Amkor Technology, Inc. Flat semiconductor package with half package molding
US8072050B1 (en) 2008-11-18 2011-12-06 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including passive device
US8089145B1 (en) 2008-11-17 2012-01-03 Amkor Technology, Inc. Semiconductor device including increased capacity leadframe
US8089159B1 (en) 2007-10-03 2012-01-03 Amkor Technology, Inc. Semiconductor package with increased I/O density and method of making the same
US8125064B1 (en) 2008-07-28 2012-02-28 Amkor Technology, Inc. Increased I/O semiconductor package and method of making same
US8184453B1 (en) 2008-07-31 2012-05-22 Amkor Technology, Inc. Increased capacity semiconductor package
US8294276B1 (en) 2010-05-27 2012-10-23 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
US8324511B1 (en) 2010-04-06 2012-12-04 Amkor Technology, Inc. Through via nub reveal method and structure
US8390130B1 (en) 2011-01-06 2013-03-05 Amkor Technology, Inc. Through via recessed reveal structure and method
US8440554B1 (en) 2010-08-02 2013-05-14 Amkor Technology, Inc. Through via connected backside embedded circuit features structure and method
US8487420B1 (en) 2008-12-08 2013-07-16 Amkor Technology, Inc. Package in package semiconductor device with film over wire
US8487445B1 (en) 2010-10-05 2013-07-16 Amkor Technology, Inc. Semiconductor device having through electrodes protruding from dielectric layer
US8552548B1 (en) 2011-11-29 2013-10-08 Amkor Technology, Inc. Conductive pad on protruding through electrode semiconductor device
US8575742B1 (en) 2009-04-06 2013-11-05 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including power bars
US8648450B1 (en) 2011-01-27 2014-02-11 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands
US8674485B1 (en) 2010-12-08 2014-03-18 Amkor Technology, Inc. Semiconductor device including leadframe with downsets
US8680656B1 (en) 2009-01-05 2014-03-25 Amkor Technology, Inc. Leadframe structure for concentrated photovoltaic receiver package
US8791501B1 (en) 2010-12-03 2014-07-29 Amkor Technology, Inc. Integrated passive device structure and method
US8796561B1 (en) 2009-10-05 2014-08-05 Amkor Technology, Inc. Fan out build up substrate stackable package and method
US8937381B1 (en) 2009-12-03 2015-01-20 Amkor Technology, Inc. Thin stackable package and method
US9048298B1 (en) 2012-03-29 2015-06-02 Amkor Technology, Inc. Backside warpage control structure and fabrication method
US9129943B1 (en) 2012-03-29 2015-09-08 Amkor Technology, Inc. Embedded component package and fabrication method
US9184148B2 (en) 2013-10-24 2015-11-10 Amkor Technology, Inc. Semiconductor package and method therefor
US9184118B2 (en) 2013-05-02 2015-11-10 Amkor Technology Inc. Micro lead frame structure having reinforcing portions and method
US20160064310A1 (en) * 2014-08-28 2016-03-03 UTAC Headquarters Pte. Ltd. Semiconductor package having routing traces therein
US9287476B2 (en) 2008-09-03 2016-03-15 Nichia Corporation Light emitting device, resin package, resin-molded body, and methods for manufacturing light emitting device, resin package and resin-molded body
US9631481B1 (en) 2011-01-27 2017-04-25 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands and method
US9673122B2 (en) 2014-05-02 2017-06-06 Amkor Technology, Inc. Micro lead frame structure having reinforcing portions and method
US9691734B1 (en) 2009-12-07 2017-06-27 Amkor Technology, Inc. Method of forming a plurality of electronic component packages
US9704725B1 (en) 2012-03-06 2017-07-11 Amkor Technology, Inc. Semiconductor device with leadframe configured to facilitate reduced burr formation
US10811341B2 (en) 2009-01-05 2020-10-20 Amkor Technology Singapore Holding Pte Ltd. Semiconductor device with through-mold via
US11881413B2 (en) * 2019-12-04 2024-01-23 Stmicroelectronics (Tours) Sas Method for manufacturing electronic chips

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0156622B1 (en) * 1995-04-27 1998-10-15 문정환 Semiconductor leadframe and the manufacturing method

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60160639A (en) * 1984-01-31 1985-08-22 Nec Corp Semiconductor device
JPS62263666A (en) * 1986-05-10 1987-11-16 Matsushita Electronics Corp Resin sealed type semiconductor package
JPS63296252A (en) * 1987-05-27 1988-12-02 Mitsubishi Electric Corp Resin sealed semiconductor device
JPH04129252A (en) * 1990-09-20 1992-04-30 Mitsubishi Electric Corp Semiconductor package
US5122860A (en) * 1987-08-26 1992-06-16 Matsushita Electric Industrial Co., Ltd. Integrated circuit device and manufacturing method thereof
US5172214A (en) * 1991-02-06 1992-12-15 Motorola, Inc. Leadless semiconductor device and method for making the same
US5235207A (en) * 1990-07-20 1993-08-10 Hitachi, Ltd. Semiconductor device
US5250841A (en) * 1992-04-06 1993-10-05 Motorola, Inc. Semiconductor device with test-only leads

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63152161A (en) * 1986-12-17 1988-06-24 Hitachi Ltd Semiconductor device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60160639A (en) * 1984-01-31 1985-08-22 Nec Corp Semiconductor device
JPS62263666A (en) * 1986-05-10 1987-11-16 Matsushita Electronics Corp Resin sealed type semiconductor package
JPS63296252A (en) * 1987-05-27 1988-12-02 Mitsubishi Electric Corp Resin sealed semiconductor device
US5122860A (en) * 1987-08-26 1992-06-16 Matsushita Electric Industrial Co., Ltd. Integrated circuit device and manufacturing method thereof
US5235207A (en) * 1990-07-20 1993-08-10 Hitachi, Ltd. Semiconductor device
JPH04129252A (en) * 1990-09-20 1992-04-30 Mitsubishi Electric Corp Semiconductor package
US5172214A (en) * 1991-02-06 1992-12-15 Motorola, Inc. Leadless semiconductor device and method for making the same
US5250841A (en) * 1992-04-06 1993-10-05 Motorola, Inc. Semiconductor device with test-only leads

Cited By (288)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5594234A (en) * 1994-11-14 1997-01-14 Texas Instruments Incorporated Downset exposed die mount pad leadframe and package
US5770888A (en) * 1995-12-29 1998-06-23 Lg Semicon Co., Ltd. Integrated chip package with reduced dimensions and leads exposed from the top and bottom of the package
US5866939A (en) * 1996-01-21 1999-02-02 Anam Semiconductor Inc. Lead end grid array semiconductor package
DE19716668C2 (en) * 1996-05-17 1999-05-27 Lg Semicon Co Ltd Semiconductor chip stack housing with leads underneath
US5939779A (en) * 1996-05-17 1999-08-17 Lg Semicon Co., Ltd. Bottom lead semiconductor chip stack package
US5693573A (en) * 1996-06-14 1997-12-02 Lg Semicon Co., Ltd. Semiconductor package lead deflash method
US5861668A (en) * 1996-06-14 1999-01-19 Lg Semicon Co., Ltd. Semiconductor package
DE19651549B4 (en) * 1996-06-14 2004-03-18 LG Semicon Co., Ltd., Cheongju Connection frame and chip housing
US5886404A (en) * 1996-06-18 1999-03-23 Lg Semicon Co., Ltd. Bottom lead semiconductor package having folded leads
DE19725625C2 (en) * 1996-06-18 1999-08-05 Lg Semicon Co Ltd Semiconductor package with leads underneath
US6150709A (en) * 1996-06-21 2000-11-21 Anam Semiconductor Inc. Grid array type lead frame having lead ends in different planes
US5863805A (en) * 1996-07-08 1999-01-26 Industrial Technology Research Institute Method of packaging semiconductor chips based on lead-on-chip (LOC) architecture
US6045369A (en) * 1996-07-29 2000-04-04 Lg Semicon Co., Ltd. Device for mounting semiconductor package and method of fabricating same
US5998877A (en) * 1996-08-29 1999-12-07 Oki Electric Industry Co., Ltd. Semiconductor device packaged in plastic and mold employable for production thereof
US5942794A (en) * 1996-10-22 1999-08-24 Matsushita Electronics Corporation Plastic encapsulated semiconductor device and method of manufacturing the same
US6130115A (en) * 1996-10-22 2000-10-10 Matsushita Electronics Corporation Plastic encapsulated semiconductor device and method of manufacturing the same
US5963433A (en) * 1996-12-28 1999-10-05 Lg Semicon Co., Ltd. Bottom lead semiconductor package with recessed leads and fabrication method thereof
US6118174A (en) * 1996-12-28 2000-09-12 Lg Semicon Co., Ltd. Bottom lead frame and bottom lead semiconductor package using the same
US6421248B1 (en) * 1997-01-15 2002-07-16 Infineon Technologies Ag Chip card module
US6911353B2 (en) 1997-03-10 2005-06-28 Sanyo Electric Co., Ltd. Semiconductor device and method of manufacturing same
US6410363B1 (en) 1997-03-10 2002-06-25 Sanyo Electric Co., Ltd. Semiconductor device and method of manufacturing same
CN1107349C (en) * 1997-04-21 2003-04-30 日本电气株式会社 Semiconductor device, lead frame, and lead bonding
US6157074A (en) * 1997-07-16 2000-12-05 Hyundai Electronics Industries Co., Ltd. Lead frame adapted for variable sized devices, semiconductor package with such lead frame and method for using same
DE19827237B4 (en) * 1998-02-10 2006-02-02 LG Semicon Co., Ltd., Cheongju A printed circuit board substrate for a semiconductor device package and a semiconductor device package using the same, and a manufacturing method thereof
US6177718B1 (en) * 1998-04-28 2001-01-23 Kabushiki Kaisha Toshiba Resin-sealed semiconductor device
US6122822A (en) * 1998-06-23 2000-09-26 Vanguard International Semiconductor Corporation Method for balancing mold flow in encapsulating devices
US7005326B1 (en) 1998-06-24 2006-02-28 Amkor Technology, Inc. Method of making an integrated circuit package
US8963301B1 (en) 1998-06-24 2015-02-24 Amkor Technology, Inc. Integrated circuit package and method of making the same
US8853836B1 (en) 1998-06-24 2014-10-07 Amkor Technology, Inc. Integrated circuit package and method of making the same
US7030474B1 (en) 1998-06-24 2006-04-18 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
US7071541B1 (en) 1998-06-24 2006-07-04 Amkor Technology, Inc. Plastic integrated circuit package and method and leadframe for making the package
US7112474B1 (en) 1998-06-24 2006-09-26 Amkor Technology, Inc. Method of making an integrated circuit package
US8318287B1 (en) 1998-06-24 2012-11-27 Amkor Technology, Inc. Integrated circuit package and method of making the same
US9224676B1 (en) 1998-06-24 2015-12-29 Amkor Technology, Inc. Integrated circuit package and method of making the same
US6893900B1 (en) 1998-06-24 2005-05-17 Amkor Technology, Inc. Method of making an integrated circuit package
US6168975B1 (en) * 1998-06-24 2001-01-02 St Assembly Test Services Pte Ltd Method of forming extended lead package
US6630728B2 (en) * 1998-06-24 2003-10-07 Amkor Technology, Inc. Plastic integrated circuit package and leadframe for making the package
US7332375B1 (en) 1998-06-24 2008-02-19 Amkor Technology, Inc. Method of making an integrated circuit package
US7560804B1 (en) 1998-06-24 2009-07-14 Amkor Technology, Inc. Integrated circuit package and method of making the same
WO2000024056A1 (en) * 1998-10-22 2000-04-27 Azimuth Industrial Company, Inc. Semiconductor package for high frequency performance
US20030020146A1 (en) * 1998-11-20 2003-01-30 Yee Jae Hak Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant
US20080036055A1 (en) * 1998-11-20 2008-02-14 Yee Jae H Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant
US6825062B2 (en) 1998-11-20 2004-11-30 Amkor Technology, Inc. Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant
US7564122B2 (en) 1998-11-20 2009-07-21 Amkor Technology, Inc. Semiconductor package and method of making using leadframe having lead locks to secure leads to encapsulant
US7057280B2 (en) 1998-11-20 2006-06-06 Amkor Technology, Inc. Leadframe having lead locks to secure leads to encapsulant
US20040097016A1 (en) * 1998-11-20 2004-05-20 Yee Jae Hak Semiconductor package and method of making leadframe having lead locks to secure leads to encapsulant
US6265761B1 (en) * 1999-05-07 2001-07-24 Maxim Integrated Products, Inc. Semiconductor devices with improved lead frame structures
US6469369B1 (en) 1999-06-30 2002-10-22 Amkor Technology, Inc. Leadframe having a mold inflow groove and method for making
US6420779B1 (en) 1999-09-14 2002-07-16 St Assembly Test Services Ltd. Leadframe based chip scale package and method of producing the same
US20040061217A1 (en) * 1999-10-15 2004-04-01 Ku Jae Hun Thin and heat radiant semiconductor package and method for manufacturing
US6646339B1 (en) 1999-10-15 2003-11-11 Amkor Technology, Inc. Thin and heat radiant semiconductor package and method for manufacturing
US6696747B1 (en) 1999-10-15 2004-02-24 Amkor Technology, Inc. Semiconductor package having reduced thickness
US6853059B1 (en) 1999-10-15 2005-02-08 Amkor Technology, Inc. Semiconductor package having improved adhesiveness and ground bonding
US6475827B1 (en) 1999-10-15 2002-11-05 Amkor Technology, Inc. Method for making a semiconductor package having improved defect testing and increased production yield
US7067908B2 (en) 1999-10-15 2006-06-27 Amkor Technology, Inc. Semiconductor package having improved adhesiveness and ground bonding
US7321162B1 (en) 1999-10-15 2008-01-22 Amkor Technology, Inc. Semiconductor package having reduced thickness
US6677662B1 (en) 1999-10-15 2004-01-13 Amkor Technology, Inc. Clamp and heat block assembly for wire bonding a semiconductor package assembly
US20060186517A1 (en) * 1999-10-15 2006-08-24 Jang Sung S Semiconductor package having improved adhesiveness and ground bonding
US7102208B1 (en) 1999-10-15 2006-09-05 Amkor Technology, Inc. Leadframe and semiconductor package with improved solder joint strength
US6501161B1 (en) 1999-10-15 2002-12-31 Amkor Technology, Inc. Semiconductor package having increased solder joint strength
US6525406B1 (en) 1999-10-15 2003-02-25 Amkor Technology, Inc. Semiconductor device having increased moisture path and increased solder joint strength
US7115445B2 (en) 1999-10-15 2006-10-03 Amkor Technology, Inc. Semiconductor package having reduced thickness
US6555899B1 (en) 1999-10-15 2003-04-29 Amkor Technology, Inc. Semiconductor package leadframe assembly and method of manufacture
US7535085B2 (en) 1999-10-15 2009-05-19 Amkor Technology, Inc. Semiconductor package having improved adhesiveness and ground bonding
US20040227217A1 (en) * 1999-10-15 2004-11-18 Jang Sung Sik Semiconductor package having improved adhesiveness and ground bonding
US6616436B1 (en) 1999-10-15 2003-09-09 Amkor Technology, Inc. Apparatus for manufacturing semiconductor packages
US6627976B1 (en) 1999-10-15 2003-09-30 Amkor Technology, Inc. Leadframe for semiconductor package and mold for molding the same
US20070176287A1 (en) * 1999-11-05 2007-08-02 Crowley Sean T Thin integrated circuit device packages for improved radio frequency performance
US7253503B1 (en) 1999-11-05 2007-08-07 Amkor Technology, Inc. Integrated circuit device packages and substrates for making the packages
US6965157B1 (en) 1999-11-09 2005-11-15 Amkor Technology, Inc. Semiconductor package with exposed die pad and body-locking leadframe
US6427976B1 (en) * 1999-12-14 2002-08-06 Siliconware Precision Industries Co., Ltd. Lead-frame-based chip-scale package and method of manufacturing the same
US6605866B1 (en) 1999-12-16 2003-08-12 Amkor Technology, Inc. Stackable semiconductor package and method for manufacturing same
US6753597B1 (en) 1999-12-16 2004-06-22 Amkor Technology, Inc. Encapsulated semiconductor package including chip paddle and leads
US20040056338A1 (en) * 1999-12-16 2004-03-25 Crowley Sean Timothy Near chip size semiconductor package
US7045396B2 (en) 1999-12-16 2006-05-16 Amkor Technology, Inc. Stackable semiconductor package and method for manufacturing same
US6730544B1 (en) 1999-12-20 2004-05-04 Amkor Technology, Inc. Stackable semiconductor package and method for manufacturing same
US6677663B1 (en) 1999-12-30 2004-01-13 Amkor Technology, Inc. End grid array semiconductor package
KR100592784B1 (en) * 2000-01-14 2006-06-26 삼성전자주식회사 Multi chip package
US20050062148A1 (en) * 2000-03-25 2005-03-24 Seo Seong Min Semiconductor package
US6953988B2 (en) 2000-03-25 2005-10-11 Amkor Technology, Inc. Semiconductor package
US9362210B2 (en) 2000-04-27 2016-06-07 Amkor Technology, Inc. Leadframe and semiconductor package made using the leadframe
US8410585B2 (en) 2000-04-27 2013-04-02 Amkor Technology, Inc. Leadframe and semiconductor package made using the leadframe
US20060151858A1 (en) * 2000-04-27 2006-07-13 Ahn Byung H Leadframe and semiconductor package made using the leadframe
US6483177B1 (en) 2000-10-09 2002-11-19 St Assembly Test Services Ltd Leaded semiconductor packages and method of trimming and singulating such packages
US6686258B2 (en) 2000-11-02 2004-02-03 St Assembly Test Services Ltd. Method of trimming and singulating leaded semiconductor packages
US7045882B2 (en) 2000-12-29 2006-05-16 Amkor Technology, Inc. Semiconductor package including flip chip
US20050029636A1 (en) * 2000-12-29 2005-02-10 Paek Jong Sik Semiconductor package including flip chip
US20050156292A1 (en) * 2001-01-15 2005-07-21 Paek Jong S. Reduced size semiconductor package with stacked dies
US6965154B2 (en) 2001-02-08 2005-11-15 Renesas Technology Corp. Semiconductor device
US20020105061A1 (en) * 2001-02-08 2002-08-08 Shunichi Abe Semiconductor device and manufacturing method thereof
US20040178490A1 (en) * 2001-02-08 2004-09-16 Renesas Technology Corp. Semiconductor device
US6737736B2 (en) * 2001-02-08 2004-05-18 Renesas Technology Corp. Semiconductor device
US6967395B1 (en) 2001-03-20 2005-11-22 Amkor Technology, Inc. Mounting for a package containing a chip
US6777789B1 (en) 2001-03-20 2004-08-17 Amkor Technology, Inc. Mounting for a package containing a chip
US20060289973A1 (en) * 2001-03-27 2006-12-28 Lee Hyung J Lead frame for semiconductor package
US8102037B2 (en) 2001-03-27 2012-01-24 Amkor Technology, Inc. Leadframe for semiconductor package
US7928542B2 (en) 2001-03-27 2011-04-19 Amkor Technology, Inc. Lead frame for semiconductor package
US20110140250A1 (en) * 2001-03-27 2011-06-16 Hyung Ju Lee Leadframe for semiconductor package
US7170150B2 (en) 2001-03-27 2007-01-30 Amkor Technology, Inc. Lead frame for semiconductor package
US7521294B2 (en) 2001-03-27 2009-04-21 Amkor Technology, Inc. Lead frame for semiconductor package
US6846704B2 (en) 2001-03-27 2005-01-25 Amkor Technology, Inc. Semiconductor package and method for manufacturing the same
US6861736B2 (en) 2001-03-28 2005-03-01 Siliconware Precision Industries Co., Ltd. Leadframe-based semiconductor package for multi-media card
US6603196B2 (en) * 2001-03-28 2003-08-05 Siliconware Precision Industries Co., Ltd. Leadframe-based semiconductor package for multi-media card
US20030222331A1 (en) * 2001-03-28 2003-12-04 Siliconware Precision Industries Co., Ltd. Leadframe-based semiconductor package for multi-media card
US7045883B1 (en) 2001-04-04 2006-05-16 Amkor Technology, Inc. Thermally enhanced chip scale lead on chip semiconductor package and method of making same
US7064009B1 (en) 2001-04-04 2006-06-20 Amkor Technology, Inc. Thermally enhanced chip scale lead on chip semiconductor package and method of making same
US6998702B1 (en) * 2001-09-19 2006-02-14 Amkor Technology, Inc. Front edge chamfer feature for fully-molded memory cards
US7485952B1 (en) 2001-09-19 2009-02-03 Amkor Technology, Inc. Drop resistant bumpers for fully molded memory cards
US6965159B1 (en) 2001-09-19 2005-11-15 Amkor Technology, Inc. Reinforced lead-frame assembly for interconnecting circuits within a circuit module
US7176062B1 (en) 2001-09-19 2007-02-13 Amkor Technology, Inc. Lead-frame method and assembly for interconnecting circuits within a circuit module
US6873041B1 (en) 2001-11-07 2005-03-29 Amkor Technology, Inc. Power semiconductor package with strap
US6627977B1 (en) 2002-05-09 2003-09-30 Amkor Technology, Inc. Semiconductor package including isolated ring structure
US6841414B1 (en) 2002-06-19 2005-01-11 Amkor Technology, Inc. Saw and etch singulation method for a chip package
US6867071B1 (en) 2002-07-12 2005-03-15 Amkor Technology, Inc. Leadframe including corner leads and semiconductor package using same
US7508054B2 (en) 2002-08-29 2009-03-24 Hitachi, Ltd. Semiconductor device and a method of manufacturing the same
US20040041250A1 (en) * 2002-08-29 2004-03-04 Hitachi, Ltd. Semiconductor device and a method of manufacturing the same
US20050233501A1 (en) * 2002-08-29 2005-10-20 Hitachi, Ltd. Semiconductor device and a method of manufacturing the same
US6924549B2 (en) * 2002-08-29 2005-08-02 Hitachi, Ltd. Semiconductor device and a method of manufacturing the same
US6818973B1 (en) 2002-09-09 2004-11-16 Amkor Technology, Inc. Exposed lead QFP package fabricated through the use of a partial saw process
US20050139969A1 (en) * 2002-09-09 2005-06-30 Lee Choon H. Semiconductor package with increased number of input and output pins
US6995459B2 (en) 2002-09-09 2006-02-07 Amkor Technology, Inc. Semiconductor package with increased number of input and output pins
US6876068B1 (en) 2002-09-09 2005-04-05 Amkor Technology, Inc Semiconductor package with increased number of input and output pins
US7211471B1 (en) 2002-09-09 2007-05-01 Amkor Technology, Inc. Exposed lead QFP package fabricated through the use of a partial saw process
US6919620B1 (en) 2002-09-17 2005-07-19 Amkor Technology, Inc. Compact flash memory card with clamshell leadframe
US9406645B1 (en) 2002-11-08 2016-08-02 Amkor Technology, Inc. Wafer level package and fabrication method
US7932595B1 (en) 2002-11-08 2011-04-26 Amkor Technology, Inc. Electronic component package comprising fan-out traces
US7714431B1 (en) 2002-11-08 2010-05-11 Amkor Technology, Inc. Electronic component package comprising fan-out and fan-in traces
US7192807B1 (en) 2002-11-08 2007-03-20 Amkor Technology, Inc. Wafer level package and fabrication method
US7692286B1 (en) 2002-11-08 2010-04-06 Amkor Technology, Inc. Two-sided fan-out wafer escape package
US8691632B1 (en) 2002-11-08 2014-04-08 Amkor Technology, Inc. Wafer level package and fabrication method
US8501543B1 (en) 2002-11-08 2013-08-06 Amkor Technology, Inc. Direct-write wafer level chip scale package
US8298866B1 (en) 2002-11-08 2012-10-30 Amkor Technology, Inc. Wafer level package and fabrication method
US7361533B1 (en) 2002-11-08 2008-04-22 Amkor Technology, Inc. Stacked embedded leadframe
US7723210B2 (en) 2002-11-08 2010-05-25 Amkor Technology, Inc. Direct-write wafer level chip scale package
US8952522B1 (en) 2002-11-08 2015-02-10 Amkor Technology, Inc. Wafer level package and fabrication method
US8188584B1 (en) 2002-11-08 2012-05-29 Amkor Technology, Inc. Direct-write wafer level chip scale package
US7247523B1 (en) 2002-11-08 2007-07-24 Amkor Technology, Inc. Two-sided wafer escape package
US9054117B1 (en) 2002-11-08 2015-06-09 Amkor Technology, Inc. Wafer level package and fabrication method
US8486764B1 (en) 2002-11-08 2013-07-16 Amkor Technology, Inc. Wafer level package and fabrication method
US8119455B1 (en) 2002-11-08 2012-02-21 Amkor Technology, Inc. Wafer level package fabrication method
US9871015B1 (en) 2002-11-08 2018-01-16 Amkor Technology, Inc. Wafer level package and fabrication method
US8710649B1 (en) 2002-11-08 2014-04-29 Amkor Technology, Inc. Wafer level package and fabrication method
US7420272B1 (en) 2002-11-08 2008-09-02 Amkor Technology, Inc. Two-sided wafer escape package
US10665567B1 (en) 2002-11-08 2020-05-26 Amkor Technology, Inc. Wafer level package and fabrication method
US7345357B2 (en) 2002-11-27 2008-03-18 United Test And Assembly Center Ltd. High density chip scale leadframe package and method of manufacturing the package
US20040104457A1 (en) * 2002-11-27 2004-06-03 United Test And Assembly Test Center Ltd. High density chip scale leadframe package and method of manufacturing the package
US20040124508A1 (en) * 2002-11-27 2004-07-01 United Test And Assembly Test Center Ltd. High performance chip scale leadframe package and method of manufacturing the package
US7323769B2 (en) 2002-11-27 2008-01-29 United Test And Assembly Center Ltd. High performance chip scale leadframe package with thermal dissipating structure and annular element and method of manufacturing package
US8129222B2 (en) 2002-11-27 2012-03-06 United Test And Assembly Test Center Ltd. High density chip scale leadframe package and method of manufacturing the package
US20050275077A1 (en) * 2002-11-27 2005-12-15 Utac -United Test And Assembly Test Center Ltd. High density chip scale leadframe package and method of manufacturing the package
US20060202313A1 (en) * 2002-11-27 2006-09-14 Utac - United Test And Assembly Test Center Ltd. High performance chip scale leadframe with t-shape die pad and method of manufacturing package
US6798047B1 (en) 2002-12-26 2004-09-28 Amkor Technology, Inc. Pre-molded leadframe
US20050012186A1 (en) * 2003-01-29 2005-01-20 Quantum Leap Packaging, Inc. Lead for integrated circuit package
US7598598B1 (en) 2003-02-05 2009-10-06 Amkor Technology, Inc. Offset etched corner leads for semiconductor package
US6750545B1 (en) 2003-02-28 2004-06-15 Amkor Technology, Inc. Semiconductor package capable of die stacking
US6927483B1 (en) 2003-03-07 2005-08-09 Amkor Technology, Inc. Semiconductor package exhibiting efficient lead placement
US6794740B1 (en) 2003-03-13 2004-09-21 Amkor Technology, Inc. Leadframe package for semiconductor devices
US6844615B1 (en) 2003-03-13 2005-01-18 Amkor Technology, Inc. Leadframe package for semiconductor devices
US7001799B1 (en) 2003-03-13 2006-02-21 Amkor Technology, Inc. Method of making a leadframe for semiconductor devices
US6879034B1 (en) 2003-05-01 2005-04-12 Amkor Technology, Inc. Semiconductor package including low temperature co-fired ceramic substrate
US7095103B1 (en) 2003-05-01 2006-08-22 Amkor Technology, Inc. Leadframe based memory card
US7008825B1 (en) 2003-05-27 2006-03-07 Amkor Technology, Inc. Leadframe strip having enhanced testability
US6897550B1 (en) 2003-06-11 2005-05-24 Amkor Technology, Inc. Fully-molded leadframe stand-off feature
US20050054141A1 (en) * 2003-08-23 2005-03-10 Jin-Ho Kim Thin semiconductor package having stackable lead frame and method of manufacturing the same
US7364784B2 (en) 2003-08-23 2008-04-29 Samsung Electronics Co., Ltd. Thin semiconductor package having stackable lead frame and method of manufacturing the same
US7615859B2 (en) 2003-08-23 2009-11-10 Samsung Electronics Co., Ltd. Thin semiconductor package having stackable lead frame and method of manufacturing the same
US20080164586A1 (en) * 2003-08-23 2008-07-10 Samsung Electronics Co., Ltd. Thin semiconductor package having stackable lead frame and method of manufacturing the same
US7245007B1 (en) 2003-09-18 2007-07-17 Amkor Technology, Inc. Exposed lead interposer leadframe package
US20050062139A1 (en) * 2003-09-24 2005-03-24 Chung-Hsing Tzu Reinforced die pad support structure
US7138707B1 (en) 2003-10-21 2006-11-21 Amkor Technology, Inc. Semiconductor package including leads and conductive posts for providing increased functionality
US7144517B1 (en) 2003-11-07 2006-12-05 Amkor Technology, Inc. Manufacturing method for leadframe and for semiconductor package using the leadframe
US7214326B1 (en) 2003-11-07 2007-05-08 Amkor Technology, Inc. Increased capacity leadframe and semiconductor package using the same
US7211879B1 (en) 2003-11-12 2007-05-01 Amkor Technology, Inc. Semiconductor package with chamfered corners and method of manufacturing the same
US20050127532A1 (en) * 2003-12-09 2005-06-16 Leeshawn Luo Inverted J-lead package for power devices
US7633140B2 (en) * 2003-12-09 2009-12-15 Alpha And Omega Semiconductor Incorporated Inverted J-lead for power devices
US7057268B1 (en) 2004-01-27 2006-06-06 Amkor Technology, Inc. Cavity case with clip/plug for use on multi-media card
US7091594B1 (en) 2004-01-28 2006-08-15 Amkor Technology, Inc. Leadframe type semiconductor package having reduced inductance and its manufacturing method
US20080003722A1 (en) * 2004-04-15 2008-01-03 Chun David D Transfer mold solution for molded multi-media card
US7190062B1 (en) 2004-06-15 2007-03-13 Amkor Technology, Inc. Embedded leadframe semiconductor package
US7202554B1 (en) 2004-08-19 2007-04-10 Amkor Technology, Inc. Semiconductor package and its manufacturing method
US7217991B1 (en) 2004-10-22 2007-05-15 Amkor Technology, Inc. Fan-in leadframe semiconductor package
US7309910B2 (en) 2004-10-22 2007-12-18 Tessera, Inc. Micro lead frame packages and methods of manufacturing the same
US7473584B1 (en) 2004-10-22 2009-01-06 Amkor Technology, Inc. Method for fabricating a fan-in leadframe semiconductor package
US7202112B2 (en) 2004-10-22 2007-04-10 Tessera, Inc. Micro lead frame packages and methods of manufacturing the same
US20070105282A1 (en) * 2004-10-22 2007-05-10 Tessera, Inc. Micro lead frame packages and methods of manufacturing the same
US20060099789A1 (en) * 2004-10-22 2006-05-11 Tessera, Inc. Micro lead frame packages and methods of manufacturing the same
US7507603B1 (en) 2005-12-02 2009-03-24 Amkor Technology, Inc. Etch singulated semiconductor package
US7732899B1 (en) 2005-12-02 2010-06-08 Amkor Technology, Inc. Etch singulated semiconductor package
US7977163B1 (en) 2005-12-08 2011-07-12 Amkor Technology, Inc. Embedded electronic component package fabrication method
US7572681B1 (en) 2005-12-08 2009-08-11 Amkor Technology, Inc. Embedded electronic component package
US7902660B1 (en) 2006-05-24 2011-03-08 Amkor Technology, Inc. Substrate for semiconductor device and manufacturing method thereof
US8441110B1 (en) 2006-06-21 2013-05-14 Amkor Technology, Inc. Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package
US7968998B1 (en) 2006-06-21 2011-06-28 Amkor Technology, Inc. Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package
US7687893B2 (en) 2006-12-27 2010-03-30 Amkor Technology, Inc. Semiconductor package having leadframe with exposed anchor pads
US8089141B1 (en) 2006-12-27 2012-01-03 Amkor Technology, Inc. Semiconductor package having leadframe with exposed anchor pads
US7829990B1 (en) 2007-01-18 2010-11-09 Amkor Technology, Inc. Stackable semiconductor package including laminate interposer
US7982297B1 (en) 2007-03-06 2011-07-19 Amkor Technology, Inc. Stackable semiconductor package having partially exposed semiconductor die and method of fabricating the same
US7960815B2 (en) * 2007-03-22 2011-06-14 Stats Chippac, Ltd. Leadframe design for QFN package with top terminal leads
US20090166821A1 (en) * 2007-03-22 2009-07-02 Stats Chippac, Ltd. Leadframe Design for QFN Package with Top Terminal Leads
US7517733B2 (en) * 2007-03-22 2009-04-14 Stats Chippac, Ltd. Leadframe design for QFN package with top terminal leads
US20080230876A1 (en) * 2007-03-22 2008-09-25 Stats Chippac, Ltd. Leadframe Design for QFN Package with Top Terminal Leads
US8304866B1 (en) 2007-07-10 2012-11-06 Amkor Technology, Inc. Fusion quad flat semiconductor package
US7977774B2 (en) 2007-07-10 2011-07-12 Amkor Technology, Inc. Fusion quad flat semiconductor package
US7872343B1 (en) 2007-08-07 2011-01-18 Amkor Technology, Inc. Dual laminate package structure with embedded elements
US8283767B1 (en) 2007-08-07 2012-10-09 Amkor Technology, Inc. Dual laminate package structure with embedded elements
US7687899B1 (en) 2007-08-07 2010-03-30 Amkor Technology, Inc. Dual laminate package structure with embedded elements
US8319338B1 (en) 2007-10-01 2012-11-27 Amkor Technology, Inc. Thin stacked interposer package
US7777351B1 (en) 2007-10-01 2010-08-17 Amkor Technology, Inc. Thin stacked interposer package
US8089159B1 (en) 2007-10-03 2012-01-03 Amkor Technology, Inc. Semiconductor package with increased I/O density and method of making the same
US8227921B1 (en) 2007-10-03 2012-07-24 Amkor Technology, Inc. Semiconductor package with increased I/O density and method of making same
US7847386B1 (en) 2007-11-05 2010-12-07 Amkor Technology, Inc. Reduced size stacked semiconductor package and method of making the same
US7956453B1 (en) 2008-01-16 2011-06-07 Amkor Technology, Inc. Semiconductor package with patterning layer and method of making same
US8729710B1 (en) 2008-01-16 2014-05-20 Amkor Technology, Inc. Semiconductor package with patterning layer and method of making same
US7723852B1 (en) 2008-01-21 2010-05-25 Amkor Technology, Inc. Stacked semiconductor package and method of making same
US7906855B1 (en) 2008-01-21 2011-03-15 Amkor Technology, Inc. Stacked semiconductor package and method of making same
US8067821B1 (en) 2008-04-10 2011-11-29 Amkor Technology, Inc. Flat semiconductor package with half package molding
US7768135B1 (en) 2008-04-17 2010-08-03 Amkor Technology, Inc. Semiconductor package with fast power-up cycle and method of making same
US8084868B1 (en) 2008-04-17 2011-12-27 Amkor Technology, Inc. Semiconductor package with fast power-up cycle and method of making same
US7808084B1 (en) 2008-05-06 2010-10-05 Amkor Technology, Inc. Semiconductor package with half-etched locking features
US8125064B1 (en) 2008-07-28 2012-02-28 Amkor Technology, Inc. Increased I/O semiconductor package and method of making same
US8184453B1 (en) 2008-07-31 2012-05-22 Amkor Technology, Inc. Increased capacity semiconductor package
US9490411B2 (en) 2008-09-03 2016-11-08 Nichia Corporation Light emitting device, resin package, resin-molded body, and methods for manufacturing light emitting device, resin package and resin-molded body
US9287476B2 (en) 2008-09-03 2016-03-15 Nichia Corporation Light emitting device, resin package, resin-molded body, and methods for manufacturing light emitting device, resin package and resin-molded body
US11094854B2 (en) 2008-09-03 2021-08-17 Nichia Corporation Light emitting device, resin package, resin-molded body, and methods for manufacturing light emitting device, resin package and resin-molded body
US9537071B2 (en) 2008-09-03 2017-01-03 Nichia Corporation Light emitting device, resin package, resin-molded body, and methods for manufacturing light emitting device, resin package and resin-molded body
US10700241B2 (en) 2008-09-03 2020-06-30 Nichia Corporation Light emitting device, resin package, resin-molded body, and methods for manufacturing light emitting device, resin package and resin-molded body
US10115870B2 (en) 2008-09-03 2018-10-30 Nichia Corporation Light emitting device, resin package, resin-molded body, and methods for manufacturing light emitting device, resin package and resin-molded body
US10573789B2 (en) 2008-09-03 2020-02-25 Nichia Corporation Light emitting device, resin package, resin-molded body, and methods for manufacturing light emitting device, resin package and resin-molded body
US10573788B2 (en) 2008-09-03 2020-02-25 Nichia Corporation Light emitting device, resin package, resin-molded body, and methods for manufacturing light emitting device, resin package and resin-molded body
US7847392B1 (en) 2008-09-30 2010-12-07 Amkor Technology, Inc. Semiconductor device including leadframe with increased I/O
US8299602B1 (en) 2008-09-30 2012-10-30 Amkor Technology, Inc. Semiconductor device including leadframe with increased I/O
US8432023B1 (en) 2008-10-06 2013-04-30 Amkor Technology, Inc. Increased I/O leadframe and semiconductor device including same
US7989933B1 (en) 2008-10-06 2011-08-02 Amkor Technology, Inc. Increased I/O leadframe and semiconductor device including same
US8008758B1 (en) 2008-10-27 2011-08-30 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe
US8823152B1 (en) 2008-10-27 2014-09-02 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe
US8089145B1 (en) 2008-11-17 2012-01-03 Amkor Technology, Inc. Semiconductor device including increased capacity leadframe
US8072050B1 (en) 2008-11-18 2011-12-06 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including passive device
US8188579B1 (en) 2008-11-21 2012-05-29 Amkor Technology, Inc. Semiconductor device including leadframe having power bars and increased I/O
US7875963B1 (en) 2008-11-21 2011-01-25 Amkor Technology, Inc. Semiconductor device including leadframe having power bars and increased I/O
US7982298B1 (en) 2008-12-03 2011-07-19 Amkor Technology, Inc. Package in package semiconductor device
US8487420B1 (en) 2008-12-08 2013-07-16 Amkor Technology, Inc. Package in package semiconductor device with film over wire
US10811341B2 (en) 2009-01-05 2020-10-20 Amkor Technology Singapore Holding Pte Ltd. Semiconductor device with through-mold via
US11869829B2 (en) 2009-01-05 2024-01-09 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor device with through-mold via
US8680656B1 (en) 2009-01-05 2014-03-25 Amkor Technology, Inc. Leadframe structure for concentrated photovoltaic receiver package
US8058715B1 (en) 2009-01-09 2011-11-15 Amkor Technology, Inc. Package in package device for RF transceiver module
US8558365B1 (en) 2009-01-09 2013-10-15 Amkor Technology, Inc. Package in package device for RF transceiver module
US8026589B1 (en) 2009-02-23 2011-09-27 Amkor Technology, Inc. Reduced profile stackable semiconductor package
US7960818B1 (en) 2009-03-04 2011-06-14 Amkor Technology, Inc. Conformal shield on punch QFN semiconductor package
US8729682B1 (en) 2009-03-04 2014-05-20 Amkor Technology, Inc. Conformal shield on punch QFN semiconductor package
US8575742B1 (en) 2009-04-06 2013-11-05 Amkor Technology, Inc. Semiconductor device with increased I/O leadframe including power bars
US8796561B1 (en) 2009-10-05 2014-08-05 Amkor Technology, Inc. Fan out build up substrate stackable package and method
US8937381B1 (en) 2009-12-03 2015-01-20 Amkor Technology, Inc. Thin stackable package and method
US9691734B1 (en) 2009-12-07 2017-06-27 Amkor Technology, Inc. Method of forming a plurality of electronic component packages
US10546833B2 (en) 2009-12-07 2020-01-28 Amkor Technology, Inc. Method of forming a plurality of electronic component packages
US9324614B1 (en) 2010-04-06 2016-04-26 Amkor Technology, Inc. Through via nub reveal method and structure
US8324511B1 (en) 2010-04-06 2012-12-04 Amkor Technology, Inc. Through via nub reveal method and structure
US8294276B1 (en) 2010-05-27 2012-10-23 Amkor Technology, Inc. Semiconductor device and fabricating method thereof
US9159672B1 (en) 2010-08-02 2015-10-13 Amkor Technology, Inc. Through via connected backside embedded circuit features structure and method
US8440554B1 (en) 2010-08-02 2013-05-14 Amkor Technology, Inc. Through via connected backside embedded circuit features structure and method
US8900995B1 (en) 2010-10-05 2014-12-02 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US8487445B1 (en) 2010-10-05 2013-07-16 Amkor Technology, Inc. Semiconductor device having through electrodes protruding from dielectric layer
US8791501B1 (en) 2010-12-03 2014-07-29 Amkor Technology, Inc. Integrated passive device structure and method
US8674485B1 (en) 2010-12-08 2014-03-18 Amkor Technology, Inc. Semiconductor device including leadframe with downsets
US8390130B1 (en) 2011-01-06 2013-03-05 Amkor Technology, Inc. Through via recessed reveal structure and method
US9082833B1 (en) 2011-01-06 2015-07-14 Amkor Technology, Inc. Through via recessed reveal structure and method
US9275939B1 (en) 2011-01-27 2016-03-01 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands and method
US9508631B1 (en) 2011-01-27 2016-11-29 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands and method
US8648450B1 (en) 2011-01-27 2014-02-11 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands
US9631481B1 (en) 2011-01-27 2017-04-25 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands and method
US9978695B1 (en) 2011-01-27 2018-05-22 Amkor Technology, Inc. Semiconductor device including leadframe with a combination of leads and lands and method
US8981572B1 (en) 2011-11-29 2015-03-17 Amkor Technology, Inc. Conductive pad on protruding through electrode semiconductor device
US10410967B1 (en) 2011-11-29 2019-09-10 Amkor Technology, Inc. Electronic device comprising a conductive pad on a protruding-through electrode
US9947623B1 (en) 2011-11-29 2018-04-17 Amkor Technology, Inc. Semiconductor device comprising a conductive pad on a protruding-through electrode
US8552548B1 (en) 2011-11-29 2013-10-08 Amkor Technology, Inc. Conductive pad on protruding through electrode semiconductor device
US11043458B2 (en) 2011-11-29 2021-06-22 Amkor Technology Singapore Holding Pte. Ltd. Method of manufacturing an electronic device comprising a conductive pad on a protruding-through electrode
US9431323B1 (en) 2011-11-29 2016-08-30 Amkor Technology, Inc. Conductive pad on protruding through electrode
US10090228B1 (en) 2012-03-06 2018-10-02 Amkor Technology, Inc. Semiconductor device with leadframe configured to facilitate reduced burr formation
US9704725B1 (en) 2012-03-06 2017-07-11 Amkor Technology, Inc. Semiconductor device with leadframe configured to facilitate reduced burr formation
US9129943B1 (en) 2012-03-29 2015-09-08 Amkor Technology, Inc. Embedded component package and fabrication method
US10014240B1 (en) 2012-03-29 2018-07-03 Amkor Technology, Inc. Embedded component package and fabrication method
US9048298B1 (en) 2012-03-29 2015-06-02 Amkor Technology, Inc. Backside warpage control structure and fabrication method
US9184118B2 (en) 2013-05-02 2015-11-10 Amkor Technology Inc. Micro lead frame structure having reinforcing portions and method
US9543235B2 (en) 2013-10-24 2017-01-10 Amkor Technology, Inc. Semiconductor package and method therefor
US9184148B2 (en) 2013-10-24 2015-11-10 Amkor Technology, Inc. Semiconductor package and method therefor
US9673122B2 (en) 2014-05-02 2017-06-06 Amkor Technology, Inc. Micro lead frame structure having reinforcing portions and method
US9564387B2 (en) * 2014-08-28 2017-02-07 UTAC Headquarters Pte. Ltd. Semiconductor package having routing traces therein
US20160064310A1 (en) * 2014-08-28 2016-03-03 UTAC Headquarters Pte. Ltd. Semiconductor package having routing traces therein
US11881413B2 (en) * 2019-12-04 2024-01-23 Stmicroelectronics (Tours) Sas Method for manufacturing electronic chips

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JP2599748Y2 (en) 1999-09-20

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