US5485592A - Write back cache controller method and apparatus for use in a system having a CPU with internal cache memory - Google Patents
Write back cache controller method and apparatus for use in a system having a CPU with internal cache memory Download PDFInfo
- Publication number
- US5485592A US5485592A US08/090,517 US9051793A US5485592A US 5485592 A US5485592 A US 5485592A US 9051793 A US9051793 A US 9051793A US 5485592 A US5485592 A US 5485592A
- Authority
- US
- United States
- Prior art keywords
- cache
- bus
- memory
- external
- write
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
Description
Claims (5)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/090,517 US5485592A (en) | 1992-04-07 | 1993-07-12 | Write back cache controller method and apparatus for use in a system having a CPU with internal cache memory |
PCT/US1994/007832 WO1995003568A2 (en) | 1993-07-12 | 1994-07-12 | Write back cache controller method and apparatus for use in a system having a cpu with internal cache memory |
AU73308/94A AU7330894A (en) | 1993-07-12 | 1994-07-12 | Write back cache controller method and apparatus for use in a system having a cpu with internal cache memory |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US86453592A | 1992-04-07 | 1992-04-07 | |
US08/090,517 US5485592A (en) | 1992-04-07 | 1993-07-12 | Write back cache controller method and apparatus for use in a system having a CPU with internal cache memory |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US86453592A Continuation-In-Part | 1992-04-07 | 1992-04-07 |
Publications (1)
Publication Number | Publication Date |
---|---|
US5485592A true US5485592A (en) | 1996-01-16 |
Family
ID=22223131
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/090,517 Expired - Lifetime US5485592A (en) | 1992-04-07 | 1993-07-12 | Write back cache controller method and apparatus for use in a system having a CPU with internal cache memory |
Country Status (3)
Country | Link |
---|---|
US (1) | US5485592A (en) |
AU (1) | AU7330894A (en) |
WO (1) | WO1995003568A2 (en) |
Cited By (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5623633A (en) * | 1993-07-27 | 1997-04-22 | Dell Usa, L.P. | Cache-based computer system employing a snoop control circuit with write-back suppression |
US5699548A (en) * | 1995-06-01 | 1997-12-16 | Intel Corporation | Method and apparatus for selecting a mode for updating external memory |
US5768558A (en) * | 1994-08-29 | 1998-06-16 | Intel Corporation | Identification of the distinction between the beginning of a new write back cycle and an ongoing write cycle |
US5787486A (en) * | 1995-12-15 | 1998-07-28 | International Business Machines Corporation | Bus protocol for locked cycle cache hit |
US5802577A (en) * | 1995-03-17 | 1998-09-01 | Intel Corporation | Multi-processing cache coherency protocol on a local bus |
US5862358A (en) * | 1994-12-20 | 1999-01-19 | Digital Equipment Corporation | Method and apparatus for reducing the apparent read latency when connecting busses with fixed read reply timeouts to CPUs with write-back caches |
US20020108021A1 (en) * | 2001-02-08 | 2002-08-08 | Syed Moinul I. | High performance cache and method for operating same |
US20020108019A1 (en) * | 2001-02-08 | 2002-08-08 | Allen Michael S. | Cache system with DMA capabilities and method for operating same |
US20030061452A1 (en) * | 2001-09-27 | 2003-03-27 | Kabushiki Kaisha Toshiba | Processor and method of arithmetic processing thereof |
US6560675B1 (en) * | 1999-12-30 | 2003-05-06 | Unisys Corporation | Method for controlling concurrent cache replace and return across an asynchronous interface |
US20050114559A1 (en) * | 2003-11-20 | 2005-05-26 | Miller George B. | Method for efficiently processing DMA transactions |
US20050144397A1 (en) * | 2003-12-29 | 2005-06-30 | Rudd Kevin W. | Method and apparatus for enabling volatile shared data across caches in a coherent memory multiprocessor system to reduce coherency traffic |
US20070002607A1 (en) * | 2005-06-29 | 2007-01-04 | Khellah Muhammad M | Memory circuit |
US20080162986A1 (en) * | 2006-12-28 | 2008-07-03 | Intel Corporation | Memory cell bit valve loss detection and restoration |
US20110258393A1 (en) * | 2010-04-16 | 2011-10-20 | Pmc Sierra, Inc. | Mirrored cache protection |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5623070A (en) | 1990-07-27 | 1997-04-22 | Isis Pharmaceuticals, Inc. | Heteroatomic oligonucleoside linkages |
ATE251638T1 (en) | 1996-06-06 | 2003-10-15 | Novartis Pharma Gmbh | 2-SUBSTITUTED NUCLEOSIDE AND OLIGONUCLEOTIDE DERIVATIVES |
Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5023776A (en) * | 1988-02-22 | 1991-06-11 | International Business Machines Corp. | Store queue for a tightly coupled multiple processor configuration with two-level cache buffer storage |
US5091846A (en) * | 1986-10-03 | 1992-02-25 | Intergraph Corporation | Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency |
US5119485A (en) * | 1989-05-15 | 1992-06-02 | Motorola, Inc. | Method for data bus snooping in a data processing system by selective concurrent read and invalidate cache operation |
US5155824A (en) * | 1989-05-15 | 1992-10-13 | Motorola, Inc. | System for transferring selected data words between main memory and cache with multiple data words and multiple dirty bits for each address |
US5168560A (en) * | 1987-05-29 | 1992-12-01 | Amdahl Corporation | Microprocessor system private split cache tag stores with the system tag store having a different validity bit for the same data line |
US5210848A (en) * | 1989-02-22 | 1993-05-11 | International Business Machines Corporation | Multi-processor caches with large granularity exclusivity locking |
US5261109A (en) * | 1990-12-21 | 1993-11-09 | Intel Corporation | Distributed arbitration method and apparatus for a computer bus using arbitration groups |
US5276852A (en) * | 1990-10-01 | 1994-01-04 | Digital Equipment Corporation | Method and apparatus for controlling a processor bus used by multiple processor components during writeback cache transactions |
US5317720A (en) * | 1990-06-29 | 1994-05-31 | Digital Equipment Corporation | Processor system with writeback cache using writeback and non writeback transactions stored in separate queues |
US5319766A (en) * | 1992-04-24 | 1994-06-07 | Digital Equipment Corporation | Duplicate tag store for a processor having primary and backup cache memories in a multiprocessor computer system |
US5325504A (en) * | 1991-08-30 | 1994-06-28 | Compaq Computer Corporation | Method and apparatus for incorporating cache line replacement and cache write policy information into tag directories in a cache system |
US5335335A (en) * | 1991-08-30 | 1994-08-02 | Compaq Computer Corporation | Multiprocessor cache snoop access protocol wherein snoop means performs snooping operations after host bus cycle completion and delays subsequent host bus cycles until snooping operations are completed |
US5345576A (en) * | 1991-12-31 | 1994-09-06 | Intel Corporation | Microprocessor simultaneously issues an access to an external cache over an external cache bus and to an internal cache, cancels the external cache access on an internal cache hit, and reissues the access over a main memory bus on an external cache miss |
US5353415A (en) * | 1992-10-02 | 1994-10-04 | Compaq Computer Corporation | Method and apparatus for concurrency of bus operations |
-
1993
- 1993-07-12 US US08/090,517 patent/US5485592A/en not_active Expired - Lifetime
-
1994
- 1994-07-12 WO PCT/US1994/007832 patent/WO1995003568A2/en active Application Filing
- 1994-07-12 AU AU73308/94A patent/AU7330894A/en not_active Abandoned
Patent Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5091846A (en) * | 1986-10-03 | 1992-02-25 | Intergraph Corporation | Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency |
US5168560A (en) * | 1987-05-29 | 1992-12-01 | Amdahl Corporation | Microprocessor system private split cache tag stores with the system tag store having a different validity bit for the same data line |
US5023776A (en) * | 1988-02-22 | 1991-06-11 | International Business Machines Corp. | Store queue for a tightly coupled multiple processor configuration with two-level cache buffer storage |
US5210848A (en) * | 1989-02-22 | 1993-05-11 | International Business Machines Corporation | Multi-processor caches with large granularity exclusivity locking |
US5119485A (en) * | 1989-05-15 | 1992-06-02 | Motorola, Inc. | Method for data bus snooping in a data processing system by selective concurrent read and invalidate cache operation |
US5155824A (en) * | 1989-05-15 | 1992-10-13 | Motorola, Inc. | System for transferring selected data words between main memory and cache with multiple data words and multiple dirty bits for each address |
US5317720A (en) * | 1990-06-29 | 1994-05-31 | Digital Equipment Corporation | Processor system with writeback cache using writeback and non writeback transactions stored in separate queues |
US5276852A (en) * | 1990-10-01 | 1994-01-04 | Digital Equipment Corporation | Method and apparatus for controlling a processor bus used by multiple processor components during writeback cache transactions |
US5261109A (en) * | 1990-12-21 | 1993-11-09 | Intel Corporation | Distributed arbitration method and apparatus for a computer bus using arbitration groups |
US5325504A (en) * | 1991-08-30 | 1994-06-28 | Compaq Computer Corporation | Method and apparatus for incorporating cache line replacement and cache write policy information into tag directories in a cache system |
US5335335A (en) * | 1991-08-30 | 1994-08-02 | Compaq Computer Corporation | Multiprocessor cache snoop access protocol wherein snoop means performs snooping operations after host bus cycle completion and delays subsequent host bus cycles until snooping operations are completed |
US5345576A (en) * | 1991-12-31 | 1994-09-06 | Intel Corporation | Microprocessor simultaneously issues an access to an external cache over an external cache bus and to an internal cache, cancels the external cache access on an internal cache hit, and reissues the access over a main memory bus on an external cache miss |
US5319766A (en) * | 1992-04-24 | 1994-06-07 | Digital Equipment Corporation | Duplicate tag store for a processor having primary and backup cache memories in a multiprocessor computer system |
US5353415A (en) * | 1992-10-02 | 1994-10-04 | Compaq Computer Corporation | Method and apparatus for concurrency of bus operations |
Cited By (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5623633A (en) * | 1993-07-27 | 1997-04-22 | Dell Usa, L.P. | Cache-based computer system employing a snoop control circuit with write-back suppression |
US5768558A (en) * | 1994-08-29 | 1998-06-16 | Intel Corporation | Identification of the distinction between the beginning of a new write back cycle and an ongoing write cycle |
US5862358A (en) * | 1994-12-20 | 1999-01-19 | Digital Equipment Corporation | Method and apparatus for reducing the apparent read latency when connecting busses with fixed read reply timeouts to CPUs with write-back caches |
US6226703B1 (en) * | 1994-12-20 | 2001-05-01 | Compaq Computer Corporation | Method and apparatus for reducing the apparent read latency when connecting busses with fixed read replay timeouts to CPU'S with write-back caches |
US5802577A (en) * | 1995-03-17 | 1998-09-01 | Intel Corporation | Multi-processing cache coherency protocol on a local bus |
US5699548A (en) * | 1995-06-01 | 1997-12-16 | Intel Corporation | Method and apparatus for selecting a mode for updating external memory |
US5787486A (en) * | 1995-12-15 | 1998-07-28 | International Business Machines Corporation | Bus protocol for locked cycle cache hit |
US6560675B1 (en) * | 1999-12-30 | 2003-05-06 | Unisys Corporation | Method for controlling concurrent cache replace and return across an asynchronous interface |
US20020108019A1 (en) * | 2001-02-08 | 2002-08-08 | Allen Michael S. | Cache system with DMA capabilities and method for operating same |
US20020108021A1 (en) * | 2001-02-08 | 2002-08-08 | Syed Moinul I. | High performance cache and method for operating same |
US6988167B2 (en) * | 2001-02-08 | 2006-01-17 | Analog Devices, Inc. | Cache system with DMA capabilities and method for operating same |
US20030061452A1 (en) * | 2001-09-27 | 2003-03-27 | Kabushiki Kaisha Toshiba | Processor and method of arithmetic processing thereof |
US6931495B2 (en) | 2001-09-27 | 2005-08-16 | Kabushiki Kaisha Toshiba | Processor and method of arithmetic processing thereof |
US20050114559A1 (en) * | 2003-11-20 | 2005-05-26 | Miller George B. | Method for efficiently processing DMA transactions |
US20050144397A1 (en) * | 2003-12-29 | 2005-06-30 | Rudd Kevin W. | Method and apparatus for enabling volatile shared data across caches in a coherent memory multiprocessor system to reduce coherency traffic |
US20070002607A1 (en) * | 2005-06-29 | 2007-01-04 | Khellah Muhammad M | Memory circuit |
US20080162986A1 (en) * | 2006-12-28 | 2008-07-03 | Intel Corporation | Memory cell bit valve loss detection and restoration |
US7653846B2 (en) | 2006-12-28 | 2010-01-26 | Intel Corporation | Memory cell bit valve loss detection and restoration |
US20110258393A1 (en) * | 2010-04-16 | 2011-10-20 | Pmc Sierra, Inc. | Mirrored cache protection |
US8806134B2 (en) * | 2010-04-16 | 2014-08-12 | Pmc-Sierra Us, Inc. | Mirrored cache protection |
Also Published As
Publication number | Publication date |
---|---|
WO1995003568A3 (en) | 1995-10-12 |
AU7330894A (en) | 1995-02-20 |
WO1995003568A2 (en) | 1995-02-02 |
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Legal Events
Date | Code | Title | Description |
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STPP | Information on status: patent application and granting procedure in general |
Free format text: APPLICATION UNDERGOING PREEXAM PROCESSING |
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AS | Assignment |
Owner name: EXXON CHEMICAL PATENTS INC., DELAWARE Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:VERDUIJN, JOHANNES PETRUS;REEL/FRAME:007117/0162 Effective date: 19930820 |
|
AS | Assignment |
Owner name: VIDEO TECHNOLOGY COMPUTERS, LTD., HONG KONG Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LAU, TIM Y.T.;REEL/FRAME:007614/0756 Effective date: 19930907 |
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