US5497019A - Silicon-on-insulator gate-all-around MOSFET devices and fabrication methods - Google Patents
Silicon-on-insulator gate-all-around MOSFET devices and fabrication methods Download PDFInfo
- Publication number
- US5497019A US5497019A US08/310,915 US31091594A US5497019A US 5497019 A US5497019 A US 5497019A US 31091594 A US31091594 A US 31091594A US 5497019 A US5497019 A US 5497019A
- Authority
- US
- United States
- Prior art keywords
- gate dielectric
- bottom gate
- top gate
- gate electrode
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000012212 insulator Substances 0.000 title claims abstract description 44
- 238000000034 method Methods 0.000 title description 37
- 238000004519 manufacturing process Methods 0.000 title description 5
- 239000004065 semiconductor Substances 0.000 claims abstract description 34
- 239000004020 conductor Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims description 22
- 239000000463 material Substances 0.000 claims description 6
- 235000012431 wafers Nutrition 0.000 abstract description 64
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 42
- 229910052710 silicon Inorganic materials 0.000 abstract description 42
- 239000010703 silicon Substances 0.000 abstract description 42
- 230000003071 parasitic effect Effects 0.000 abstract description 5
- 238000002955 isolation Methods 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract description 3
- 230000005669 field effect Effects 0.000 abstract description 2
- 230000008569 process Effects 0.000 description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 14
- 229920005591 polysilicon Polymers 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000005855 radiation Effects 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 230000008901 benefit Effects 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 230000007547 defect Effects 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000004075 alteration Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000036039 immunity Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 230000000191 radiation effect Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
- H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/012—Bonding, e.g. electrostatic for strain gauges
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/135—Removal of substrate
Definitions
- This invention relates to the class of transistors called metal-oxide-semiconductor field-effect transistors (MOSFETs) and more particularly to MOSFETs formed in semiconductor layers on insulated substrates of a silicon-on-insulator (SOI) wafer, and more particularly to the class of SOI MOSFETs formed with gate electrodes at the top and bottom of the semiconductor layer substantially forming gate-all-around (GAA) MOSFETs, hereinafter referred to as SOI GAA MOSFETs.
- MOSFETs metal-oxide-semiconductor field-effect transistors
- SOI silicon-on-insulator
- the general problem to which this invention is addressed is the improvement in performance and reliability of the SOI MOSFET, which is the active element common to many microelectronic circuits.
- a conventional MOSFET operates by driving current through the channel region between the source and drain of the device. The conductivity of the channel region is modulated by the application of a voltage on the conducting gate above the channel surface and insulated from it.
- Efforts are ongoing within many MOS integrated circuit manufacturing companies as well as at many universities and government laboratories to improve the speed and available drive current of the SOI MOSFET, to reduce its power consumption, and to improve its reliability and radiation hardness for applications in harsh or remote environments, including space.
- Silicon-on-insulator is the generic term describing those technologies in which the MOSFETs or other active devices are built in a thin film of silicon over an insulating layer or substrate.
- the presence of the insulator reduces the parasitic capacitances in the MOSFET compared to a bulk silicon device, resulting in inherent improvements in the speed and power dissipation of MOS integrated circuits, as well as improved immunity to single-event upset of MOS memory elements in a radiation environment.
- the presence of the back interface in the SOI MOSFET can lead to failure of the integrated circuit in a radiation environment caused by charging of the silicon/insulator interface by radiation-induced interface states or fixed charges at this interface (D. C. Mayer, Modes of Operation and Radiation Sensitivity of Ultrathin SOI Transistors, IEEE Trans. Electron Devices, 37, 1280, 1990).
- the SOI gate-all-around (GAA) MOSFET has been described and fabricated to improve the performance of the SOI MOSFET.
- DELTA Fully Depleted Lean-Channel Transistor
- DELTA Fully Depleted Lean-Channel Transistor
- IEDM Tech. Digest 833 (1989)
- J. P. Colinge et al. Silicon-on-Insulator Gate-All-Around Device, IEDM Tech. Digest, 595, 1990.
- this bottom active gate creates an enlarged channel of the MOSFET and thereby contributes to the drive current by adding a back surface current to the device front surface current created by the top active gate.
- the SOI GAA MOSFET has also demonstrated improved radiation hardness (R. K. Lawrence and H. L. Hughes, Radiation Effects in Gate-All-Around Structures, 1991 IEEE International SOI Conf. Proc., 80, 1991).
- the bottom surface of the mesa is defined and delineated by the Separation by Implanted Oxygen (SIMOX) process which uses an energetic oxygen implant and high-temperature anneal (K. Izumi et al., CMOS Devices Fabricated on Buried SiO 2 Layers Formed by Oxygen Implantation into Silicon, Electronics Letts. 14, 593, 1978).
- SIMOX Separation by Implanted Oxygen
- This method of creating an oxide/silicon interface is known to generate a higher number of defects at the interface than would a conventional thermal oxidation, (S. Visitserngtrakul et al., Formation of Multiply Faulted Defects in Oxygen Implanted Silicon-on-Insulator Material, J. Appl. Phys. 69, 1784 1991).
- SIMOX Separation by Implanted Oxygen
- An object of the present invention is to provide a Gate All Around (GAA) MOSFET.
- GAA Gate All Around
- Another object of the present invention is to provide a GAA MOSFET having at least a top and bottom gate both for controlling conduction through a channel disposed therebetween.
- Another object of the present invention is to form a GAA MOSFET using Silicon On Insulator (SOI) wafer.
- SOI Silicon On Insulator
- Yet another object of the present invention is to form a MOSFET having at least a top and bottom gate both for controlling conduction through a channel disposed therebetween using an SOI wafer having one of said gate insulated therein.
- Yet a further object of the invention is to form a MOSFET having at least a top and bottom gate both for controlling conduction through a channel disposed therebetween using an SOI wafer having the bottom gate of said gate insulated therein flip-bonded onto a bulk silicon wafer for burying the bottom gate within a merged bonded wafer consisting of the SOI wafer and bulk silicon wafer.
- Still another object of the present invention is to provide a merged bonded wafer including a bulk silicon wafer and a flip bonded SOI wafer having at least one buried electrode.
- the present invention takes advantage of SOI wafers, bulk silicon wafers and conventional processing techniques in new methods to form a novel SOI GAA MOSFET structure.
- the method for forming a flip-bonded SOI GAAMOSFET described herein employs conventional MOS processing steps in combination with well-established SOI techniques.
- a bottom gate dielectric layer, a bottom gate electrode and a bottom gate insulator on an SOI wafer which is then flip bonded onto a bulk silicon wafer having a bulk silicon insulator layer, the bottom gate electrode is thus buried in a merged wafer comprising the processed flip-bonded SOI wafer and bulk silicon wafer.
- One novel aspect of the present invention is the formation of the bottom gate of the GAA MOSFET device on an SOI wafer before the bottom gate dielectric field oxide layer is formed.
- This allows a conventional, controllable, high-quality gate dielectric formation upon the bottom gate in a GAA MOSFET.
- the thickness of the integral insulator layer between the bottom gate and the bulk silicon substrate is determined independently by the thicknesses of the bulk silicon insulator layer and a bottom gate insulator layer.
- the present invention allows the bottom gate to be formed using conventional, reliable gate dielectric and polysilicon deposition techniques.
- the present invention enables the GAA MOSFET device to be manufactured using only established process techniques that have been used in the past to construct bulk, SIMOX, or BESOI MOSFETs.
- the present invention has the additional advantage of allowing an arbitrarily thick oxide buried insulating layer between the polysilicon bottom gate and the bulk silicon substrate, thereby minimizing the parasitic capacitance and ensuring reliable isolation between the bottom gate and the bulk silicon substrate.
- the present invention forms the bottom gate dielectric, bottom gate electrode, and the bottom gate insulator layer of the MOSFET on an SOI wafer before flipping the SOI wafer upside-down and bonding it to a bulk silicon wafer using conventional bond-and-etch-back SOI (BESOI) techniques.
- BESOI bond-and-etch-back SOI
- the bulk insulator layer formed on bulk silicon wafer and the bottom gate insulator layer formed over the polysilicon bottom gate electrode of SOI wafer are merged together as a thick oxide buried insulating layer of the merged wafers.
- the SOI substrate and SOI buried insulator layer are then stripped from SOI wafer to expose the SOI semiconductor layer.
- the remaining MOSFETs structures are formed as a mesa superstructure on the merged wafer by conventional mesa etch and polysilicon gate processes.
- the exposed SOI semiconductor layer is etched and processed to define the drain, source and channel conducting regions upon which is then deposited a top gate dielectric.
- a patterned conductive polycrystalline silicon layer is deposited, defined, and etched to become the top gate electrode on mesa superstructure of the merged wafer.
- the top gate electrode of the MOSFET and metal connections to the source, drain, and top and bottom gates are then formed using conventional MOS processing techniques.
- Any SOI process may be used to form the SOI wafer.
- the present invention takes advantage of the buried oxide insulator layer of the SOI wafer as an etch-stop for the removal of the SOI substrate and SOI buried oxide insulator layer of the SOI wafer after the flip-bonding process to expose the SOI semiconductor layer. Bonding of SOI wafers may apply known SIMOX wafer bonding processes and allows conventional BESOI processing to define the thin active silicon layer. Conventional BESOI processes have traditionally used a doped silicon layer as the silicon etch stop which makes the uniformity of the silicon layer thickness difficult to control and restricts the silicon film to thicknesses greater than three microns.
- the SOI wafer bonding and oxide insulator layer etch stop technique allows for a very thin, less than one-tenth micron, silicon layer to be formed, which, when combined with bottom gate formation described in this invention, enables the SOI GAA MOSFET to operate in its fully-depleted mode, thereby allowing maximum current drive at the top and bottom surfaces and body of the channel of the MOSFET.
- FIG. 1 is a top view of a flip-bonded SOI GAA MOSFET.
- FIG. 2 is a cross-sectional view of the flip-bonded SOI GAA MOSFET as defined by a A--A' plane shown in FIG. 1.
- FIG. 3 is a cross-sectional view of the flip-bonded SOI GAA MOSFET as defined by a B--B' plane shown in FIG. 1.
- FIG. 4a is a cross-sectional view of a processed SOI wafer formed to include a superstructure having a buried gate.
- FIG. 4b is a cross-sectional view of a bulk silicon wafer including a bulk insulation layer and a bulk substrate layer.
- FIG. 4c is a cross-sectional view of a flip-bonded merged wafer including the processed SOI wafer flipped and bonded onto the bulk silicon wafer.
- FIG. 1 a top view is shown of Gate-All-Around (GAA) MOSFET having a top gate conductor 10, a bottom gate conductor 12, a drain conductor 14 and a source conductor 16.
- the conductors 10, 12, 14 and 16 are used to connect the GAA MOSFET to external circuits.
- the MOSFET further includes a top gate electrode 18 and bottom gate electrode 20 respectively connected to conductors 10 and 12.
- the active regions of the GAA MOSFET include a drain region 22, a channel region 24 and a source region 26.
- the drain region 22 and the source region 26 are connected to conductors 14 and 16, respectively.
- the active regions 22, 24 and 26 are integrally formed together as shown with the channel region being defined as that portion 24 generally disposed directly between the bottom gate electrode 20 and the top gate electrode 18.
- FIGS. 2 and 3 show side sectional views of the GAA MOSFET shown in FIG. 1 which also depicts conductors 10, 12, 14 and 16, gate electrodes 18 and 20, and regions 22, 24 and 26.
- the GAA MOSFET is generally disposed on a substrate 28 with a thick oxide insulating layer which, in the preferred form of the invention, includes insulator layers 30 and 32.
- the bottom gate electrode is separate from the regions 22, 24 and 26 by a gate dielectric 34 which is also an insulating layer.
- the bottom gate electrode is encapsulated within insulating materials, and preferably oxide insulators of layers 30, 32 and 34, excepting for the electrical contact to the bottom gate conductor 12.
- the insulating layers 30 and 32 provide insulation of the GAA MOSFET from the substrate 28 without the need of lateral isolation wells, not shown, which may otherwise be used to electrically isolate the GAA MOSFET from surrounding circuits.
- the regions 20, 22 and 24 are likewise separated from the top gate electrode 18 by a top gate dielectric 36 preferably and generally formed in a mesa processing configuration as shown.
- the GAA MOSFET lastly includes a top gate insulating layer 38 which is disposed over the entire GAA MOSFET save the etch windows shown by the penetration of the conductors 10, 12, 14 and 16 to the top gate 18, bottom gate 20, drain region 22 and source region 26, respectively.
- the bottom gate conductor 12 penetrates the bottom gate dielectric 34 to connect to the bottom gate electrode 20.
- both the drain conductor 14 and the source conductor 16 penetrate the top dielectric 36 to respectively connect to the drain region 22 and source region 26.
- the top gate conductor 10 only penetrates the top gate insulator layer 38 to connect to the top gate 18.
- the hereinabove GAAMOSFET has advantages in structure.
- the GAAMOSFET has two separated gate electrodes 18 and 20 which may be controlled separately by separately electrically connecting and controlling gate conductors 10 and 12, or controlled commonly by connecting together the gate conductors 10 and 12, for flexible electronic use of the MOSFET.
- the GAA MOSFET is substantially a gate all around device having gate electrodes substantially surrounding the channel region 24 on the top, sides and bottom of the channel region.
- the GAA MOSFET device is not a true GAA device by virtue of the bottom gate dielectric 34 separating the top and bottom gate electrodes 18 and 20, as shown.
- the GAA MOSFET device is effectively and essentially a GAA MOSFET as the bottom gate electrode 20 and top gate electrode 18 both are used to create surface conduction through the channel 24 between the source 26 and drain 22 along the top, bottom, and side surfaces of the channel 24 to enable the device to be operated with minimum loss of effect due to the separation of the gate electrodes 20 and 18 by the bottom gate dielectric 34 as shown.
- the GAA MOSFET device could be made to be a true GAA device, but that would necessarily require a common connection between the top and bottom gate electrode 18 and 20, and is thus not preferred so as to save the independent control of the top and bottom gate electrodes.
- top gate electrode 18 Before defining the top gate electrode 18, windows, not shown, in the bottom dielectric 34 could be made so that top gate electrode 18 connects directly to the bottom gate electrode 20 through such windows to create a true GAAMOSFET device, which is not preferred as effectively unnecessary. In such a true GAAMOSFET a thin native oxide layer would exist on the bottom gate electrode 34 when exposed to oxygen as in air preventing ideal connectivity between polysilicon gate electrodes 18 and 20 as shown.
- the GAA MOSFET is substantially completely electrically isolated from surrounding circuits and from the substrate 28 by virtue of the insulator layers 30, 32, 34, 36 and 38. Moreover, the GAA MOSFET has reduced parasitic capacitance to the substrate 28 by virtue of a relatively thick oxide insulator consisting of insulating layers 30 and 32. Further, the GAA MOSFET device may be fabricated using conventional MOSFET and integrated circuit manufacturing processes in a new and novel way as hereinbelow preferably set forth.
- the GAA MOSFET is preferably fabricated using a series of process steps, starting with silicon-on-insulator wafer 40 having an SOI semiconductor layer 42, an SOI buried insulator layer 44 and an SOI substrate 46.
- the drain, source and channel regions 22, 26 and 24, repectively, are formed in the silicon semiconductor layer 42 having a predetermined conductivity typically from a predetermined dopant concentration.
- the layer 42 may be processed, using for example, ion implantation, to define the source and drain regions 26 and 22, respectively, to thereby define the channel region 24. This process step is preferably done at a later stage in the process, and therefore the layer 42 preferably remains as 28 a layer of uniform semiconductor material.
- the layer is preferably made of silicon, but any suitable semiconductor may be used on the insulating layer 44.
- the bottom gate dielectric 34 is formed over semiconductor layer 42 preferably including the source, channel and drain regions 26, 24 and 22, respectively, but particularly the channel region 24.
- the top and bottom gate electrodes 18 and 20 are made from conductive material, preferably a polycrystalline silicon (polysilicon).
- the bottom gate electrode 20 is formed on the bottom gate dielectric 34 over the channel region 24.
- the bottom gate insulator layer 32 is formed over the bottom gate electrode 20 as well as the bottom gate dielectric 34.
- the exposed insulator layer 32 is planarized using convention planarized processing methods to form a substantially exposed flat surface resulting in a processed SOI wafer 48 including layers 32, 34, 42, 44 and 46 and the bottom gate electrode 20.
- the processed SOI wafer 48 may be further processed at this time, but preferably not, to remove the SOI substrate 46 and SOI insulator layer 44 from the processed SOI wafer 48.
- a bulk silicon wafer 50 consists initially of only a substrate 28.
- the bulk silicon insulator layer 30 is formed on the bulk silicon substrate 28.
- the processed SOI wafer 48 is flipped and its exposed planarized surface of the bottom gate insulator layer 32 is bonded to the bulk silicon insulator layer 30 of the bulk silicon wafer using well known prior art bonding techniques, to form a merged wafer 52 as shown in FIG. 4C comprising the bulk silicon wafer 50 and the processed SOI wafer 48.
- the merged wafer 52 essentially provides a buried conducting material, preferably a polysilicon material, encapsulated in an insulating material, preferably an oxide insulating material.
- the buried conductor material is preferably a buried bottom gate electrode 20, but which may be formed as another circuit structure, such as a buried conductor, not shown, for connecting together subsurface circuits, such as other surface MOSFETs, also not shown.
- this embodiment of the invention enables the creation of patterned conducting layers by repeated processes creating for example buried etch runs in a semiconductor wafer similar to prior art hybrid electronics or printed circuit boards having multiple etch run layers for routing to integrated circuit chips or integrated circuit packages, respectively.
- the SOI substrate 46 and the SOI insulator 44 of the processed SOI wafer 48 are now preferably removed, exposing the silicon semiconductor layer 42.
- the SOI insulator 44 functions as an etch stop during removal of the SOI substrate 46.
- the exposed semiconductor layer 42 of the merged wafer 52 becomes a top surface for further processing similar to conventional and well known MOSFET mesa processes. Processing is now preferably performed to define the transistor mesa by etching the semiconductor layer 42 as an initial mesa formation step.
- the top gate insulator 36 is then formed, for example, by partial thermal oxidation of the semiconductor layer 42.
- the top gate electrode 18 is then formed, for example, by polysilicon deposition and etching.
- the drain and source regions 22 and 26, with enhanced conductivity, are then defined preferably by ion implantation at a predetermined concentration.
- the mesa formation of the semiconductor layer 42 may be formed by a local oxidation of silicon process (LOCOS).
- LOCS local oxidation of silicon process
- the top gate dielectric 36 is formed over the mesa source, channel and drain, 22, 24 and 26, and formed over both the top and vertical side walls of the regions 22, 24 and 26 as shown.
- the top gate electrode 18, preferably of polysilicon, is formed over the top gate dielectric 36, including the top and vertical side walls of the top gate dielectric 36, as shown.
- the top gate electrode 18 extends over the top and side walls of the channel region 24 as does the top gate dielectric, and in combination with bottom gate 20, tends to substantially surround the channel 24 for enhanced operation of the GAA MOSFET.
- the top gate insulator 38 preferably of oxide is formed over the top gate electrode 18 as well as exposed portions of the top and bottom gate dielectrics 34 and 36.
- the conductor 10 connected to the top gate electrode 18, the conductor 12 connected to the bottom gate electrode 20, the conductor 14 connected to the drain region 22, and the conductor 16 connected to the source region 26 are formed and connected through respective insulator contact windows as represented by rectangular criss-crosses in FIG. 1.
Abstract
Description
Claims (6)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/310,915 US5497019A (en) | 1994-09-22 | 1994-09-22 | Silicon-on-insulator gate-all-around MOSFET devices and fabrication methods |
US08/422,196 US5580802A (en) | 1994-09-22 | 1995-04-13 | Silicon-on-insulator gate-all-around mosfet fabrication methods |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/310,915 US5497019A (en) | 1994-09-22 | 1994-09-22 | Silicon-on-insulator gate-all-around MOSFET devices and fabrication methods |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/422,196 Division US5580802A (en) | 1994-09-22 | 1995-04-13 | Silicon-on-insulator gate-all-around mosfet fabrication methods |
Publications (1)
Publication Number | Publication Date |
---|---|
US5497019A true US5497019A (en) | 1996-03-05 |
Family
ID=23204613
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/310,915 Expired - Fee Related US5497019A (en) | 1994-09-22 | 1994-09-22 | Silicon-on-insulator gate-all-around MOSFET devices and fabrication methods |
US08/422,196 Expired - Lifetime US5580802A (en) | 1994-09-22 | 1995-04-13 | Silicon-on-insulator gate-all-around mosfet fabrication methods |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/422,196 Expired - Lifetime US5580802A (en) | 1994-09-22 | 1995-04-13 | Silicon-on-insulator gate-all-around mosfet fabrication methods |
Country Status (1)
Country | Link |
---|---|
US (2) | US5497019A (en) |
Cited By (40)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5747847A (en) * | 1996-03-18 | 1998-05-05 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device, method for manufacturing the same, and logical circuit |
US5804848A (en) * | 1995-01-20 | 1998-09-08 | Sony Corporation | Field effect transistor having multiple gate electrodes surrounding the channel region |
US5818070A (en) * | 1994-07-07 | 1998-10-06 | Semiconductor Energy Laboratory Company, Ltd. | Electro-optical device incorporating a peripheral dual gate electrode TFT driver circuit |
US5889302A (en) * | 1997-04-21 | 1999-03-30 | Advanced Micro Devices, Inc. | Multilayer floating gate field effect transistor structure for use in integrated circuit devices |
US5910684A (en) * | 1995-11-03 | 1999-06-08 | Micron Technology, Inc. | Integrated circuitry |
US5936280A (en) * | 1997-04-21 | 1999-08-10 | Advanced Micro Devices, Inc. | Multilayer quadruple gate field effect transistor structure for use in integrated circuit devices |
US6031269A (en) * | 1997-04-18 | 2000-02-29 | Advanced Micro Devices, Inc. | Quadruple gate field effect transistor structure for use in integrated circuit devices |
US6091150A (en) * | 1996-09-03 | 2000-07-18 | Micron Technology, Inc. | Integrated circuitry comprising electrically insulative material over interconnect line tops, sidewalls and bottoms |
US6320228B1 (en) | 2000-01-14 | 2001-11-20 | Advanced Micro Devices, Inc. | Multiple active layer integrated circuit and a method of making such a circuit |
US6346446B1 (en) | 1998-06-01 | 2002-02-12 | Massachusetts Institute Of Technology | Methods of forming features of integrated circuits using modified buried layers |
US6429484B1 (en) | 2000-08-07 | 2002-08-06 | Advanced Micro Devices, Inc. | Multiple active layer structure and a method of making such a structure |
US20020175328A1 (en) * | 2001-03-27 | 2002-11-28 | Semiconductor Energy Laboratory Co. Ltd. | Semiconductor device and method for manufacturing the same |
US6501097B1 (en) | 1994-04-29 | 2002-12-31 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device |
US6563131B1 (en) | 2000-06-02 | 2003-05-13 | International Business Machines Corporation | Method and structure of a dual/wrap-around gate field effect transistor |
US20030164500A1 (en) * | 2001-03-27 | 2003-09-04 | Akira Tsunoda | Semiconductor device and method for manufacturing the same |
US6642115B1 (en) * | 2000-05-15 | 2003-11-04 | International Business Machines Corporation | Double-gate FET with planarized surfaces and self-aligned silicides |
US6664582B2 (en) | 2002-04-12 | 2003-12-16 | International Business Machines Corporation | Fin memory cell and method of fabrication |
US20040016968A1 (en) * | 2002-04-08 | 2004-01-29 | Stmicroelectronics S.A. | Surround-gate semiconductor device encapsulated in an insulating medium |
US6686630B2 (en) * | 2001-02-07 | 2004-02-03 | International Business Machines Corporation | Damascene double-gate MOSFET structure and its fabrication method |
US6709935B1 (en) | 2001-03-26 | 2004-03-23 | Advanced Micro Devices, Inc. | Method of locally forming a silicon/geranium channel layer |
US20040119100A1 (en) * | 2002-12-19 | 2004-06-24 | International Business Machines Corporation | Dense dual-plane devices |
US20050003592A1 (en) * | 2003-06-18 | 2005-01-06 | Jones A. Brooke | All-around MOSFET gate and methods of manufacture thereof |
US20050184348A1 (en) * | 2004-02-19 | 2005-08-25 | Jae-Man Youn | Semiconductor device gate structure and method of forming the same |
US20050263795A1 (en) * | 2004-05-25 | 2005-12-01 | Jeong-Dong Choi | Semiconductor device having a channel layer and method of manufacturing the same |
US20050281069A1 (en) * | 2001-08-28 | 2005-12-22 | Leonard Forbes | Computer systems, processes for turning a SRAM cell off, and processes for writing a SRAM cell |
US20060017104A1 (en) * | 2004-07-22 | 2006-01-26 | Jae-Man Yoon | Semiconductor device having a channel pattern and method of manufacturing the same |
US20060022715A1 (en) * | 2004-07-30 | 2006-02-02 | Atsushi Kawasumi | Variable timing circuit |
US7312125B1 (en) | 2004-02-05 | 2007-12-25 | Advanced Micro Devices, Inc. | Fully depleted strained semiconductor on insulator transistor and method of making the same |
US20080203476A1 (en) * | 2004-12-28 | 2008-08-28 | Koninklijke Philips Electronics N.V. | Semiconductor Device Having Strip-Shaped Channel And Method For Manufacturing Such A Device |
US20090173984A1 (en) * | 2008-01-08 | 2009-07-09 | Qimonda Ag | Integrated circuit and method of manufacturing an integrated circuit |
DE102008005518A1 (en) * | 2008-01-22 | 2009-07-30 | Qimonda Ag | Integrated circuit for use with floating body transistor, has two source or drain regions and floating body region, arranged between two source or drain regions, and back gate electrode is provided |
US8399922B2 (en) * | 2004-09-29 | 2013-03-19 | Intel Corporation | Independently accessed double-gate and tri-gate transistors |
US8803242B2 (en) | 2011-09-19 | 2014-08-12 | Eta Semiconductor Inc. | High mobility enhancement mode FET |
US8900935B2 (en) | 2011-01-25 | 2014-12-02 | International Business Machines Corporation | Deposition on a nanowire using atomic layer deposition |
JP2015005730A (en) * | 2013-05-18 | 2015-01-08 | 株式会社半導体エネルギー研究所 | Semiconductor device |
US9214538B2 (en) | 2011-05-16 | 2015-12-15 | Eta Semiconductor Inc. | High performance multigate transistor |
US9502312B2 (en) | 2010-11-29 | 2016-11-22 | Qualcomm Incorporated | Area efficient field effect device |
EP3154093A1 (en) * | 2015-10-10 | 2017-04-12 | Semiconductor Manufacturing International Corporation (Beijing) | Transistor and method for forming the same |
US9966435B2 (en) | 2015-12-09 | 2018-05-08 | Qualcomm Incorporated | Body tied intrinsic FET |
US10170304B1 (en) | 2017-10-25 | 2019-01-01 | Globalfoundries Inc. | Self-aligned nanotube structures |
Families Citing this family (45)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3254007B2 (en) * | 1992-06-09 | 2002-02-04 | 株式会社半導体エネルギー研究所 | Thin film semiconductor device and method for manufacturing the same |
US6004865A (en) * | 1993-09-06 | 1999-12-21 | Hitachi, Ltd. | Method of fabricating multi-layered structure having single crystalline semiconductor film formed on insulator |
KR100205442B1 (en) * | 1995-12-26 | 1999-07-01 | 구본준 | Thin film transistor and method of fabricating the same |
JP3535307B2 (en) * | 1996-03-15 | 2004-06-07 | 株式会社半導体エネルギー研究所 | Semiconductor device |
US5683918A (en) * | 1996-04-01 | 1997-11-04 | Motorola, Inc. | Method of making semiconductor-on-insulator device with closed-gate electrode |
US5661051A (en) * | 1996-10-09 | 1997-08-26 | National Science Council | Method for fabricating a polysilicon transistor having a buried-gate structure |
US6207530B1 (en) * | 1998-06-19 | 2001-03-27 | International Business Machines Corporation | Dual gate FET and process |
JP4076648B2 (en) | 1998-12-18 | 2008-04-16 | 株式会社半導体エネルギー研究所 | Semiconductor device |
JP4008133B2 (en) * | 1998-12-25 | 2007-11-14 | 株式会社半導体エネルギー研究所 | Semiconductor device |
JP4202502B2 (en) | 1998-12-28 | 2008-12-24 | 株式会社半導体エネルギー研究所 | Semiconductor device |
US8158980B2 (en) | 2001-04-19 | 2012-04-17 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having a pixel matrix circuit that includes a pixel TFT and a storage capacitor |
US6259135B1 (en) | 1999-09-24 | 2001-07-10 | International Business Machines Corporation | MOS transistors structure for reducing the size of pitch limited circuits |
US6483156B1 (en) | 2000-03-16 | 2002-11-19 | International Business Machines Corporation | Double planar gated SOI MOSFET structure |
US6512269B1 (en) | 2000-09-07 | 2003-01-28 | International Business Machines Corporation | High-voltage high-speed SOI MOSFET |
EP1244142A1 (en) * | 2001-03-23 | 2002-09-25 | Universite Catholique De Louvain | Fabrication method of SOI semiconductor devices |
US6906344B2 (en) * | 2001-05-24 | 2005-06-14 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor with plural channels and corresponding plural overlapping electrodes |
DE10223709B4 (en) * | 2002-05-28 | 2009-06-10 | Qimonda Ag | Method for producing a double-gate transistor |
JP4679146B2 (en) * | 2002-08-07 | 2011-04-27 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Field effect transistor |
FR2845201B1 (en) * | 2002-09-27 | 2005-08-05 | St Microelectronics Sa | METHOD FOR FORMATION OF PORTIONS OF A MATERIAL COMPOUND WITHIN A CAVITY AND ELECTRIC CIRCUIT INCORPORATING PORTIONS OF COMPOUND MATERIAL OBTAINED THEREBY |
DE102005026228B4 (en) * | 2004-06-08 | 2010-04-15 | Samsung Electronics Co., Ltd., Suwon | GAA type transistor and method of making the same |
US20070262377A1 (en) * | 2004-11-10 | 2007-11-15 | Gil Asa | Transistor Structure and Method of Manufacturing Thereof |
TW200633154A (en) * | 2005-01-26 | 2006-09-16 | Harvatek Corp | Wafer-level electro-optical semiconductor fabrication mechanism and method thereof |
US7250347B2 (en) * | 2005-01-28 | 2007-07-31 | International Business Machines Corporation | Double-gate FETs (Field Effect Transistors) |
US7709313B2 (en) * | 2005-07-19 | 2010-05-04 | International Business Machines Corporation | High performance capacitors in planar back gates CMOS |
US7314794B2 (en) * | 2005-08-08 | 2008-01-01 | International Business Machines Corporation | Low-cost high-performance planar back-gate CMOS |
KR100630764B1 (en) | 2005-08-30 | 2006-10-04 | 삼성전자주식회사 | Gate all around semiconductor and method of manufacturing the same |
KR100711000B1 (en) * | 2005-11-28 | 2007-04-24 | 동부일렉트로닉스 주식회사 | Mos transistor equipped with double gate and the manufacturing method thereof |
TWI336945B (en) * | 2006-06-15 | 2011-02-01 | Au Optronics Corp | Dual-gate transistor and pixel structure using the same |
US7868374B2 (en) * | 2008-02-21 | 2011-01-11 | International Business Machines Corporation | Semitubular metal-oxide-semiconductor field effect transistor |
US9496227B2 (en) | 2009-07-15 | 2016-11-15 | Qualcomm Incorporated | Semiconductor-on-insulator with back side support layer |
US8912646B2 (en) | 2009-07-15 | 2014-12-16 | Silanna Semiconductor U.S.A., Inc. | Integrated circuit assembly and method of making |
US9466719B2 (en) | 2009-07-15 | 2016-10-11 | Qualcomm Incorporated | Semiconductor-on-insulator with back side strain topology |
TWI619235B (en) | 2009-07-15 | 2018-03-21 | 高通公司 | Semiconductor-on-insulator with back side heat dissipation |
US9390974B2 (en) | 2012-12-21 | 2016-07-12 | Qualcomm Incorporated | Back-to-back stacked integrated circuit assembly and method of making |
US9076873B2 (en) | 2011-01-07 | 2015-07-07 | International Business Machines Corporation | Graphene devices with local dual gates |
US9466536B2 (en) | 2013-03-27 | 2016-10-11 | Qualcomm Incorporated | Semiconductor-on-insulator integrated circuit with back side gate |
US8748245B1 (en) | 2013-03-27 | 2014-06-10 | Io Semiconductor, Inc. | Semiconductor-on-insulator integrated circuit with interconnect below the insulator |
US9478507B2 (en) | 2013-03-27 | 2016-10-25 | Qualcomm Incorporated | Integrated circuit assembly with faraday cage |
US9263520B2 (en) | 2013-10-10 | 2016-02-16 | Globalfoundries Inc. | Facilitating fabricating gate-all-around nanowire field-effect transistors |
US9515181B2 (en) * | 2014-08-06 | 2016-12-06 | Qualcomm Incorporated | Semiconductor device with self-aligned back side features |
US9576856B2 (en) | 2014-10-27 | 2017-02-21 | Globalfoundries Inc. | Fabrication of nanowire field effect transistor structures |
US9281379B1 (en) | 2014-11-19 | 2016-03-08 | International Business Machines Corporation | Gate-all-around fin device |
WO2017052557A1 (en) * | 2015-09-24 | 2017-03-30 | Intel Corporation | Techniques for soi device formation on a virtual substrate, and associated configurations |
US11103168B2 (en) * | 2016-08-08 | 2021-08-31 | New York University | Systems and methods for in vivo detection of electrophysiological and electrochemical signals |
US10103241B2 (en) | 2017-03-07 | 2018-10-16 | Nxp Usa, Inc. | Multigate transistor |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4980308A (en) * | 1987-01-30 | 1990-12-25 | Sony Corporation | Method of making a thin film transistor |
US5188973A (en) * | 1991-05-09 | 1993-02-23 | Nippon Telegraph & Telephone Corporation | Method of manufacturing SOI semiconductor element |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4771016A (en) * | 1987-04-24 | 1988-09-13 | Harris Corporation | Using a rapid thermal process for manufacturing a wafer bonded soi semiconductor |
US4902641A (en) * | 1987-07-31 | 1990-02-20 | Motorola, Inc. | Process for making an inverted silicon-on-insulator semiconductor device having a pedestal structure |
US5168078A (en) * | 1988-11-29 | 1992-12-01 | Mcnc | Method of making high density semiconductor structure |
US5034343A (en) * | 1990-03-08 | 1991-07-23 | Harris Corporation | Manufacturing ultra-thin wafer using a handle wafer |
US5468674A (en) * | 1994-06-08 | 1995-11-21 | The United States Of America As Represented By The Secretary Of The Navy | Method for forming low and high minority carrier lifetime layers in a single semiconductor structure |
-
1994
- 1994-09-22 US US08/310,915 patent/US5497019A/en not_active Expired - Fee Related
-
1995
- 1995-04-13 US US08/422,196 patent/US5580802A/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4980308A (en) * | 1987-01-30 | 1990-12-25 | Sony Corporation | Method of making a thin film transistor |
US5188973A (en) * | 1991-05-09 | 1993-02-23 | Nippon Telegraph & Telephone Corporation | Method of manufacturing SOI semiconductor element |
Non-Patent Citations (22)
Title |
---|
A Field Assisted Bonding Process for Silicon Dielectric Isolation Frye, R. C., Griffith, J. E., Wong, Y. H., J Electrochem. Soc. 133. * |
A Fully Depleted Lean Channel Transistor (DELTA) A Novel Vertical Ultra Thin SOI MOSFET Hisamoto, D., Kaga, T., Kawamoto, Y., Takeda, E. IEDM Tech Digest. * |
A Fully Depleted Lean-Channel Transistor (DELTA)--A Novel Vertical Ultra Thin SOI MOSFET Hisamoto, D., Kaga, T., Kawamoto, Y., Takeda, E.--IEDM Tech Digest. |
Bonding of Silicon Wafers for Silicon On Insulator Maszara, W. P., Goetz, G., Caviglia, A., McKitterick, J. B. J. Appl. Phys. 64. * |
Bonding of Silicon Wafers for Silicon-On-Insulator Maszara, W. P., Goetz, G., Caviglia, A., McKitterick, J. B. J. Appl. Phys. 64. |
C.M.O.S. Devices Fabricated on Buried SiO 2 Layers Formed by Oxygen Implantation Into Silicon Izumi, K., Doken, M., Ariyoshi, H., Electronics Letts. 14. * |
C.M.O.S. Devices Fabricated on Buried SiO2 Layers Formed by Oxygen Implantation Into Silicon Izumi, K., Doken, M., Ariyoshi, H., Electronics Letts. 14. |
Dual Gate Operation and Volume Inversion in n Channel SOI MOSFETs Venkatesan, S., Neudeck, G. W., Pierret, R. F., IEEE Electron Device Letts. 13. * |
Dual Gate Operation and Volume Inversion in n-Channel SOI MOSFETs Venkatesan, S., Neudeck, G. W., Pierret, R. F., IEEE Electron Device Letts. 13. |
Dual Gate SOI CMOS Technology by Local Overgrowth (LOG) Zingg, R. P., Hofflinger, B., Neudick, G. W., 1989 IEEE SOS/SOI Tech Conf. Proc., 1989. * |
Dual-Gate SOI CMOS Technology by Local Overgrowth (LOG) Zingg, R. P., Hofflinger, B., Neudick, G. W., 1989 IEEE SOS/SOI Tech Conf. Proc., 1989. |
Formation of Multiply Faulted Defects in Oxygen Implanted Silicon on Insulator Material Visitserngtrakul, S., Krause, S. J., J. Aool. Phys. 69. * |
Formation of Multiply Faulted Defects in Oxygen Implanted Silicon-on-Insulator Material Visitserngtrakul, S., Krause, S. J.,--J. Aool. Phys. 69. |
Modes of Operation and Radiation Sensitivity of Ultrathin SOI Transistors Mayer, D. C., IEEE Trans. Electron Devices. * |
Radiation Effects in Gate All Around Structures Lawrence, R. K., Colinge, J. P., Hughes, H. L., 1991 IEEE Int l SOI Conf. * |
Radiation Effects in Gate-All-Around Structures Lawrence, R. K., Colinge, J. P., Hughes, H. L., 1991 IEEE Int'l SOI Conf. |
Silicon On Insulator by Bonding and Etch Back Lasky, J. B., Stiffler, S. R., White, F. R., Abernathey, J. F. IEDM Tech. Digest, 1985. * |
Silicon On Insulator Gate All Around Device Colinge, J. P., Gao, M. H., Romano Rodriguez, A., Maes, H., Claeys, C. IEDM Tech Digest. * |
Silicon-On-Insulator by Bonding and Etch-Back Lasky, J. B., Stiffler, S. R., White, F. R., Abernathey, J. F. IEDM Tech. Digest, 1985. |
Silicon-On-Insulator Gate-All-Around Device Colinge, J. P., Gao, M. H., Romano-Rodriguez, A., Maes, H., Claeys, C. IEDM Tech Digest. |
VLSI SOI Fabrication by SIMOX Wafer Bonding (SWB) Tong, Q. Y., Gosele, U., 1992 IEEE Int l SOI Conf. Proc., 1992. * |
VLSI SOI Fabrication by SIMOX Wafer Bonding (SWB) Tong, Q. Y., Gosele, U., 1992 IEEE Int'l SOI Conf. Proc., 1992. |
Cited By (64)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6501097B1 (en) | 1994-04-29 | 2002-12-31 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device |
US7102164B2 (en) | 1994-04-29 | 2006-09-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having a conductive layer with a light shielding part |
US20060284221A1 (en) * | 1994-04-29 | 2006-12-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and electronic device |
US6800873B2 (en) | 1994-04-29 | 2004-10-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and electronic device |
US7423291B2 (en) | 1994-04-29 | 2008-09-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and electronic device |
US8319715B2 (en) | 1994-04-29 | 2012-11-27 | Semiconductor Energy Laboratory Co., Ltd. | Active matrix type liquid crystal display device |
US20030116766A1 (en) * | 1994-04-29 | 2003-06-26 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and electronic device |
US5818070A (en) * | 1994-07-07 | 1998-10-06 | Semiconductor Energy Laboratory Company, Ltd. | Electro-optical device incorporating a peripheral dual gate electrode TFT driver circuit |
US5804848A (en) * | 1995-01-20 | 1998-09-08 | Sony Corporation | Field effect transistor having multiple gate electrodes surrounding the channel region |
US5899710A (en) * | 1995-01-20 | 1999-05-04 | Sony Corporation | Method for forming field effect transistor having multiple gate electrodes surrounding the channel region |
US6066553A (en) * | 1995-11-03 | 2000-05-23 | Micron Technology, Inc. | Semiconductor processing method of forming electrically conductive interconnect lines and integrated circuitry |
US5910684A (en) * | 1995-11-03 | 1999-06-08 | Micron Technology, Inc. | Integrated circuitry |
US6432813B1 (en) | 1995-11-03 | 2002-08-13 | Micron Technology, Inc. | Semiconductor processing method of forming insulative material over conductive lines |
US5747847A (en) * | 1996-03-18 | 1998-05-05 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device, method for manufacturing the same, and logical circuit |
US6091150A (en) * | 1996-09-03 | 2000-07-18 | Micron Technology, Inc. | Integrated circuitry comprising electrically insulative material over interconnect line tops, sidewalls and bottoms |
US6031269A (en) * | 1997-04-18 | 2000-02-29 | Advanced Micro Devices, Inc. | Quadruple gate field effect transistor structure for use in integrated circuit devices |
US5936280A (en) * | 1997-04-21 | 1999-08-10 | Advanced Micro Devices, Inc. | Multilayer quadruple gate field effect transistor structure for use in integrated circuit devices |
US6294829B1 (en) | 1997-04-21 | 2001-09-25 | Advanced Micro Devices, Inc. | Multilayer quadruple gate field effect transistor structure for use in integrated circuit devices |
US5889302A (en) * | 1997-04-21 | 1999-03-30 | Advanced Micro Devices, Inc. | Multilayer floating gate field effect transistor structure for use in integrated circuit devices |
US6346446B1 (en) | 1998-06-01 | 2002-02-12 | Massachusetts Institute Of Technology | Methods of forming features of integrated circuits using modified buried layers |
US6320228B1 (en) | 2000-01-14 | 2001-11-20 | Advanced Micro Devices, Inc. | Multiple active layer integrated circuit and a method of making such a circuit |
US6642115B1 (en) * | 2000-05-15 | 2003-11-04 | International Business Machines Corporation | Double-gate FET with planarized surfaces and self-aligned silicides |
US20040023460A1 (en) * | 2000-05-15 | 2004-02-05 | Cohen Guy M. | Double-gate fet with planarized surfaces and self-aligned silicides |
US6967377B2 (en) | 2000-05-15 | 2005-11-22 | International Business Machines Corporation | Double-gate fet with planarized surfaces and self-aligned silicides |
US6563131B1 (en) | 2000-06-02 | 2003-05-13 | International Business Machines Corporation | Method and structure of a dual/wrap-around gate field effect transistor |
US6429484B1 (en) | 2000-08-07 | 2002-08-06 | Advanced Micro Devices, Inc. | Multiple active layer structure and a method of making such a structure |
US6686630B2 (en) * | 2001-02-07 | 2004-02-03 | International Business Machines Corporation | Damascene double-gate MOSFET structure and its fabrication method |
US6709935B1 (en) | 2001-03-26 | 2004-03-23 | Advanced Micro Devices, Inc. | Method of locally forming a silicon/geranium channel layer |
US7189997B2 (en) | 2001-03-27 | 2007-03-13 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
US6982194B2 (en) | 2001-03-27 | 2006-01-03 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
US20030164500A1 (en) * | 2001-03-27 | 2003-09-04 | Akira Tsunoda | Semiconductor device and method for manufacturing the same |
US20020175328A1 (en) * | 2001-03-27 | 2002-11-28 | Semiconductor Energy Laboratory Co. Ltd. | Semiconductor device and method for manufacturing the same |
US7164597B2 (en) * | 2001-08-28 | 2007-01-16 | Micron Technology, Inc. | Computer systems |
US20060193161A1 (en) * | 2001-08-28 | 2006-08-31 | Leonard Forbes | Processes for turning a SRAM cell off and processess for writing a SRAM cell |
US20050281069A1 (en) * | 2001-08-28 | 2005-12-22 | Leonard Forbes | Computer systems, processes for turning a SRAM cell off, and processes for writing a SRAM cell |
US6969878B2 (en) * | 2002-04-08 | 2005-11-29 | Stmicroelectronics S.A. | Surround-gate semiconductor device encapsulated in an insulating medium |
US20040016968A1 (en) * | 2002-04-08 | 2004-01-29 | Stmicroelectronics S.A. | Surround-gate semiconductor device encapsulated in an insulating medium |
US6664582B2 (en) | 2002-04-12 | 2003-12-16 | International Business Machines Corporation | Fin memory cell and method of fabrication |
US6794718B2 (en) | 2002-12-19 | 2004-09-21 | International Business Machines Corporation | High mobility crystalline planes in double-gate CMOS technology |
US20040119100A1 (en) * | 2002-12-19 | 2004-06-24 | International Business Machines Corporation | Dense dual-plane devices |
US20050003592A1 (en) * | 2003-06-18 | 2005-01-06 | Jones A. Brooke | All-around MOSFET gate and methods of manufacture thereof |
US7312125B1 (en) | 2004-02-05 | 2007-12-25 | Advanced Micro Devices, Inc. | Fully depleted strained semiconductor on insulator transistor and method of making the same |
DE102005006899B4 (en) * | 2004-02-19 | 2010-11-25 | Samsung Electronics Co., Ltd. | A semiconductor device having a gate structure, and methods for forming the gate structure and the semiconductor device |
US20050184348A1 (en) * | 2004-02-19 | 2005-08-25 | Jae-Man Youn | Semiconductor device gate structure and method of forming the same |
US20050263795A1 (en) * | 2004-05-25 | 2005-12-01 | Jeong-Dong Choi | Semiconductor device having a channel layer and method of manufacturing the same |
US20060017104A1 (en) * | 2004-07-22 | 2006-01-26 | Jae-Man Yoon | Semiconductor device having a channel pattern and method of manufacturing the same |
US7579648B2 (en) | 2004-07-22 | 2009-08-25 | Samsung Electronics Co., Ltd. | Semiconductor device having a channel pattern and method of manufacturing the same |
US7034577B2 (en) * | 2004-07-30 | 2006-04-25 | Kabushiki Kaisha Toshiba | Variable timing circuit |
US20060022715A1 (en) * | 2004-07-30 | 2006-02-02 | Atsushi Kawasumi | Variable timing circuit |
US8399922B2 (en) * | 2004-09-29 | 2013-03-19 | Intel Corporation | Independently accessed double-gate and tri-gate transistors |
US7691695B2 (en) * | 2004-12-28 | 2010-04-06 | Nxp B.V. | Semiconductor device having strip-shaped channel and method for manufacturing such a device |
US20080203476A1 (en) * | 2004-12-28 | 2008-08-28 | Koninklijke Philips Electronics N.V. | Semiconductor Device Having Strip-Shaped Channel And Method For Manufacturing Such A Device |
US20090173984A1 (en) * | 2008-01-08 | 2009-07-09 | Qimonda Ag | Integrated circuit and method of manufacturing an integrated circuit |
DE102008005518A1 (en) * | 2008-01-22 | 2009-07-30 | Qimonda Ag | Integrated circuit for use with floating body transistor, has two source or drain regions and floating body region, arranged between two source or drain regions, and back gate electrode is provided |
US9502312B2 (en) | 2010-11-29 | 2016-11-22 | Qualcomm Incorporated | Area efficient field effect device |
US9437677B2 (en) | 2011-01-25 | 2016-09-06 | Globalfoundries Inc. | Deposition on a nanowire using atomic layer deposition |
US8900935B2 (en) | 2011-01-25 | 2014-12-02 | International Business Machines Corporation | Deposition on a nanowire using atomic layer deposition |
US9214538B2 (en) | 2011-05-16 | 2015-12-15 | Eta Semiconductor Inc. | High performance multigate transistor |
US8803242B2 (en) | 2011-09-19 | 2014-08-12 | Eta Semiconductor Inc. | High mobility enhancement mode FET |
JP2015005730A (en) * | 2013-05-18 | 2015-01-08 | 株式会社半導体エネルギー研究所 | Semiconductor device |
EP3154093A1 (en) * | 2015-10-10 | 2017-04-12 | Semiconductor Manufacturing International Corporation (Beijing) | Transistor and method for forming the same |
US10199478B2 (en) | 2015-10-10 | 2019-02-05 | Semiconductor Manufacturing International (Shanghai) Corporation | Transistor and method for forming the same |
US9966435B2 (en) | 2015-12-09 | 2018-05-08 | Qualcomm Incorporated | Body tied intrinsic FET |
US10170304B1 (en) | 2017-10-25 | 2019-01-01 | Globalfoundries Inc. | Self-aligned nanotube structures |
Also Published As
Publication number | Publication date |
---|---|
US5580802A (en) | 1996-12-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5497019A (en) | Silicon-on-insulator gate-all-around MOSFET devices and fabrication methods | |
US5893745A (en) | Methods of forming semiconductor-on-insulator substrates | |
US7115950B2 (en) | Semiconductor device and method of manufacturing the same | |
US7109551B2 (en) | Semiconductor device | |
US6320228B1 (en) | Multiple active layer integrated circuit and a method of making such a circuit | |
US6462379B2 (en) | SOI semiconductor device and method for manufacturing the same | |
US5356827A (en) | Method of manufacturing semiconductor device | |
US5882981A (en) | Mesa isolation Refill Process for Silicon on Insulator Technology Using Flowage Oxides as the Refill Material | |
US6586802B2 (en) | Semiconductor device | |
EP0364393A2 (en) | Power semiconductor device | |
JPH1074921A (en) | Semiconductor device and manufacturing method thereof | |
US6229179B1 (en) | Intelligent power integrated circuit | |
WO2009090780A1 (en) | Semiconductor device, manufacturing method thereof and display device | |
JP3061020B2 (en) | Dielectric separated type semiconductor device | |
US8018003B2 (en) | Leakage power reduction in CMOS circuits | |
KR20070014969A (en) | Semiconductor device and manufacturing method thereof | |
JPH10256556A (en) | Semiconductor device and manufacture thereof | |
KR20070086005A (en) | Semiconductor device manufacturing method and semiconductor device | |
US7391109B2 (en) | Integrated circuit interconnect | |
US6175135B1 (en) | Trench contact structure of silicon on insulator | |
JP3127253B2 (en) | SOI semiconductor device and method of manufacturing the same | |
JP2936536B2 (en) | Semiconductor device and method of manufacturing the same | |
JP2839088B2 (en) | Semiconductor device | |
JPH05315437A (en) | Manufacture of semiconductor device | |
KR100649813B1 (en) | Manufacturing method of semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: AEROSPACE CORPORATION, THE, CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MAYER, DONALD C.;MACWILLIAMS, KENNETH P.;REEL/FRAME:007171/0098 Effective date: 19940831 |
|
AS | Assignment |
Owner name: AIR FORCE, UNITED STATES, VIRGINIA Free format text: CONFIRMATORY LICENSE;ASSIGNOR:AEROSPACE CORPORATION, THE;REEL/FRAME:008843/0840 Effective date: 19950808 |
|
REMI | Maintenance fee reminder mailed | ||
FPAY | Fee payment |
Year of fee payment: 4 |
|
SULP | Surcharge for late payment | ||
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20040305 |
|
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |