US5548542A - Half-band filter and method - Google Patents
Half-band filter and method Download PDFInfo
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- US5548542A US5548542A US08/304,433 US30443394A US5548542A US 5548542 A US5548542 A US 5548542A US 30443394 A US30443394 A US 30443394A US 5548542 A US5548542 A US 5548542A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H17/00—Networks using digital techniques
- H03H17/02—Frequency selective networks
- H03H17/06—Non-recursive filters
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/499—Denomination or exception handling, e.g. rounding or overflow
- G06F7/49905—Exception handling
- G06F7/4991—Overflow or underflow
- G06F7/49921—Saturation, i.e. clipping the result to a minimum or maximum value
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H19/00—Networks using time-varying elements, e.g. N-path filters
Definitions
- the present invention relates to electronic devices, and, more particularly, to semiconductor circuits and methods useful for filtering digital data streams.
- FDM frequency division multiplexing
- each source modulates its carrier frequency with its information signal and keeps within its allocated frequency band.
- Extraction of a desired information signal from a received broadband of simultaneous broadcasts may be performed by mixing down (down conversion by the selected carrier frequency) followed by lowpass filtering and demodulation as schematically illustrated by system 100 in FIG. 1.
- system 100 receives radio frequency signals (e.g., 100-200 MHz) at antenna 102, filters and mixes the signals down to intermediate frequencies (e.g., 1-10 MHz) with a wideband tuner 104, converts from analog to digital format with sampling analog-to-digital converter 106, extracts the selected frequency band (e.g., of width 5 KHz) with digital down converter 108 which performs the down conversion and filtering, and demodulates and reconstructs an analog information signal with demodulator/processor 110.
- radio frequency signals e.g., 100-200 MHz
- intermediate frequencies e.g., 1-10 MHz
- digital down converter 108 which performs the down conversion and filtering
- analog-to-digital converter 106 will sample at 20 MHz or more (at least the Nyquist rate), and digital down converter 108 will output a 5 KHz selected band at a sampling rate of 10 KHz. That is, digital down converter 108 may decrease the sampling rate due to the small bandwidth of its output without loss of information.
- the problems of construction of system 100 include realizing digital down converter 108 operating at a high sampling frequency while maintaining a low ripple sharp cutoff filter which has programmable down conversion frequency and programmable bandwidth.
- Known realizations of a down conversion function include the combination of a numerically controlled oscillator/modulator (NCOM) such as the HSP45106 manufactured by Harris Corporation together with two decimating lowpass digital filters (one for the in-phase and one for the quadrature outputs of the NCOM) such as the HSP43220 also manufactured by Harris Corporation.
- NCOM numerically controlled oscillator/modulator
- a lowpass decimating filter having a decimation rate R which may be factored as
- the filter may be realized as M cascaded independent lowpass decimation filters with the jth filter having decimation rate R j .
- This multistage approach may greatly reduce the number of computations required to perform the filtering. Indeed, the first stages in a multistage filter need not have narrow transition bands because the transition band of the last stage will essentially determine the overall transition band. Further, the early stages decimate the sampling rate so the latter stages operate at a much lower sampling frequency.
- Multistage filters may be effectively designed with stages of half-band filters.
- a lowpass digital FIR filter with optimal (equiripple) design and with symmetry about ⁇ /2 is called a half-band filter. That is, a half-band filter has a transfer function Fourier transform as shown in FIG. 2a with passband and stopband of equal width.
- Half-band filters have about one half of their filter coefficients equal to zero, so the filter computations include only about one half as many multiplications as a usual FIR filter.
- Half-band filters may appropriately be used only for decimation or interpolation of sampling rate by a factor of 2 and when aliasing to the final transition band is permitted. See FIG. 2b illustrating the aliasing of a decimation by 2 half-band filter.
- multistage filters with powers of 2 decimation or interpolation profitably employ cascaded half-band filters.
- Crochiere and Rabiner, Multirate Digital Signal Processing provides general information regarding signal processing using sampling rate changes.
- Hogenauer, An Economical Class of Digital Filters for Decimation and Interpolation, 29 IEEE Tr.Ac.Sp.Sig.Proc. 155 (1981) discloses decimation filters made of an integrator section followed by comb section operating a low sampling rate.
- the present invention provides a digital half-band filter with truncated multipliers and joint overflow and saturation compensating complementers.
- the truncated multipliers reduce the amount of hardware, and the complementers permit full dynamic range
- FIG. 1 illustrates a first application of a first preferred embodiment
- FIGS. 2a-b show half-band filter characteristics
- FIG. 3 is a functional block diagram of a first preferred embodiment half-band filter
- FIG. 4 illustrates four modes of operation of the present invention
- FIG. 5 illustrates an application of a preferred embodiment
- FIGS. 6(A)-(F) illustrate the sequence of the filtering operation in the downconversion and decimation by two mode
- FIGS. 7(A)-(G) illustrate the sequence of the filtering operation in the interpolate by two and upconversion mode
- FIG. 8 illustrates in block form FIR filter
- FIG. 9 shows a portion of a Wallace tree
- FIG. 10 shows the re-coded coefficients
- FIG. 11 lists the multiplicand locations within the Wallace trees
- FIG. 12 shows the sign extension words
- FIG. 13 illustrates the truncation decision
- FIG. 14 is a schematic for saturation detection within rounding.
- FIG. 3 is a functional block circuit diagram of a first preferred embodiment single chip digital half-band filter generally denoted by reference numeral 300, which includes the following blocks and items: 16-bit parallel port register 302 for input data samples Ain(15:0), 16-bit parallel port register 304 for input data samples Bin(15:0), multiplexer 306 for selecting between Ain and Bin input, 16-bit registers 312 and 314 for holding inputs, multipliers 322 and 324 for downconversion, local oscillator 326 for generating the sines and cosines for downconversion and upconversion, FIR filter odd arm 327 and even arm 328 for the lowpass half-band filtering, multipliers 332 and 334 for upconversion, adder 340 for combining signals in real output, rounders 342 and 344 for rounding to 16,14, 12, 11, 10, 9, or 8 bits, output registers 346 and 348, clock control 350, and control registers 352 for selecting mode of operation, rounding level, positive or negative frequency conversion, internal versus external multiplezing,
- Filter 300 is a 67-Tap, 20-bit, fixed coefficient filter that has four basic modes of operation illustrated in FIG. 4: (1) decimation by two filtering of a real input signal; (2) interpolation by two filtering of a real input signal; (3) quadrature downconversion of a real I.F. signal with decimation by two filtering of the resulting I and Q channels; and (4) interpolation by two filtering of a complex baseband signal and quadrature upconversion to produce a real output signal.
- the first two modes are useful for easing the requirements on the analog antialiasing filter used with a D/A converter or a A/D converter.
- FIG. 5 shows an application of filter 300 with the NCOM and two DDFs.
- the third mode listed above converts a real non-baseband signal to a baseband complex signal.
- the complex sample stream will only have to clock at half the input sample rate. This allows an A/D converter clock at twice the clock rate that the NCOM and DDF can run, i.e. a 25 MHz NCOM and DDF could be used with a 50 MHz A/D and process a signal bandwidth of almost 25 MHz. See FIG. 6.
- the fourth mode permits using the NCOM or HSP45216 (NCO16) as a modulator.
- This mode converts the quadrature baseband output of the NCOM or NCO16 to twice the clock rate and shifts the center frequency to FCLK/4. (FCLK is the output clock rate.) This allows a 25 MHz NCOM or NCO16 to drive a 50 MHz D/A and get almost 25 Mhz of tuning range. See FIG. 7.
- the filter response of half-band filter 300 has a shape factor, (Passband+Transition Band)/Passband of 1.24:1 with 90 dB alias free passband at 80% of Nyquist. There is less than 0.0005 dB of passband ripple. Due to characteristics of the half-band filter, half of the coefficients are zero (with the exception of the center tap). The center tap is effectively a delay and multiply of the input signal.
- a programmable, symmetric rounding stage (rounders 342-344) with saturation logic is provided to select from 8 to 16 bits of output, depending on the user's application.
- Outputs are available as Two's Complement or Offset Binary.
- Half-band filter 300 is a 67-Tap, 20-bit, fixed coefficient filter.
- the characteristics of a half-band filter are such that the coefficient set is symmetric with every even coefficient being zero, except for the center tap.
- the filter is divided into even and odd arms of the filter. Since the even coefficients are all zero with the exception of the center tap, the even filter arm is effectively a delay and multiply.
- the odd filter coefficients are in the top arm and the delay and multiply of the even center tap is in the lower arm of the filter.
- the four basic modes of operation are selected by the Mode 0-1 pins:
- 16-bit real data is input on Ain(15:0).
- the incoming data samples are divided into odd and even samples.
- the input samples come in at the fastest clock rate (CLK) and are multiplexed into odd and even samples at this rate.
- CLK clock rate
- the FIR section of the chip, and the output samples will run at the rate of CLK/2.
- the odd samples of data are multiplexed through the top arm of the filter, and the even samples are multiplexed through the lower arm of the filter.
- the two filter outputs are summed together to give one 16-bit output sample on Aout(15:0).
- the following illustration shows the proper decimation by two filter response using a standard, 67-tap filter with coefficients c 1 , c 2 , . . . c 67 so the center tap corresponds to c 34 .
- the filter forms the decimated-by-2 output stream Y 1 , Y 3 , Y 5 , . . .
- decimated-by-2 output stream is
- This mode will convert a real, non-baseband signal to a baseband complex signal, and decimate the resulting I and Q channels by two.
- the incoming data samples are divided into odd and even samples.
- the input samples come in at the fastest clock rate (CLK) and are multiplexed into odd and even samples at this rate.
- CLK clock rate
- Each of the odd and even samples pass through multipication by local oscillator (L.O.) 326 before going to the filter arms.
- L.O. local oscillator
- the FIR section of the chip, and the output samples will run at the rate of CLK/2.
- the odd samples of data go through the odd arm 327 of the filter, and the even samples go through the even arm 328 of the filter.
- the top and lower arms of the filter generate the resulting I and Q channels.
- the local oscillator multipliers 322-324 can be reduced to (1, -1) multipliers since the even data never goes to the odd coefficients and vice versa for the odd data. This results in passing data on the positive one multiply, and taking the two's complement of the data when multiplying by negative one.
- filter 300 to be implemented as true/complementer 322 providing alternating signs on the odd data which proceeds through the filter odd arm 327 and outputs as Aout(15:0), and true/complementer 324 providing alternating signs on the even data which proceeds through the filter even arm 328 (which is just delay and multiply by c 34 ) and outputs as Bout(15:0).
- Down conversion and shifting towards positive infinity is accomplished by convolving the data spectrum with an impulse located at positive frequency F S /4. This impulse is derived from a vector rotating clockwise about the unit circle. Downconversion and shifting towards negative infinity is accomplished by convolving the data spectrum with an impulse located at negative frequency -F S /4. This impulse is the result of a vector rotating counter clockwise about the unit circle.
- This mode converts the quadrature baseband output of the HSP45116 (NCOM) or HSP45106 (NCO16) to twice the clock rate and shifts the center frequency to FCLK/4 (FCLK is the output clock rate).
- FCLK is the output clock rate.
- complex data is input on Ain(15:0) and Bin(15:0) at the rate of CLK/2.
- the data samples effectively have zeroes placed between them before being multiplied by the filter coefficients.
- the output from the FIR section then pass through local oscillators which upconverts the signal to the frequency of FCLK/4.
- the FIR section of the chip and the local oscillators will run at CLK/2.
- Both of the local oscillators generate output samples which will be muxed out at Aout(15:0) at the rate of CLK.
- the following illustration shows the proper interpolation and upconversion using a standard, 67-tap filter with coefficients c 1 , c 2 , . . . c 67 so the center tap corresponds to c 34 .
- the interpolation 0's lead to the stream X 1 , 0, X 2 , 0, X 3 , . . . into the filter to form the interpolated-by-2 output stream Y 1 , Y 2 , Y 3 , . . .
- Filter 300 is implemented by the odd samples proceeding through the odd arm and then given alternating signs by true/complementer 332 and then output as Aout, and the even samples given alternating signs by true/complementer 334 and also output as Aout interleaved with the odd samples.
- the filter 300 expects to see the first (odd) piece of data on the following clock.
- SYNC# can be pulsed low at the beginning or it can run off a divided clock. If running off of a divided clock, it is restricted to clock/4 for modes which use internal mux and either oscillator, and clock/2 for all other modes.
- filter 300 will output data in Offset Binary Format. If FMT is low, the output data will be in Two's Complement Format.
- Aout(15:0) and Bout(15:0) are three-state control output busses controlled by OEA# and the OEB# (active low). There are also three other input pins to control the outputs. RNDO-2 input pins provide rounding control and allow the user to select the number of output bits from eight to sixteen.
- true/complementers 322, 324, 332, and 334 either pass data or invert and add 1 (two's complement).
- a tree structure is used to maximize speed.
- An alternative eliminates the incrementers and inserts the carry into the Wallace trees. There are several ways this could be done but they add complexity and do not give a clear hardware savings.
- bit positions 2 33 through 2 17 (17 bits) will be selected from the output of the adder.
- the bit positions refer to the Wallace tree bit positions. 2 35 was highest Wallace tree bit and 2 9 was lowest that was kept. Therefore, there were 27 bits of accuracy. Due to combinations of sums and carries in Wallace trees, filter 300 has a 23 bit full adder following the last Wallace tree. No rounding occurs in the bottom data path through the even arm when 16 bit outputs are chosen as there are only 16 bits of data.
- the filter 300 outputs can be in 2's complement or offset binary format as selected by FMT.
- FIG. 8 shows the functional architecture of the 67 tap FIR filter.
- the multiplications of filter coeffidents by data samples is carried out by a hardware which adds partial products in Wallace trees. These partial products are generated by hardwired, Booth Type recoding of the filter coefficients. This recoding was used to reduce the number of partial products required.
- Wallace tree summation first consider the multipication of a 16-bit multiplicand (the data sample) by a 20-bit multiplier (the filter coefficient). Written out, this product is seen to be the sum of easily-generated partial products.
- each of the 20 partial products may be generated by merely shifting the multiplicand for a corresponding 1 in the multiplier and by putting in 0s for a corresponding 0 in the multiplier. That is, the multiplicand feeding a multiplexer array controlled by the multiplier can provide the shifting and zeroing to form the partial products. If the numbers are in two's complement format, then sign extension bits would be inserted to extend the leading 1's in negative partial products out to the sign bit position. The summing of the 20 partial products consumes the bulk of the multiplication time.
- the summing of the partial products may be accelerated in two ways while keeping the hardware minimized: the summing may be done in a Wallace tree plus final adder (see FIG. 9) and the multiplier may be recoded to reduce the number of partial products by use of a Booth-type algorithm.
- FIR odd arm 327 shown in FIG. 8 has both Wallace trees (the 12 rectangles with a ⁇ ) and recoding of the multipliers (filter coefficients).
- the data samples are clocked in at the righthand portion of FIG. 8, and the hardwired recoded coefficients appear as the boxes with Xs with the corresponding coefficient noted as C1, . . . C17.
- the 67 coefficients split into 34 odd coefficients and 33 even coefficients.
- the even coefficients are all zero except the center tap, c 34 , which is equal to 2 18 and does not need a multiplier except for a shift by 18.
- the 34 odd coefficients are symmetric, so there are only 17 independent coefficients, and these are the C1, . . . C17. Note both the top and bottom rows of coefficients to make up the total of 34.
- a Wallace tree consists of an array of full adders which have three inputs (the two bits being added plus the carry in from the sum of lower order bits) and two outputs (the sum bit plus the carry out to higher order bits).
- each layer of a Wallace tree roughly has 2/3 the number of terms of the previous layer.
- FIG. 9 shows a portion of a Wallace tree for adding nine numbers called A, B, C, . . . H, and I with a subscript indicating the bit order.
- the rectangles indicate full adders and the broken vertical lines group bits of the same order with the least significant bits on the right. Note that every carry out goes into the adjacent grouping to the left.
- FIG. 9 after four levels the nine numbers have been added to form at most one sum bit and one carry bit in each bit position.
- the regularity of the tree is apparent in the lefthand portion of FIG. 9.
- the output of the final Wallace tree feeds a final adder as indicated by the output lines at the righthand edge of FIG. 8.
- the even data is operated on only by the center coefficient c 34 . Because the center coefficient equals a power of two (2 18 ) there is no need for an actual multiplier. The data is delayed and the bit weighting changed. The final value for the number of pipeline delays depends on the delays in the odd FIR filter arm and the front end of filter 300.
- the odd data enters odd arm 327 of the FIR filter which has 34 taps. At each tap the data is recoded into partial products which feed the Wallace trees. Where possible, the pipelines have been moved to minimize hardware. By moving a pipeline from the bottom to the top data path, the need for registering the sum and carrys is eliminated, a savings of almost 48 flops each time this is done. This was only done in cases where the resulting Wallace tree would be 6 levels or less.
- the recoding of the 34 coefficients of odd arm 327 proceeded by a two step process: first a set of coefficients were derived by standard methods for a 67-tap half-band filter with a prescribed width and tolerance for the passband and stopband.
- FIG. 10 shows the resulting set of coefficients together with their recodings (1 and -1 beneath each grouping of 1s). The total number of partial products reduces to 139 for all 67 taps.
- a sign extension word was calculated for each different set of coefficients coming into each Wallace tree; see FIG. 11.
- the letters A through R represent the 16-bit samples and show the Wallace tree levels to which the 17 different coefficient recodings place the corresponding multiplicand sample's bits.
- c 1 equals 4 (relative to c 34 equal to 2 18 ) and this implies one partial product which arises from shifting the sample's bits two places; the sample's 16 bits are denoted by A 15 down to A 0 and are located under the 16 bit positions 2 17 through 2 2 .
- c 3 equals -24 which recodes to -32+8 and generates two partial products for its corresponding multiplicand sample B with bits B 15 through B 0 entered twice, once shifted 3 bits and once (negated) shifted 5 bits. If the multiplicand sample were negative, then its leading bit would be a 1 and sign extension 1s would be needed.
- the top lines in FIG. 15 illustrate how to handle this possibility: a sign extension word of 1s for A appears under 2 19 and extending to the left edge (2 31 is the maximum shown). Also, the bit equal to the complement of A 15 is entered under 2 18 and a carry bit 1 is also entered uner 2 18 .
- filter 300 has the low bit weight positions in the Wallace trees truncated. This removes a portion of the Wallace tree hardware and simply disregards the corresponding bits which would have entered the truncated portions.
- FIG. 13 shows the method used to determine location of the truncation in the Wallace trees. In particular, the columns add the number of bits under each power of 2 for each Wallace tree by adding the number of partial products plus the number of carry bits shown in FIG. 11. Accumulate the number of bits for a column by considering the carries from lower power of 2 columns, and this determines the maximum which could be disregarded. In particular, for the 2 8 column the total is 122.
- the effects of this hardware truncation on the filter performance should be negligible in the spectral sense. Random mistakes in the filter response computation for points of the time domain output will not greatly effect the spectral response because the spectral response is a Fourier transform of the time domain responses. A Fourier transform invokes integration over time domain responses, and random noise has a uniform power spectral density without any spectral spikes. This means that tolerances in passband and stopband will not be jeopardized. Thus the hardware savings by hardware truncation has a time domain impact which spectrally averages out by the Fourier transform integration. Also, truncations greater than or less than filter 300's may be used; the method of focussing on the rounding bit may be changed. Greater truncation saves more hardware but creates greater noise, and conversely for less truncation.
- Rounders 342 and 344 allow the user to control the number of output bits. Rounding is done by generating a carry -- in for the bit position just below the LSB of interest and then truncating the output. Saturation detect logic disables the carry -- in when the most positive number (0111 . . . 111xxx when rounding away the last four bits) is present and the carry -- in would have resulted in adder rollover to the most negative number (1000 . . . 000xxx which truncates to 1000 . . . 00).
- FIG. 14 illustrates the saturation detection circuitry with DATA bit inputs and SETRND (setround) inputs. Also provided is the function of zeroing the bits below the LSB of interest after rounding.
- the critical speed path would be from DATA -- IN changing, through the saturation detect to signal CARRY0, and through the 17 bit adder.
- the fastest 17 bit adder will come from a 17 bit tree adder with the unused B inputs demorganized to reduce logic.
- true/complementers 322, 324, 332, and 334 all have saturation compensation; whereas, true/complementer 332 must also include accumulator overflow compensation.
- true/complementer 332 must also include accumulator overflow compensation.
- this representation of numbers is asymmetric in that there is one more negative number than positive number due to zero being one of the numbers with a sign bit 0.
- the largest positive number is 2 15 -1 and is represented by 0111 1111 1111 1111, but the negative number with the largest magnitude is -2 15 and is represented by 1000 0000 0000 0000.
- Now taking the two's complement of 2 15 -1's representative yields 1000 0000 0000 0001 which represents -(2 15 -1), as expected.
- the two's complement of -2 15 's representative 1000 0000 0000 0000 is again 1000 0000 0000 0000, analogous to the two's complement of 0000 0000 0000 0000 reproducing itself.
- true/complementers 322, 324, and 334 have a detection circuit for 1000 0000 0000 0000 and force an output of the largest positive number 0111 1111 1111 rather than taking the erroneous two's complement. Thus there will be an error of one bit, but this is the best that can be
- True/complementer 332 compensates for saturation and also for overflow from the adder of filter odd arm 327. True/complementer 332 outputs 17 bits because odd arm 327 outputs 17 bits and rounding will be done in rounder 342. In particular, the adder has extra bits above the 17 bits to be output, and these bits are used to monitor overflow. In decimation mode for half-band filter 300, the 17th(2 34 ) and 18th(2 35 ) bits are compared, and for the other three modes (interpolation mode, downconvert plus decimate mode, and interpolate plus upconvert mode) the 17th(2 33 ), 18th(2 34 ), and 19th(2 35 ) bits are monitored.
- decimation mode for half-band filter 300 the 17th(2 34 ) and 18th(2 35 ) bits are compared, and for the other three modes (interpolation mode, downconvert plus decimate mode, and interpolate plus upconvert mode) the 17th(2 33 ), 18th(2 34 ), and
- True/complementer 332 provides saturation in the same manner as true/complementers 322, 324, and 334.
- the preferred embodiments may be varied in many ways while retaining the features of a filter multiplier using Wallace trees with all lower bits hardware truncated and joint saturation plus overflow compensation.
- the filter need not be a half-band filter, but any digital filter with multipliers which yield products that are rounded off.
- the hardware contributing only to bits which are rounded off could be truncated.
Abstract
Description
R=R.sub.1 R.sub.2 . . . R.sub.M
______________________________________ Mode 1pin Mode 0 pin Mode of operation ______________________________________ 0 0 Decimation by 2Filter 0 1 Interpolation by 2Filter 1 0 Downconversion withDecimation Filter 1 1 Interpolation Filter with Upconversion ______________________________________
Y.sub.1 =c.sub.1 X.sub.67 +c.sub.2 X.sub.66 +c.sub.3 X.sub.65 +. . . +c.sub.34 X.sub.34 +. . . +c.sub.66 X.sub.2 +c.sub.67 X.sub.1
Y.sub.3 =c.sub.1 X.sub.69 +c.sub.2 X.sub.68 +c.sub.3 X.sub.67 +. . . +c.sub.34 X.sub.36 +. . . +c.sub.66 X.sub.4 +c.sub.67 X.sub.3
Y.sub.5 =c.sub.1 C.sub.71 +c.sub.2 X.sub.70 +c.sub.3 X.sub.69 +. . . +c.sub.34 X.sub.38 +. . . +c.sub.66 X.sub.6 +c.sub.67 X.sub.5
Y.sub.1 =c.sub.1 X.sub.67 +c.sub.3 X.sub.65 +. . . +c.sub.34 X.sub.34 +. . . +c.sub.65 X.sub.3 +c.sub.67 X.sub.1
Y.sub.3 =c.sub.1 X.sub.69 +c.sub.3 X.sub.67 +. . . +c.sub.34 X.sub.36 +. . . +c.sub.65 X.sub.5 +c.sub.67 X.sub.3
Y.sub.5 =c.sub.1 C.sub.71 +c.sub.3 X.sub.69 +. . . +c.sub.34 X.sub.38 +. . . +c.sub.65 X.sub.7 c.sub.67 X.sub.5
Y.sub.1 =c.sub.1 X.sub.34 +c.sub.3 X.sub.33 +c.sub.5 X.sub.32 +. . . +c.sub.65 X.sub.2 +c.sub.67 X.sub.1
Y.sub.2 =c.sub.2 X.sub.34 +c.sub.4 X.sub.33 +c.sub.6 X.sub.32 +. . . +c.sub.64 X.sub.3 +c.sub.66 X.sub.2
Y.sub.3 =c.sub.1 X.sub.35 +c.sub.3 X.sub.34 +c.sub.5 X.sub.33 +. . . +c.sub.65 X.sub.3 +c.sub.67 X.sub.2
Y.sub.1 =-c.sub.1 X.sub.67 +c.sub.3 X.sub.65 -c.sub.5 X.sub.63 +. . . -c.sub.65 X.sub.3 c.sub.67 X.sub.1
Y.sub.3 =c.sub.1 X.sub.69 -c.sub.3 X.sub.67 +c.sub.5 X.sub.65 +. . . +c.sub.65 X.sub.5 -c.sub.67 X.sub.3
Y.sub.5 =-c.sub.1 X.sub.71 +c.sub.3 X.sub.69 -c.sub.5 X.sub.67 +. . . -c.sub.65 X.sub.7 +c.sub.67 X.sub.5
Z.sub.1 =+c.sub.2 X.sub.66 -c.sub.4 X.sub.64 +. . . -c.sub.64 X.sub.4 +c.sub.66 X.sub.2
Z.sub.3 =-c.sub.2 X.sub.68 +c.sub.4 X.sub.66 +. . . +c.sub.64 X.sub.6 -c.sub.66 X.sub.4
Z.sub.5 =+c.sub.2 X.sub.70 -c.sub.4 X.sub.68 +. . . -c.sub.64 X.sub.8 +c.sub.66 X.sub.6
Y.sub.1 =c.sub.1 X.sub.34 +c.sub.3 X.sub.33 +c.sub.5 X.sub.32 +. . . +c.sub.65 X.sub.2 +c.sub.67 X.sub.1
Y.sub.2 =c.sub.2 X.sub.34 +c.sub.4 X.sub.33 +c.sub.6 X.sub.33 +. . . +c.sub.64 X.sub.3 +c.sub.66 X.sub.2
Y.sub.3 =c.sub.1 X.sub.35 +c.sub.3 X.sub.34 +c.sub.5 X.sub.33 +. . . +c.sub.65 X.sub.3 +c.sub.67 X.sub.2
V.sub.1 =c.sub.1 U.sub.34 +c.sub.3 U.sub.33 +c.sub.5 U.sub.32 +. . . +c.sub.65 U.sub.2 +c.sub.67 U.sub.1
V.sub.2 =c.sub.2 U.sub.34 +c.sub.4 U.sub.33 +c.sub.6 U.sub.33 +. . . +c.sub.64 U.sub.3 +c.sub.66 U.sub.2
V.sub.3 =c.sub.1 U.sub.35 +c.sub.3 U.sub.34 +c.sub.5 U.sub.33 +. . . +c.sub.65 U.sub.3 +c.sub.67 U.sub.2
______________________________________ RND (2.0) FUNCTION ______________________________________ 000 Round for 8 output bits, zero bits below. 001 Round for 9 output bits, zero bits below. 010 Round for 10 output bits, zero bits below. 011 Round for 11 output bits, zero bits below. 100 Round for 12 output bits, zero bits below. 101 Round for 14 bits, zero bits below. 110 Round for 16 bits, zero bits below. 111 Zero all outputs. ______________________________________
______________________________________ overflow sign complement overflow data bits ______________________________________ 1 0 0 0 1111 1111 1111 1111 1 1 0 1 0000 0000 0000 0000 1 0 1 1 0000 0000 0000 0000 1 1 1 0 1111 1111 1111 1111 ______________________________________
Claims (12)
Priority Applications (2)
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US08/304,433 US5548542A (en) | 1992-08-14 | 1994-09-12 | Half-band filter and method |
US08/462,684 US5574671A (en) | 1992-08-14 | 1995-06-05 | True/complementer for a half-band filter |
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US93016792A | 1992-08-14 | 1992-08-14 | |
US08/304,433 US5548542A (en) | 1992-08-14 | 1994-09-12 | Half-band filter and method |
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US93016792A Continuation | 1992-08-14 | 1992-08-14 |
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US08/462,684 Division US5574671A (en) | 1992-08-14 | 1995-06-05 | True/complementer for a half-band filter |
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US5548542A true US5548542A (en) | 1996-08-20 |
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US08/462,684 Expired - Lifetime US5574671A (en) | 1992-08-14 | 1995-06-05 | True/complementer for a half-band filter |
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