US5821168A - Process for forming a semiconductor device - Google Patents
Process for forming a semiconductor device Download PDFInfo
- Publication number
- US5821168A US5821168A US08/895,017 US89501797A US5821168A US 5821168 A US5821168 A US 5821168A US 89501797 A US89501797 A US 89501797A US 5821168 A US5821168 A US 5821168A
- Authority
- US
- United States
- Prior art keywords
- layer
- approximately
- copper
- forming
- depositing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 75
- 229910052802 copper Inorganic materials 0.000 claims abstract description 75
- 239000010949 copper Substances 0.000 claims abstract description 75
- 230000004888 barrier function Effects 0.000 claims abstract description 27
- 238000000151 deposition Methods 0.000 claims abstract description 22
- 239000000463 material Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 21
- 229910052710 silicon Inorganic materials 0.000 claims description 21
- 239000010703 silicon Substances 0.000 claims description 21
- 230000009977 dual effect Effects 0.000 claims description 14
- 238000002161 passivation Methods 0.000 claims description 6
- 238000007747 plating Methods 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 6
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 claims description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 229910052749 magnesium Inorganic materials 0.000 claims description 2
- 239000011777 magnesium Substances 0.000 claims description 2
- 239000010936 titanium Substances 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 claims 13
- 239000002184 metal Substances 0.000 claims 13
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims 3
- 238000009792 diffusion process Methods 0.000 abstract description 16
- 239000002131 composite material Substances 0.000 abstract description 9
- 230000008021 deposition Effects 0.000 description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- OJCDKHXKHLJDOT-UHFFFAOYSA-N fluoro hypofluorite;silicon Chemical compound [Si].FOF OJCDKHXKHLJDOT-UHFFFAOYSA-N 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005121 nitriding Methods 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 239000006117 anti-reflective coating Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- -1 nitrogen-containing compound Chemical class 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000005382 thermal cycling Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
Abstract
Description
Claims (21)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/895,017 US5821168A (en) | 1997-07-16 | 1997-07-16 | Process for forming a semiconductor device |
JP10202766A JPH1140671A (en) | 1997-07-16 | 1998-07-02 | Process for forming semiconductor device |
KR10-1998-0028278A KR100505513B1 (en) | 1997-07-16 | 1998-07-14 | Process for forming a semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/895,017 US5821168A (en) | 1997-07-16 | 1997-07-16 | Process for forming a semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
US5821168A true US5821168A (en) | 1998-10-13 |
Family
ID=25403837
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/895,017 Expired - Lifetime US5821168A (en) | 1997-07-16 | 1997-07-16 | Process for forming a semiconductor device |
Country Status (3)
Country | Link |
---|---|
US (1) | US5821168A (en) |
JP (1) | JPH1140671A (en) |
KR (1) | KR100505513B1 (en) |
Cited By (138)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5930669A (en) * | 1997-04-03 | 1999-07-27 | International Business Machines Corporation | Continuous highly conductive metal wiring structures and method for fabricating the same |
US5933758A (en) * | 1997-05-12 | 1999-08-03 | Motorola, Inc. | Method for preventing electroplating of copper on an exposed surface at the edge exclusion of a semiconductor wafer |
US5990011A (en) * | 1997-09-18 | 1999-11-23 | Micron Technology, Inc. | Titanium aluminum alloy wetting layer for improved aluminum filling of damescene trenches |
US6040243A (en) * | 1999-09-20 | 2000-03-21 | Chartered Semiconductor Manufacturing Ltd. | Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion |
US6046108A (en) * | 1999-06-25 | 2000-04-04 | Taiwan Semiconductor Manufacturing Company | Method for selective growth of Cu3 Ge or Cu5 Si for passivation of damascene copper structures and device manufactured thereby |
US6045435A (en) * | 1997-08-04 | 2000-04-04 | Motorola, Inc. | Low selectivity chemical mechanical polishing (CMP) process for use on integrated circuit metal interconnects |
US6054379A (en) * | 1998-02-11 | 2000-04-25 | Applied Materials, Inc. | Method of depositing a low k dielectric with organo silane |
EP0999584A2 (en) * | 1998-11-06 | 2000-05-10 | Nec Corporation | Method for manufacturing semiconductor device |
US6069068A (en) * | 1997-05-30 | 2000-05-30 | International Business Machines Corporation | Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity |
US6071809A (en) * | 1998-09-25 | 2000-06-06 | Rockwell Semiconductor Systems, Inc. | Methods for forming high-performing dual-damascene interconnect structures |
US6080656A (en) * | 1999-09-01 | 2000-06-27 | Taiwan Semiconductor Manufacturing Company | Method for forming a self-aligned copper structure with improved planarity |
US6100196A (en) * | 1996-04-08 | 2000-08-08 | Chartered Semiconductor Manufacturing Ltd. | Method of making a copper interconnect with top barrier layer |
US6130157A (en) * | 1999-07-16 | 2000-10-10 | Taiwan Semiconductor Manufacturing Company | Method to form an encapsulation layer over copper interconnects |
US6140234A (en) * | 1998-01-20 | 2000-10-31 | International Business Machines Corporation | Method to selectively fill recesses with conductive metal |
US6150261A (en) * | 1999-05-25 | 2000-11-21 | United Microelectronics Corp. | Method of fabricating semiconductor device for preventing antenna effect |
US6156648A (en) * | 1999-03-10 | 2000-12-05 | United Microelectronics Corp. | Method for fabricating dual damascene |
US6174810B1 (en) * | 1998-04-06 | 2001-01-16 | Motorola, Inc. | Copper interconnect structure and method of formation |
US6191025B1 (en) * | 1999-07-08 | 2001-02-20 | Taiwan Semiconductor Manufacturing Company | Method of fabricating a damascene structure for copper medullization |
US6197681B1 (en) * | 1999-12-31 | 2001-03-06 | United Microelectronics Corp. | Forming copper interconnects in dielectric materials with low constant dielectrics |
US6204179B1 (en) * | 1998-03-11 | 2001-03-20 | Micron Technology, Inc. | Copper diffusion barrier, aluminum wetting layer and improved methods for filling openings in silicon substrates with copper |
US6207553B1 (en) * | 1999-01-26 | 2001-03-27 | Advanced Micro Devices, Inc. | Method of forming multiple levels of patterned metallization |
US6218302B1 (en) * | 1998-07-21 | 2001-04-17 | Motorola Inc. | Method for forming a semiconductor device |
US6224737B1 (en) * | 1999-08-19 | 2001-05-01 | Taiwan Semiconductor Manufacturing Company | Method for improvement of gap filling capability of electrochemical deposition of copper |
US6232230B1 (en) * | 1999-01-05 | 2001-05-15 | Advanced Micro Devices, Inc. | Semiconductor interconnect interface processing by high temperature deposition |
US6251759B1 (en) * | 1998-10-03 | 2001-06-26 | Applied Materials, Inc. | Method and apparatus for depositing material upon a semiconductor wafer using a transition chamber of a multiple chamber semiconductor wafer processing system |
US6251770B1 (en) * | 1999-06-30 | 2001-06-26 | Lam Research Corp. | Dual-damascene dielectric structures and methods for making the same |
FR2805084A1 (en) * | 2000-02-14 | 2001-08-17 | St Microelectronics Sa | Metal track production for integrated circuits comprises incorporation of titanium layer to prevent diffusion of silicon into copper in metal track |
US6277730B1 (en) * | 1998-02-17 | 2001-08-21 | Matsushita Electronics Corporation | Method of fabricating interconnects utilizing fluorine doped insulators and barrier layers |
US6281121B1 (en) * | 1998-03-06 | 2001-08-28 | Advanced Micro Devices, Inc. | Damascene metal interconnects using highly directional deposition of barrier and/or seed layers including (III) filling metal |
US6281127B1 (en) | 1999-04-15 | 2001-08-28 | Taiwan Semiconductor Manufacturing Company | Self-passivation procedure for a copper damascene structure |
US6284657B1 (en) * | 2000-02-25 | 2001-09-04 | Chartered Semiconductor Manufacturing Ltd. | Non-metallic barrier formation for copper damascene type interconnects |
US6287990B1 (en) | 1998-02-11 | 2001-09-11 | Applied Materials, Inc. | CVD plasma assisted low dielectric constant films |
US6287954B1 (en) | 1997-05-30 | 2001-09-11 | International Business Machines Corporation | Method of forming copper interconnections with enhanced electromigration resistance and reduced defect sensitivity |
US6303523B2 (en) | 1998-02-11 | 2001-10-16 | Applied Materials, Inc. | Plasma processes for depositing low dielectric constant films |
US6335570B2 (en) * | 1998-05-01 | 2002-01-01 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
US6344410B1 (en) * | 1999-03-30 | 2002-02-05 | Advanced Micro Devices, Inc. | Manufacturing method for semiconductor metalization barrier |
US6348421B1 (en) * | 1998-02-06 | 2002-02-19 | National Semiconductor Corporation | Dielectric gap fill process that effectively reduces capacitance between narrow metal lines using HDP-CVD |
US6350364B1 (en) * | 2000-02-18 | 2002-02-26 | Taiwan Semiconductor Manufacturing Company | Method for improvement of planarity of electroplated copper |
WO2002017388A2 (en) * | 2000-08-23 | 2002-02-28 | Applied Materials, Inc. | Method of improving the adhesion of copper |
US6352940B1 (en) * | 1998-06-26 | 2002-03-05 | Intel Corporation | Semiconductor passivation deposition process for interfacial adhesion |
US6358831B1 (en) * | 1999-03-03 | 2002-03-19 | Taiwan Semiconductor Manufacturing Company | Method for forming a top interconnection level and bonding pads on an integrated circuit chip |
US6358842B1 (en) * | 2000-08-07 | 2002-03-19 | Chartered Semiconductor Manufacturing Ltd. | Method to form damascene interconnects with sidewall passivation to protect organic dielectrics |
US6368953B1 (en) * | 2000-05-09 | 2002-04-09 | International Business Machines Corporation | Encapsulated metal structures for semiconductor devices and MIM capacitors including the same |
US6372632B1 (en) | 2000-01-24 | 2002-04-16 | Taiwan Semiconductor Manufacturing Company | Method to eliminate dishing of copper interconnects by the use of a sacrificial oxide layer |
US6387800B1 (en) | 1999-12-20 | 2002-05-14 | Taiwan Semiconductor Manufacturing Company | Method of forming barrier and seed layers for electrochemical deposition of copper |
US6391783B1 (en) | 2000-07-13 | 2002-05-21 | Chartered Semiconductor Manufacturing Ltd. | Method to thin down copper barriers in deep submicron geometries by using alkaline earth element, barrier additives, or self assembly technique |
US6395642B1 (en) | 1999-12-28 | 2002-05-28 | Taiwan Semiconductor Manufacturing Company | Method to improve copper process integration |
US6399489B1 (en) | 1999-11-01 | 2002-06-04 | Applied Materials, Inc. | Barrier layer deposition using HDP-CVD |
US6403462B1 (en) * | 1998-05-29 | 2002-06-11 | Kabushiki Kaisha Toshiba | Method for manufacturing high reliability interconnection having diffusion barrier layer |
EP1217648A2 (en) * | 2000-12-19 | 2002-06-26 | Canon Sales Co., Inc. | Method of manufacturing an interlayer dielectric layer with low dielectric constant |
US6417094B1 (en) * | 1998-12-31 | 2002-07-09 | Newport Fab, Llc | Dual-damascene interconnect structures and methods of fabricating same |
KR100345528B1 (en) * | 1999-09-29 | 2002-07-26 | 인터내셔널 비지네스 머신즈 코포레이션 | Dual damascene flowable oxide insulation structure and metallic barrier |
US6425987B1 (en) * | 1999-11-25 | 2002-07-30 | National Science Council | Technique for deposition of multilayer interference thin films using silicon as the only coating material |
US6429117B1 (en) | 2000-07-19 | 2002-08-06 | Chartered Semiconductor Manufacturing Ltd. | Method to create copper traps by modifying treatment on the dielectrics surface |
US20020109233A1 (en) * | 2000-01-18 | 2002-08-15 | Micron Technology, Inc. | Process for providing seed layers for integrated circuit metallurgy |
US20020129972A1 (en) * | 2001-03-13 | 2002-09-19 | International Business Machines Corporation | Structure having laser ablated Features and method of fabricating |
WO2002078060A2 (en) * | 2001-03-27 | 2002-10-03 | Advanced Micro Devices, Inc. | Damascene processing using dielectric barrier films |
US20020177006A1 (en) * | 2001-05-23 | 2002-11-28 | International Business Machines Corporation | Structure having flush circuitry features and method of making |
US6492268B1 (en) * | 1999-12-22 | 2002-12-10 | Hyundai Electronics Industries Co., Ltd. | Method of forming a copper wiring in a semiconductor device |
US20030032373A1 (en) * | 2001-01-05 | 2003-02-13 | Basol Bulent M. | Fabrication of semiconductor interconnect structures |
US6528412B1 (en) * | 2001-04-30 | 2003-03-04 | Advanced Micro Devices, Inc. | Depositing an adhesion skin layer and a conformal seed layer to fill an interconnect opening |
US6531398B1 (en) | 2000-10-30 | 2003-03-11 | Applied Materials, Inc. | Method of depositing organosillicate layers |
US20030049388A1 (en) * | 2001-09-10 | 2003-03-13 | Seon-Mee Cho | Silicon carbide deposited by high density plasma chemical-vapor deposition with bias |
KR100376259B1 (en) * | 2000-12-27 | 2003-03-17 | 주식회사 하이닉스반도체 | Method of forming a copper wiring in a semiconductor device |
US6551919B2 (en) * | 1999-07-13 | 2003-04-22 | Motorola, Inc. | Method for forming a dual inlaid copper interconnect structure |
US6551914B1 (en) * | 1997-03-31 | 2003-04-22 | Nec Electronics Corporation | Method of forming polish stop by plasma treatment for interconnection |
US20030082901A1 (en) * | 2001-10-31 | 2003-05-01 | Thomas Werner | Void formation monitoring in a damascene process |
US6566242B1 (en) * | 2001-03-23 | 2003-05-20 | International Business Machines Corporation | Dual damascene copper interconnect to a damascene tungsten wiring level |
US20030104708A1 (en) * | 2001-06-18 | 2003-06-05 | Applied Materials, Inc. | CVD plasma assisted lower dielectric constant sicoh film |
US6593655B1 (en) | 1998-05-29 | 2003-07-15 | Dow Corning Corporation | Method for producing hydrogenated silicon oxycarbide films having low dielectric constant |
US6593247B1 (en) | 1998-02-11 | 2003-07-15 | Applied Materials, Inc. | Method of depositing low k films using an oxidizing plasma |
US20030148223A1 (en) * | 2001-02-23 | 2003-08-07 | Applied Materials, Inc. | Method of depositing low dielectric constant silicon carbide layers |
US6633392B1 (en) | 2002-01-17 | 2003-10-14 | Advanced Micro Devices, Inc. | X-ray reflectance system to determine suitability of SiON ARC layer |
US20030194495A1 (en) * | 2002-04-11 | 2003-10-16 | Applied Materials, Inc. | Crosslink cyclo-siloxane compound with linear bridging group to form ultra low k dielectric |
US20030194496A1 (en) * | 2002-04-11 | 2003-10-16 | Applied Materials, Inc. | Methods for depositing dielectric material |
US20030194880A1 (en) * | 2002-04-16 | 2003-10-16 | Applied Materials, Inc. | Use of cyclic siloxanes for hardness improvement |
US20030206337A1 (en) * | 2002-05-06 | 2003-11-06 | Eastman Kodak Company | Exposure apparatus for irradiating a sensitized substrate |
US20030211244A1 (en) * | 2002-04-11 | 2003-11-13 | Applied Materials, Inc. | Reacting an organosilicon compound with an oxidizing gas to form an ultra low k dielectric |
US6656837B2 (en) | 2001-10-11 | 2003-12-02 | Applied Materials, Inc. | Method of eliminating photoresist poisoning in damascene applications |
US6660656B2 (en) | 1998-02-11 | 2003-12-09 | Applied Materials Inc. | Plasma processes for depositing low dielectric constant films |
US6663786B2 (en) | 2001-06-14 | 2003-12-16 | International Business Machines Corporation | Structure having embedded flush circuitry features and method of fabricating |
US6667553B2 (en) | 1998-05-29 | 2003-12-23 | Dow Corning Corporation | H:SiOC coated substrates |
US20040009676A1 (en) * | 2002-07-11 | 2004-01-15 | Applied Materials, Inc. | Nitrogen-free dielectric anti-reflective coating and hardmask |
US20040029400A1 (en) * | 1998-02-11 | 2004-02-12 | Applied Materials, Inc. | Method of decreasing the K value in SIOC layer deposited by chemical vapor deposition |
US6696360B2 (en) | 2001-03-15 | 2004-02-24 | Micron Technology, Inc. | Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow |
US20040038507A1 (en) * | 1998-09-23 | 2004-02-26 | Infineon Technologies Ag | Method of producing an integrated circuit configuration |
US6703307B2 (en) | 2001-11-26 | 2004-03-09 | Advanced Micro Devices, Inc. | Method of implantation after copper seed deposition |
US6703308B1 (en) | 2001-11-26 | 2004-03-09 | Advanced Micro Devices, Inc. | Method of inserting alloy elements to reduce copper diffusion and bulk diffusion |
US6709721B2 (en) | 2001-03-28 | 2004-03-23 | Applied Materials Inc. | Purge heater design and process development for the improvement of low k film properties |
US20040063307A1 (en) * | 2002-09-30 | 2004-04-01 | Subramanian Karthikeyan | Method to avoid copper contamination of a via or dual damascene structure |
US6716746B1 (en) * | 1999-09-16 | 2004-04-06 | Samsung Electronics Co., Ltd. | Semiconductor device having self-aligned contact and method of fabricating the same |
US6726529B2 (en) * | 1997-12-29 | 2004-04-27 | Intel Corporation | Low temperature chemical mechanical polishing of dielectric materials |
US6740580B1 (en) | 1999-09-03 | 2004-05-25 | Chartered Semiconductor Manufacturing Ltd. | Method to form copper interconnects by adding an aluminum layer to the copper diffusion barrier |
US6743716B2 (en) | 2000-01-18 | 2004-06-01 | Micron Technology, Inc. | Structures and methods to enhance copper metallization |
US6750141B2 (en) | 2001-03-28 | 2004-06-15 | Applied Materials Inc. | Silicon carbide cap layers for low dielectric constant silicon oxide layers |
US6756298B2 (en) | 2000-01-18 | 2004-06-29 | Micron Technology, Inc. | Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals |
US20040130035A1 (en) * | 2003-01-07 | 2004-07-08 | Zhen-Cheng Wu | Method of forming copper interconnects |
US20040152338A1 (en) * | 2003-01-31 | 2004-08-05 | Applied Materials, Inc. | Method for depositing a low dielectric constant film |
US20040214446A1 (en) * | 2002-07-11 | 2004-10-28 | Applied Materials, Inc. | Nitrogen-free dielectric anti-reflective coating and hardmask |
US20040219738A1 (en) * | 2000-08-22 | 2004-11-04 | Dinesh Chopra | Method of providing a structure using self-aligned features |
US6835655B1 (en) * | 2001-11-26 | 2004-12-28 | Advanced Micro Devices, Inc. | Method of implanting copper barrier material to improve electrical performance |
US6836400B2 (en) * | 2000-02-24 | 2004-12-28 | Newport Fab, Llc | Structures based on ceramic tantalum nitride |
US20040262764A1 (en) * | 2003-06-23 | 2004-12-30 | International Business Machines Corporation | Dual damascene interconnect structures having different materials for line and via conductors |
US6861349B1 (en) | 2002-05-15 | 2005-03-01 | Advanced Micro Devices, Inc. | Method of forming an adhesion layer with an element reactive with a barrier layer |
US20050085073A1 (en) * | 2003-10-16 | 2005-04-21 | Advanced Micro Devices, Inc. | Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper deposition |
US20050095843A1 (en) * | 2003-10-30 | 2005-05-05 | West Jeffrey A. | Method for improving reliability of copper interconnects |
US20050153570A1 (en) * | 2002-05-13 | 2005-07-14 | Tokyo Electron Limited | Substrate processing method |
US20050181542A1 (en) * | 2003-10-21 | 2005-08-18 | Ziptronix, Inc. | Single mask via method and device |
US20050178423A1 (en) * | 2004-02-12 | 2005-08-18 | Shriram Ramanathan | Microelectronic assembly having thermoelectric elements to cool a die and a method of making the same |
US6936309B2 (en) | 2002-04-02 | 2005-08-30 | Applied Materials, Inc. | Hardness improvement of silicon carboxy films |
US20050227480A1 (en) * | 2004-04-02 | 2005-10-13 | International Business Machines Corporation (Ibm) | Low dielectric semiconductor device and process for fabricating the same |
US20050250321A1 (en) * | 2004-05-06 | 2005-11-10 | Eui-Seong Hwang | Method for fabricating semiconductor device having diffusion barrier layer |
US20050263900A1 (en) * | 1998-11-17 | 2005-12-01 | Applied Materials, Inc. | Semiconductor device having silicon carbide and conductive pathway interface |
US20050272258A1 (en) * | 2004-06-04 | 2005-12-08 | Toshiyuki Morita | Method of manufacturing a semiconductor device and semiconductor device |
US6974766B1 (en) | 1998-10-01 | 2005-12-13 | Applied Materials, Inc. | In situ deposition of a low κ dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application |
US6979903B1 (en) * | 2001-06-04 | 2005-12-27 | Advanced Micro Devices, Inc. | Integrated circuit with dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers |
US20060024954A1 (en) * | 2004-08-02 | 2006-02-02 | Zhen-Cheng Wu | Copper damascene barrier and capping layer |
US20060131754A1 (en) * | 2003-07-18 | 2006-06-22 | Nec Corporation | Semiconductor device having trench interconnection and manufacturing method of semiconductor device |
US7220665B2 (en) | 2003-08-05 | 2007-05-22 | Micron Technology, Inc. | H2 plasma treatment |
US7253521B2 (en) | 2000-01-18 | 2007-08-07 | Micron Technology, Inc. | Methods for making integrated-circuit wiring from copper, silver, gold, and other metals |
US7288205B2 (en) | 2004-07-09 | 2007-10-30 | Applied Materials, Inc. | Hermetic low dielectric constant layer for barrier applications |
US20070278624A1 (en) * | 2005-02-24 | 2007-12-06 | Anderson Brent A | Damascene filament wire structure |
US20070281463A1 (en) * | 1998-12-21 | 2007-12-06 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
WO2008028850A1 (en) * | 2006-09-04 | 2008-03-13 | Koninklijke Philips Electronics N.V. | CuSiN/SiN DIFFUSION BARRIER FOR COPPER IN INTEGRATED-CIRCUIT DEVICES |
US20090185060A1 (en) * | 2008-01-21 | 2009-07-23 | Sony Corporation | Solid-state imaging device, method of fabricating solid-state imaging device, and camera |
US20090212439A1 (en) * | 2008-02-27 | 2009-08-27 | International Business Machines Corporation | Fluorine depleted adhesion layer for metal interconnect structure |
US7696092B2 (en) | 2001-11-26 | 2010-04-13 | Globalfoundries Inc. | Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect |
US20100178762A1 (en) * | 2005-08-30 | 2010-07-15 | Fujitsu Limited | Manufacture method for semiconductor device suitable for forming wirings by damascene method and semiconductor device |
CN102468430A (en) * | 2010-11-05 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | Implementation method for improving adhesiveness of phase change material |
US20130029485A1 (en) * | 2011-07-28 | 2013-01-31 | Spencer Gregory S | Method of making a die with recessed alumium die pads |
US8461043B2 (en) * | 2011-04-11 | 2013-06-11 | Micron Technology, Inc. | Barrier layer for integrated circuit contacts |
US20140134848A1 (en) * | 2012-11-09 | 2014-05-15 | Tokyo Electron Limited | Plasma etching method and plasma etching apparatus |
TWI483407B (en) * | 2011-06-17 | 2015-05-01 | Globalfoundries Us Inc | Integrated circuits including barrier polish stop layers and methods for the manufacture thereof |
US9425093B2 (en) * | 2014-12-05 | 2016-08-23 | Tokyo Electron Limited | Copper wiring forming method, film forming system, and storage medium |
US20180061702A1 (en) * | 2016-08-30 | 2018-03-01 | International Business Machines Corporation | Interconnect structure |
WO2019067579A1 (en) * | 2017-09-27 | 2019-04-04 | Invensas Corporation | Interconnect structures and methods for forming same |
US11444039B2 (en) * | 2020-05-29 | 2022-09-13 | Sandisk Technologies Llc | Semiconductor die including diffusion barrier layers embedding bonding pads and methods of forming the same |
US11450624B2 (en) * | 2020-05-29 | 2022-09-20 | Sandisk Technologies Llc | Semiconductor die including diffusion barrier layers embedding bonding pads and methods of forming the same |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3087719B2 (en) * | 1998-04-08 | 2000-09-11 | 日本電気株式会社 | Semiconductor device manufacturing method and manufacturing apparatus |
KR100384876B1 (en) * | 1999-06-24 | 2003-05-22 | 주식회사 하이닉스반도체 | Improved dual damascene process in semiconductor device |
US6551924B1 (en) * | 1999-11-02 | 2003-04-22 | International Business Machines Corporation | Post metalization chem-mech polishing dielectric etch |
KR100436134B1 (en) * | 1999-12-30 | 2004-06-14 | 주식회사 하이닉스반도체 | Method for forming metal line of semiconductor device |
US6686662B2 (en) * | 2002-05-21 | 2004-02-03 | Agere Systems Inc. | Semiconductor device barrier layer |
JP4741965B2 (en) | 2006-03-23 | 2011-08-10 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5332691A (en) * | 1992-05-14 | 1994-07-26 | Sharp Kabushiki Kaisha | Method of forming a contact |
US5604158A (en) * | 1993-03-31 | 1997-02-18 | Intel Corporation | Integrated tungsten/tungsten silicide plug process |
US5741626A (en) * | 1996-04-15 | 1998-04-21 | Motorola, Inc. | Method for forming a dielectric tantalum nitride layer as an anti-reflective coating (ARC) |
-
1997
- 1997-07-16 US US08/895,017 patent/US5821168A/en not_active Expired - Lifetime
-
1998
- 1998-07-02 JP JP10202766A patent/JPH1140671A/en active Pending
- 1998-07-14 KR KR10-1998-0028278A patent/KR100505513B1/en not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5332691A (en) * | 1992-05-14 | 1994-07-26 | Sharp Kabushiki Kaisha | Method of forming a contact |
US5604158A (en) * | 1993-03-31 | 1997-02-18 | Intel Corporation | Integrated tungsten/tungsten silicide plug process |
US5741626A (en) * | 1996-04-15 | 1998-04-21 | Motorola, Inc. | Method for forming a dielectric tantalum nitride layer as an anti-reflective coating (ARC) |
Non-Patent Citations (10)
Title |
---|
Author Anonymous, "Forming Tungsten-Nitrogen Films Using Plasma Etching", Research Disclosure 298087, Feb. 1989 and Abstract. |
Author Anonymous, Forming Tungsten Nitrogen Films Using Plasma Etching , Research Disclosure 298087, Feb. 1989 and Abstract. * |
Bai, et al., "Effectiveness and Reliability of Metal Diffusion Barriers for Copper Interconnects", Mat. Res. Soc. Symp. Proc., vol. 403, pp. 501-506 (1996). |
Bai, et al., Effectiveness and Reliability of Metal Diffusion Barriers for Copper Interconnects , Mat. Res. Soc. Symp. Proc., vol. 403, pp. 501 506 (1996). * |
Mikagi, et al. "Barrier Metal Free Copper Damascene Interconnection Technology Using Atmospheric Copper Reflow and Nitrogen Doping in SiOF Film", IEEE, International Electron Devicese, Meeting, pp. 395-468 (1996). |
Mikagi, et al. Barrier Metal Free Copper Damascene Interconnection Technology Using Atmospheric Copper Reflow and Nitrogen Doping in SiOF Film , IEEE, International Electron Devicese, Meeting, pp. 395 468 (1996). * |
Ting et al. "The Use of Titanium-Based Contact Barrier Layers in Silicon Technology", Thin Solid Films, 96, Electronics and Optics, pp. 327-345 (1982). |
Ting et al. The Use of Titanium Based Contact Barrier Layers in Silicon Technology , Thin Solid Films, 96, Electronics and Optics, pp. 327 345 (1982). * |
Vogt et al. "Plasma Deposited Dielectric Barriers for Cu Metallization", Electrochemical Society Proceedings, vol. 96-12, pp. 613-622 (1996). |
Vogt et al. Plasma Deposited Dielectric Barriers for Cu Metallization , Electrochemical Society Proceedings, vol. 96 12, pp. 613 622 (1996). * |
Cited By (286)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6100196A (en) * | 1996-04-08 | 2000-08-08 | Chartered Semiconductor Manufacturing Ltd. | Method of making a copper interconnect with top barrier layer |
US6551914B1 (en) * | 1997-03-31 | 2003-04-22 | Nec Electronics Corporation | Method of forming polish stop by plasma treatment for interconnection |
US5930669A (en) * | 1997-04-03 | 1999-07-27 | International Business Machines Corporation | Continuous highly conductive metal wiring structures and method for fabricating the same |
US6429519B1 (en) | 1997-04-03 | 2002-08-06 | International Business Machines Corporation | Wiring structures containing interconnected metal and wiring levels including a continuous, single crystalline or polycrystalline conductive material having one or more twin boundaries |
US5933758A (en) * | 1997-05-12 | 1999-08-03 | Motorola, Inc. | Method for preventing electroplating of copper on an exposed surface at the edge exclusion of a semiconductor wafer |
US6287954B1 (en) | 1997-05-30 | 2001-09-11 | International Business Machines Corporation | Method of forming copper interconnections with enhanced electromigration resistance and reduced defect sensitivity |
US6069068A (en) * | 1997-05-30 | 2000-05-30 | International Business Machines Corporation | Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity |
US6258710B1 (en) | 1997-05-30 | 2001-07-10 | International Business Machines Corporation | Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity |
US6045435A (en) * | 1997-08-04 | 2000-04-04 | Motorola, Inc. | Low selectivity chemical mechanical polishing (CMP) process for use on integrated circuit metal interconnects |
US5990011A (en) * | 1997-09-18 | 1999-11-23 | Micron Technology, Inc. | Titanium aluminum alloy wetting layer for improved aluminum filling of damescene trenches |
US6726529B2 (en) * | 1997-12-29 | 2004-04-27 | Intel Corporation | Low temperature chemical mechanical polishing of dielectric materials |
US6140234A (en) * | 1998-01-20 | 2000-10-31 | International Business Machines Corporation | Method to selectively fill recesses with conductive metal |
US7456501B1 (en) | 1998-01-20 | 2008-11-25 | International Business Machines Corporation | Semiconductor structure having recess with conductive metal |
US6348421B1 (en) * | 1998-02-06 | 2002-02-19 | National Semiconductor Corporation | Dielectric gap fill process that effectively reduces capacitance between narrow metal lines using HDP-CVD |
US6593615B1 (en) | 1998-02-06 | 2003-07-15 | National Semiconductor Corporation | Dielectric gap fill process that effectively reduces capacitance between narrow metal lines using HDP-CVD |
US6287990B1 (en) | 1998-02-11 | 2001-09-11 | Applied Materials, Inc. | CVD plasma assisted low dielectric constant films |
US20080061439A1 (en) * | 1998-02-11 | 2008-03-13 | Wai-Fan Yau | Low dielectric constant film produced from silicon compounds comprising silicon-carbon bond |
US6660663B1 (en) | 1998-02-11 | 2003-12-09 | Applied Materials Inc. | Computer readable medium for holding a program for performing plasma-assisted CVD of low dielectric constant films formed from organosilane compounds |
US7651725B2 (en) | 1998-02-11 | 2010-01-26 | Applied Materials, Inc. | Low dielectric constant film produced from silicon compounds comprising silicon-carbon bond |
US20080064225A1 (en) * | 1998-02-11 | 2008-03-13 | Wai-Fan Yau | Low dielectric constant film produced from silicon compounds comprising silicon-carbon bond |
US6541282B1 (en) | 1998-02-11 | 2003-04-01 | Applied Materials, Inc. | Plasma processes for depositing low dielectric constant films |
US20040166665A1 (en) * | 1998-02-11 | 2004-08-26 | Applied Materials, Inc. | Method of decreasing the K value in SIOC layer deposited by chemical vapor deposition |
US6303523B2 (en) | 1998-02-11 | 2001-10-16 | Applied Materials, Inc. | Plasma processes for depositing low dielectric constant films |
US6784119B2 (en) | 1998-02-11 | 2004-08-31 | Applied Materials Inc. | Method of decreasing the K value in SIOC layer deposited by chemical vapor deposition |
US6730593B2 (en) | 1998-02-11 | 2004-05-04 | Applied Materials Inc. | Method of depositing a low K dielectric with organo silane |
US6806207B2 (en) | 1998-02-11 | 2004-10-19 | Applied Materials Inc. | Method of depositing low K films |
US20040029400A1 (en) * | 1998-02-11 | 2004-02-12 | Applied Materials, Inc. | Method of decreasing the K value in SIOC layer deposited by chemical vapor deposition |
US6511903B1 (en) | 1998-02-11 | 2003-01-28 | Applied Materials, Inc. | Method of depositing a low k dielectric with organo silane |
US20050156317A1 (en) * | 1998-02-11 | 2005-07-21 | Applied Materials, Inc. | Low dielectric constant film produced from silicon compounds comprising silicon-carbon bonds |
US6593247B1 (en) | 1998-02-11 | 2003-07-15 | Applied Materials, Inc. | Method of depositing low k films using an oxidizing plasma |
US20080044557A1 (en) * | 1998-02-11 | 2008-02-21 | Wai-Fan Yau | Low dielectric constant film produced from silicon compounds comprising silicon-carbon bond |
US7074708B2 (en) | 1998-02-11 | 2006-07-11 | Applied Materials, Inc. | Method of decreasing the k value in sioc layer deposited by chemical vapor deposition |
US6537929B1 (en) | 1998-02-11 | 2003-03-25 | Applied Materials, Inc. | CVD plasma assisted low dielectric constant films |
US20050191846A1 (en) * | 1998-02-11 | 2005-09-01 | David Cheung | Plasma processes for depositing low dielectric constant films |
US20030162410A1 (en) * | 1998-02-11 | 2003-08-28 | Applied Materials, Inc. | Method of depositing low K films |
US6072227A (en) * | 1998-02-11 | 2000-06-06 | Applied Materials, Inc. | Low power method of depositing a low k dielectric with organo silane |
US6770556B2 (en) | 1998-02-11 | 2004-08-03 | Applied Materials Inc. | Method of depositing a low dielectric with organo silane |
US6660656B2 (en) | 1998-02-11 | 2003-12-09 | Applied Materials Inc. | Plasma processes for depositing low dielectric constant films |
US20040147109A1 (en) * | 1998-02-11 | 2004-07-29 | Applied Materials, Inc. | Low dielectric constant film produced from silicon compounds comprising silicon-carbon bond |
US7560377B2 (en) | 1998-02-11 | 2009-07-14 | Applied Materials, Inc. | Plasma processes for depositing low dielectric constant films |
US6562690B1 (en) | 1998-02-11 | 2003-05-13 | Applied Materials, Inc. | Plasma processes for depositing low dielectric constant films |
US6054379A (en) * | 1998-02-11 | 2000-04-25 | Applied Materials, Inc. | Method of depositing a low k dielectric with organo silane |
US6596655B1 (en) | 1998-02-11 | 2003-07-22 | Applied Materials Inc. | Plasma processes for depositing low dielectric constant films |
US6348725B2 (en) | 1998-02-11 | 2002-02-19 | Applied Materials, Inc. | Plasma processes for depositing low dielectric constant films |
US6277730B1 (en) * | 1998-02-17 | 2001-08-21 | Matsushita Electronics Corporation | Method of fabricating interconnects utilizing fluorine doped insulators and barrier layers |
US6365959B2 (en) | 1998-02-17 | 2002-04-02 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
US6281121B1 (en) * | 1998-03-06 | 2001-08-28 | Advanced Micro Devices, Inc. | Damascene metal interconnects using highly directional deposition of barrier and/or seed layers including (III) filling metal |
US6204179B1 (en) * | 1998-03-11 | 2001-03-20 | Micron Technology, Inc. | Copper diffusion barrier, aluminum wetting layer and improved methods for filling openings in silicon substrates with copper |
US6174810B1 (en) * | 1998-04-06 | 2001-01-16 | Motorola, Inc. | Copper interconnect structure and method of formation |
US6335570B2 (en) * | 1998-05-01 | 2002-01-01 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
US6552434B2 (en) | 1998-05-29 | 2003-04-22 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
US6403462B1 (en) * | 1998-05-29 | 2002-06-11 | Kabushiki Kaisha Toshiba | Method for manufacturing high reliability interconnection having diffusion barrier layer |
US6593655B1 (en) | 1998-05-29 | 2003-07-15 | Dow Corning Corporation | Method for producing hydrogenated silicon oxycarbide films having low dielectric constant |
US6667553B2 (en) | 1998-05-29 | 2003-12-23 | Dow Corning Corporation | H:SiOC coated substrates |
US6352940B1 (en) * | 1998-06-26 | 2002-03-05 | Intel Corporation | Semiconductor passivation deposition process for interfacial adhesion |
US7202568B2 (en) * | 1998-06-26 | 2007-04-10 | Intel Corporation | Semiconductor passivation deposition process for interfacial adhesion |
US6218302B1 (en) * | 1998-07-21 | 2001-04-17 | Motorola Inc. | Method for forming a semiconductor device |
US20040038507A1 (en) * | 1998-09-23 | 2004-02-26 | Infineon Technologies Ag | Method of producing an integrated circuit configuration |
US6998338B2 (en) * | 1998-09-23 | 2006-02-14 | Infineon Technologies Ag | Method of producing an integrated circuit configuration |
US6071809A (en) * | 1998-09-25 | 2000-06-06 | Rockwell Semiconductor Systems, Inc. | Methods for forming high-performing dual-damascene interconnect structures |
US7670945B2 (en) | 1998-10-01 | 2010-03-02 | Applied Materials, Inc. | In situ deposition of a low κ dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application |
US6974766B1 (en) | 1998-10-01 | 2005-12-13 | Applied Materials, Inc. | In situ deposition of a low κ dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application |
US7470611B2 (en) | 1998-10-01 | 2008-12-30 | Applied Materials, Inc. | In situ deposition of a low K dielectric layer, barrier layer, etch stop, and anti-reflective coating for damascene application |
US6251759B1 (en) * | 1998-10-03 | 2001-06-26 | Applied Materials, Inc. | Method and apparatus for depositing material upon a semiconductor wafer using a transition chamber of a multiple chamber semiconductor wafer processing system |
EP0999584A2 (en) * | 1998-11-06 | 2000-05-10 | Nec Corporation | Method for manufacturing semiconductor device |
EP0999584A3 (en) * | 1998-11-06 | 2000-08-30 | Nec Corporation | Method for manufacturing semiconductor device |
US6136708A (en) * | 1998-11-06 | 2000-10-24 | Nec Corporation | Method for manufacturing semiconductor device |
US20050263900A1 (en) * | 1998-11-17 | 2005-12-01 | Applied Materials, Inc. | Semiconductor device having silicon carbide and conductive pathway interface |
US8183150B2 (en) | 1998-11-17 | 2012-05-22 | Applied Materials, Inc. | Semiconductor device having silicon carbide and conductive pathway interface |
US20090050902A1 (en) * | 1998-11-17 | 2009-02-26 | Huang Judy H | Semiconductor device having silicon carbide and conductive pathway interface |
US20080146020A1 (en) * | 1998-12-21 | 2008-06-19 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
US8415800B2 (en) | 1998-12-21 | 2013-04-09 | Megica Corporation | Top layers of metal for high performance IC's |
US8471384B2 (en) | 1998-12-21 | 2013-06-25 | Megica Corporation | Top layers of metal for high performance IC's |
US8022545B2 (en) | 1998-12-21 | 2011-09-20 | Megica Corporation | Top layers of metal for high performance IC's |
US7999384B2 (en) | 1998-12-21 | 2011-08-16 | Megica Corporation | Top layers of metal for high performance IC's |
US8531038B2 (en) | 1998-12-21 | 2013-09-10 | Megica Corporation | Top layers of metal for high performance IC's |
US7863654B2 (en) | 1998-12-21 | 2011-01-04 | Megica Corporation | Top layers of metal for high performance IC's |
US20070281463A1 (en) * | 1998-12-21 | 2007-12-06 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
US7884479B2 (en) | 1998-12-21 | 2011-02-08 | Megica Corporation | Top layers of metal for high performance IC's |
US6417094B1 (en) * | 1998-12-31 | 2002-07-09 | Newport Fab, Llc | Dual-damascene interconnect structures and methods of fabricating same |
US6232230B1 (en) * | 1999-01-05 | 2001-05-15 | Advanced Micro Devices, Inc. | Semiconductor interconnect interface processing by high temperature deposition |
US6207553B1 (en) * | 1999-01-26 | 2001-03-27 | Advanced Micro Devices, Inc. | Method of forming multiple levels of patterned metallization |
US6358831B1 (en) * | 1999-03-03 | 2002-03-19 | Taiwan Semiconductor Manufacturing Company | Method for forming a top interconnection level and bonding pads on an integrated circuit chip |
US6156648A (en) * | 1999-03-10 | 2000-12-05 | United Microelectronics Corp. | Method for fabricating dual damascene |
US6344410B1 (en) * | 1999-03-30 | 2002-02-05 | Advanced Micro Devices, Inc. | Manufacturing method for semiconductor metalization barrier |
US6281127B1 (en) | 1999-04-15 | 2001-08-28 | Taiwan Semiconductor Manufacturing Company | Self-passivation procedure for a copper damascene structure |
US6150261A (en) * | 1999-05-25 | 2000-11-21 | United Microelectronics Corp. | Method of fabricating semiconductor device for preventing antenna effect |
US6046108A (en) * | 1999-06-25 | 2000-04-04 | Taiwan Semiconductor Manufacturing Company | Method for selective growth of Cu3 Ge or Cu5 Si for passivation of damascene copper structures and device manufactured thereby |
US7060605B2 (en) | 1999-06-30 | 2006-06-13 | Lam Research Corporation | Methods for making dual-damascene dielectric structures |
US6909190B2 (en) | 1999-06-30 | 2005-06-21 | Lam Research Corporation | Dual-damascene dielectric structures |
US20010009803A1 (en) * | 1999-06-30 | 2001-07-26 | Uglow Jay E. | Methods for making dual-damascene dielectric structures |
US6251770B1 (en) * | 1999-06-30 | 2001-06-26 | Lam Research Corp. | Dual-damascene dielectric structures and methods for making the same |
US6191025B1 (en) * | 1999-07-08 | 2001-02-20 | Taiwan Semiconductor Manufacturing Company | Method of fabricating a damascene structure for copper medullization |
US6551919B2 (en) * | 1999-07-13 | 2003-04-22 | Motorola, Inc. | Method for forming a dual inlaid copper interconnect structure |
US6130157A (en) * | 1999-07-16 | 2000-10-10 | Taiwan Semiconductor Manufacturing Company | Method to form an encapsulation layer over copper interconnects |
US6224737B1 (en) * | 1999-08-19 | 2001-05-01 | Taiwan Semiconductor Manufacturing Company | Method for improvement of gap filling capability of electrochemical deposition of copper |
US6080656A (en) * | 1999-09-01 | 2000-06-27 | Taiwan Semiconductor Manufacturing Company | Method for forming a self-aligned copper structure with improved planarity |
US6740580B1 (en) | 1999-09-03 | 2004-05-25 | Chartered Semiconductor Manufacturing Ltd. | Method to form copper interconnects by adding an aluminum layer to the copper diffusion barrier |
US6716746B1 (en) * | 1999-09-16 | 2004-04-06 | Samsung Electronics Co., Ltd. | Semiconductor device having self-aligned contact and method of fabricating the same |
US6040243A (en) * | 1999-09-20 | 2000-03-21 | Chartered Semiconductor Manufacturing Ltd. | Method to form copper damascene interconnects using a reverse barrier metal scheme to eliminate copper diffusion |
KR100345528B1 (en) * | 1999-09-29 | 2002-07-26 | 인터내셔널 비지네스 머신즈 코포레이션 | Dual damascene flowable oxide insulation structure and metallic barrier |
US6399489B1 (en) | 1999-11-01 | 2002-06-04 | Applied Materials, Inc. | Barrier layer deposition using HDP-CVD |
US6713390B2 (en) | 1999-11-01 | 2004-03-30 | Applied Materials Inc. | Barrier layer deposition using HDP-CVD |
US6425987B1 (en) * | 1999-11-25 | 2002-07-30 | National Science Council | Technique for deposition of multilayer interference thin films using silicon as the only coating material |
US6387800B1 (en) | 1999-12-20 | 2002-05-14 | Taiwan Semiconductor Manufacturing Company | Method of forming barrier and seed layers for electrochemical deposition of copper |
US6492268B1 (en) * | 1999-12-22 | 2002-12-10 | Hyundai Electronics Industries Co., Ltd. | Method of forming a copper wiring in a semiconductor device |
US6395642B1 (en) | 1999-12-28 | 2002-05-28 | Taiwan Semiconductor Manufacturing Company | Method to improve copper process integration |
US6197681B1 (en) * | 1999-12-31 | 2001-03-06 | United Microelectronics Corp. | Forming copper interconnects in dielectric materials with low constant dielectrics |
US7535103B2 (en) | 2000-01-18 | 2009-05-19 | Micron Technology, Inc. | Structures and methods to enhance copper metallization |
US7394157B2 (en) | 2000-01-18 | 2008-07-01 | Micron Technology, Inc. | Integrated circuit and seed layers |
US20020109233A1 (en) * | 2000-01-18 | 2002-08-15 | Micron Technology, Inc. | Process for providing seed layers for integrated circuit metallurgy |
US7368378B2 (en) | 2000-01-18 | 2008-05-06 | Micron Technology, Inc. | Methods for making integrated-circuit wiring from copper, silver, gold, and other metals |
US7745934B2 (en) | 2000-01-18 | 2010-06-29 | Micron Technology, Inc. | Integrated circuit and seed layers |
US7105914B2 (en) * | 2000-01-18 | 2006-09-12 | Micron Technology, Inc. | Integrated circuit and seed layers |
US7378737B2 (en) | 2000-01-18 | 2008-05-27 | Micron Technology, Inc. | Structures and methods to enhance copper metallization |
US6756298B2 (en) | 2000-01-18 | 2004-06-29 | Micron Technology, Inc. | Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals |
US7301190B2 (en) | 2000-01-18 | 2007-11-27 | Micron Technology, Inc. | Structures and methods to enhance copper metallization |
US7285196B2 (en) | 2000-01-18 | 2007-10-23 | Micron Technology, Inc. | Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals |
US7262130B1 (en) | 2000-01-18 | 2007-08-28 | Micron Technology, Inc. | Methods for making integrated-circuit wiring from copper, silver, gold, and other metals |
US7670469B2 (en) | 2000-01-18 | 2010-03-02 | Micron Technology, Inc. | Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals |
US7253521B2 (en) | 2000-01-18 | 2007-08-07 | Micron Technology, Inc. | Methods for making integrated-circuit wiring from copper, silver, gold, and other metals |
US6743716B2 (en) | 2000-01-18 | 2004-06-01 | Micron Technology, Inc. | Structures and methods to enhance copper metallization |
US8779596B2 (en) | 2000-01-18 | 2014-07-15 | Micron Technology, Inc. | Structures and methods to enhance copper metallization |
US6372632B1 (en) | 2000-01-24 | 2002-04-16 | Taiwan Semiconductor Manufacturing Company | Method to eliminate dishing of copper interconnects by the use of a sacrificial oxide layer |
US6528419B1 (en) | 2000-02-14 | 2003-03-04 | Stmicroelectronics S.A. | Process of fabricating an integrated circuit |
EP1146550A2 (en) * | 2000-02-14 | 2001-10-17 | STMicroelectronics SA | Method for making interconnections in an integrated circuit |
EP1146550A3 (en) * | 2000-02-14 | 2002-01-16 | STMicroelectronics S.A. | Method for making interconnections in an integrated circuit |
FR2805084A1 (en) * | 2000-02-14 | 2001-08-17 | St Microelectronics Sa | Metal track production for integrated circuits comprises incorporation of titanium layer to prevent diffusion of silicon into copper in metal track |
US6350364B1 (en) * | 2000-02-18 | 2002-02-26 | Taiwan Semiconductor Manufacturing Company | Method for improvement of planarity of electroplated copper |
US6836400B2 (en) * | 2000-02-24 | 2004-12-28 | Newport Fab, Llc | Structures based on ceramic tantalum nitride |
US6284657B1 (en) * | 2000-02-25 | 2001-09-04 | Chartered Semiconductor Manufacturing Ltd. | Non-metallic barrier formation for copper damascene type interconnects |
US6368953B1 (en) * | 2000-05-09 | 2002-04-09 | International Business Machines Corporation | Encapsulated metal structures for semiconductor devices and MIM capacitors including the same |
US6391783B1 (en) | 2000-07-13 | 2002-05-21 | Chartered Semiconductor Manufacturing Ltd. | Method to thin down copper barriers in deep submicron geometries by using alkaline earth element, barrier additives, or self assembly technique |
US6429117B1 (en) | 2000-07-19 | 2002-08-06 | Chartered Semiconductor Manufacturing Ltd. | Method to create copper traps by modifying treatment on the dielectrics surface |
US6358842B1 (en) * | 2000-08-07 | 2002-03-19 | Chartered Semiconductor Manufacturing Ltd. | Method to form damascene interconnects with sidewall passivation to protect organic dielectrics |
US20060154483A1 (en) * | 2000-08-22 | 2006-07-13 | Micron Technology, Inc. | Method of providing a structure using self-aligned features |
US7109112B2 (en) | 2000-08-22 | 2006-09-19 | Micron Technology, Inc. | Method of providing a structure using self-aligned features |
US20040219738A1 (en) * | 2000-08-22 | 2004-11-04 | Dinesh Chopra | Method of providing a structure using self-aligned features |
WO2002017388A2 (en) * | 2000-08-23 | 2002-02-28 | Applied Materials, Inc. | Method of improving the adhesion of copper |
WO2002017388A3 (en) * | 2000-08-23 | 2002-10-10 | Applied Materials Inc | Method of improving the adhesion of copper |
US6531398B1 (en) | 2000-10-30 | 2003-03-11 | Applied Materials, Inc. | Method of depositing organosillicate layers |
EP1217648A2 (en) * | 2000-12-19 | 2002-06-26 | Canon Sales Co., Inc. | Method of manufacturing an interlayer dielectric layer with low dielectric constant |
US6852651B2 (en) | 2000-12-19 | 2005-02-08 | Canon Sales Co., Inc. | Semiconductor device and method of manufacturing the same |
US20020113316A1 (en) * | 2000-12-19 | 2002-08-22 | Conon Sales Co., Ltd. | Semiconductor device and method of manufacturing the same |
EP1217648A3 (en) * | 2000-12-19 | 2003-12-03 | Canon Sales Co., Inc. | Method of manufacturing an interlayer dielectric layer with low dielectric constant |
KR100376259B1 (en) * | 2000-12-27 | 2003-03-17 | 주식회사 하이닉스반도체 | Method of forming a copper wiring in a semiconductor device |
US7172497B2 (en) * | 2001-01-05 | 2007-02-06 | Asm Nutool, Inc. | Fabrication of semiconductor interconnect structures |
US20070128851A1 (en) * | 2001-01-05 | 2007-06-07 | Novellus Systems, Inc. | Fabrication of semiconductor interconnect structures |
US20030032373A1 (en) * | 2001-01-05 | 2003-02-13 | Basol Bulent M. | Fabrication of semiconductor interconnect structures |
US7200460B2 (en) | 2001-02-23 | 2007-04-03 | Applied Materials, Inc. | Method of depositing low dielectric constant silicon carbide layers |
US20030148223A1 (en) * | 2001-02-23 | 2003-08-07 | Applied Materials, Inc. | Method of depositing low dielectric constant silicon carbide layers |
US20020129972A1 (en) * | 2001-03-13 | 2002-09-19 | International Business Machines Corporation | Structure having laser ablated Features and method of fabricating |
US20040064939A1 (en) * | 2001-03-13 | 2004-04-08 | International Business Machines Corporation | Structure having laser ablated features and method of fabricating |
US6730857B2 (en) | 2001-03-13 | 2004-05-04 | International Business Machines Corporation | Structure having laser ablated features and method of fabricating |
US6919514B2 (en) | 2001-03-13 | 2005-07-19 | International Business Machines Corporation | Structure having laser ablated features and method of fabricating |
US7605468B2 (en) | 2001-03-15 | 2009-10-20 | Mosaid Technologies Incorporated | Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow |
US6696360B2 (en) | 2001-03-15 | 2004-02-24 | Micron Technology, Inc. | Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow |
US7888261B2 (en) | 2001-03-15 | 2011-02-15 | Mosaid Technologies, Incorporated | Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow |
US20110111589A1 (en) * | 2001-03-15 | 2011-05-12 | Mosaid Technologies, Incorporated | Barrier-metal-free copper camascence technology using atomic hydrogen enhanced reflow |
US8211792B2 (en) | 2001-03-15 | 2012-07-03 | Mosaid Technologies Incorporated | Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow |
US20060289993A1 (en) * | 2001-03-15 | 2006-12-28 | Micron Technology, Inc. | Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow |
US8513112B2 (en) | 2001-03-15 | 2013-08-20 | Mosaid Technologies, Incorporated | Barrier-metal-free copper damascene technology using enhanced reflow |
US6762500B2 (en) | 2001-03-15 | 2004-07-13 | Micron Technology, Inc. | Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow |
US7186643B2 (en) | 2001-03-15 | 2007-03-06 | Micron Technology, Inc. | Barrier-metal-free copper damascene technology using atomic hydrogen enhanced reflow |
US20030232494A1 (en) * | 2001-03-23 | 2003-12-18 | Adams Charlotte D. | Dual damascene copper interconnect to a damascene tungsten wiring level |
US7230336B2 (en) * | 2001-03-23 | 2007-06-12 | International Business Machines Corporation | Dual damascene copper interconnect to a damascene tungsten wiring level |
US6566242B1 (en) * | 2001-03-23 | 2003-05-20 | International Business Machines Corporation | Dual damascene copper interconnect to a damascene tungsten wiring level |
US20070035025A1 (en) * | 2001-03-27 | 2007-02-15 | Advanced Micro Devices, Inc. | Damascene processing using dielectric barrier films |
WO2002078060A3 (en) * | 2001-03-27 | 2003-02-06 | Advanced Micro Devices Inc | Damascene processing using dielectric barrier films |
US7132363B2 (en) | 2001-03-27 | 2006-11-07 | Advanced Micro Devices, Inc. | Stabilizing fluorine etching of low-k materials |
CN100449730C (en) * | 2001-03-27 | 2009-01-07 | 先进微装置公司 | Damascene processing using dielectric barrier films |
WO2002078060A2 (en) * | 2001-03-27 | 2002-10-03 | Advanced Micro Devices, Inc. | Damascene processing using dielectric barrier films |
US6750141B2 (en) | 2001-03-28 | 2004-06-15 | Applied Materials Inc. | Silicon carbide cap layers for low dielectric constant silicon oxide layers |
US6709721B2 (en) | 2001-03-28 | 2004-03-23 | Applied Materials Inc. | Purge heater design and process development for the improvement of low k film properties |
US6528412B1 (en) * | 2001-04-30 | 2003-03-04 | Advanced Micro Devices, Inc. | Depositing an adhesion skin layer and a conformal seed layer to fill an interconnect opening |
US20050020079A1 (en) * | 2001-05-23 | 2005-01-27 | International Business Machines Corporation | Structure having flush circuit features and method of making |
US7098136B2 (en) * | 2001-05-23 | 2006-08-29 | International Business Machines Corporation | Structure having flush circuit features and method of making |
US20020177006A1 (en) * | 2001-05-23 | 2002-11-28 | International Business Machines Corporation | Structure having flush circuitry features and method of making |
US6815709B2 (en) | 2001-05-23 | 2004-11-09 | International Business Machines Corporation | Structure having flush circuitry features and method of making |
US6979903B1 (en) * | 2001-06-04 | 2005-12-27 | Advanced Micro Devices, Inc. | Integrated circuit with dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers |
US6841228B2 (en) | 2001-06-14 | 2005-01-11 | International Business Machines Corporation | Structure having embedded flush circuitry features and method of fabricating |
US20040081810A1 (en) * | 2001-06-14 | 2004-04-29 | International Business Machines | Structure having embedded flush circuitry features and method of fabricating |
US6663786B2 (en) | 2001-06-14 | 2003-12-16 | International Business Machines Corporation | Structure having embedded flush circuitry features and method of fabricating |
US20050153572A1 (en) * | 2001-06-18 | 2005-07-14 | Applied Materials, Inc. | CVD plasma assisted lower dielectric constant sicoh film |
US20030104708A1 (en) * | 2001-06-18 | 2003-06-05 | Applied Materials, Inc. | CVD plasma assisted lower dielectric constant sicoh film |
US6943127B2 (en) | 2001-06-18 | 2005-09-13 | Applied Materials Inc. | CVD plasma assisted lower dielectric constant SICOH film |
US7153787B2 (en) | 2001-06-18 | 2006-12-26 | Applied Materials, Inc. | CVD plasma assisted lower dielectric constant SICOH film |
US20030049388A1 (en) * | 2001-09-10 | 2003-03-13 | Seon-Mee Cho | Silicon carbide deposited by high density plasma chemical-vapor deposition with bias |
US6926926B2 (en) | 2001-09-10 | 2005-08-09 | Applied Materials, Inc. | Silicon carbide deposited by high density plasma chemical-vapor deposition with bias |
US20060205206A1 (en) * | 2001-10-11 | 2006-09-14 | Applied Materials, Inc. | Method of eliminating photoresist poisoning in damascene applications |
US20040106278A1 (en) * | 2001-10-11 | 2004-06-03 | Applied Materials, Inc. | Method of eliminating photoresist poisoning in damascene applications |
US6656837B2 (en) | 2001-10-11 | 2003-12-02 | Applied Materials, Inc. | Method of eliminating photoresist poisoning in damascene applications |
US7034409B2 (en) | 2001-10-11 | 2006-04-25 | Applied Materials Inc. | Method of eliminating photoresist poisoning in damascene applications |
US20030082901A1 (en) * | 2001-10-31 | 2003-05-01 | Thomas Werner | Void formation monitoring in a damascene process |
US6964874B2 (en) * | 2001-10-31 | 2005-11-15 | Advanced Micro Devices, Inc. | Void formation monitoring in a damascene process |
US6703308B1 (en) | 2001-11-26 | 2004-03-09 | Advanced Micro Devices, Inc. | Method of inserting alloy elements to reduce copper diffusion and bulk diffusion |
US6703307B2 (en) | 2001-11-26 | 2004-03-09 | Advanced Micro Devices, Inc. | Method of implantation after copper seed deposition |
US6835655B1 (en) * | 2001-11-26 | 2004-12-28 | Advanced Micro Devices, Inc. | Method of implanting copper barrier material to improve electrical performance |
US7696092B2 (en) | 2001-11-26 | 2010-04-13 | Globalfoundries Inc. | Method of using ternary copper alloy to obtain a low resistance and large grain size interconnect |
US6633392B1 (en) | 2002-01-17 | 2003-10-14 | Advanced Micro Devices, Inc. | X-ray reflectance system to determine suitability of SiON ARC layer |
US6936309B2 (en) | 2002-04-02 | 2005-08-30 | Applied Materials, Inc. | Hardness improvement of silicon carboxy films |
US20030194496A1 (en) * | 2002-04-11 | 2003-10-16 | Applied Materials, Inc. | Methods for depositing dielectric material |
US20030194495A1 (en) * | 2002-04-11 | 2003-10-16 | Applied Materials, Inc. | Crosslink cyclo-siloxane compound with linear bridging group to form ultra low k dielectric |
US20030211244A1 (en) * | 2002-04-11 | 2003-11-13 | Applied Materials, Inc. | Reacting an organosilicon compound with an oxidizing gas to form an ultra low k dielectric |
US6815373B2 (en) | 2002-04-16 | 2004-11-09 | Applied Materials Inc. | Use of cyclic siloxanes for hardness improvement of low k dielectric films |
US20040234688A1 (en) * | 2002-04-16 | 2004-11-25 | Vinita Singh | Use of cyclic siloxanes for hardness improvement |
US20030194880A1 (en) * | 2002-04-16 | 2003-10-16 | Applied Materials, Inc. | Use of cyclic siloxanes for hardness improvement |
US20030206337A1 (en) * | 2002-05-06 | 2003-11-06 | Eastman Kodak Company | Exposure apparatus for irradiating a sensitized substrate |
CN100373560C (en) * | 2002-05-13 | 2008-03-05 | 东京毅力科创株式会社 | Substrate processing method |
US7226874B2 (en) * | 2002-05-13 | 2007-06-05 | Tokyo Electron Limited | Substrate processing method |
US20050153570A1 (en) * | 2002-05-13 | 2005-07-14 | Tokyo Electron Limited | Substrate processing method |
US6861349B1 (en) | 2002-05-15 | 2005-03-01 | Advanced Micro Devices, Inc. | Method of forming an adhesion layer with an element reactive with a barrier layer |
US7105460B2 (en) | 2002-07-11 | 2006-09-12 | Applied Materials | Nitrogen-free dielectric anti-reflective coating and hardmask |
US20040009676A1 (en) * | 2002-07-11 | 2004-01-15 | Applied Materials, Inc. | Nitrogen-free dielectric anti-reflective coating and hardmask |
US20040214446A1 (en) * | 2002-07-11 | 2004-10-28 | Applied Materials, Inc. | Nitrogen-free dielectric anti-reflective coating and hardmask |
US6927178B2 (en) | 2002-07-11 | 2005-08-09 | Applied Materials, Inc. | Nitrogen-free dielectric anti-reflective coating and hardmask |
US20040063307A1 (en) * | 2002-09-30 | 2004-04-01 | Subramanian Karthikeyan | Method to avoid copper contamination of a via or dual damascene structure |
US7005375B2 (en) * | 2002-09-30 | 2006-02-28 | Agere Systems Inc. | Method to avoid copper contamination of a via or dual damascene structure |
US20040130035A1 (en) * | 2003-01-07 | 2004-07-08 | Zhen-Cheng Wu | Method of forming copper interconnects |
US7056826B2 (en) * | 2003-01-07 | 2006-06-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming copper interconnects |
US6897163B2 (en) | 2003-01-31 | 2005-05-24 | Applied Materials, Inc. | Method for depositing a low dielectric constant film |
US20040152338A1 (en) * | 2003-01-31 | 2004-08-05 | Applied Materials, Inc. | Method for depositing a low dielectric constant film |
US20080026566A1 (en) * | 2003-06-23 | 2008-01-31 | International Business Machines Corporation | Dual damascene interconnect structures having different materials for line and via conductors |
US20040262764A1 (en) * | 2003-06-23 | 2004-12-30 | International Business Machines Corporation | Dual damascene interconnect structures having different materials for line and via conductors |
US6958540B2 (en) * | 2003-06-23 | 2005-10-25 | International Business Machines Corporation | Dual damascene interconnect structures having different materials for line and via conductors |
US7704876B2 (en) | 2003-06-23 | 2010-04-27 | International Business Machines Corporation | Dual damascene interconnect structures having different materials for line and via conductors |
KR100772602B1 (en) * | 2003-06-23 | 2007-11-02 | 인터내셔널 비지네스 머신즈 코포레이션 | Dual damascene interconnect structures having different materials for line and via conductors |
US20050245068A1 (en) * | 2003-06-23 | 2005-11-03 | International Business Machines Corporation | Dual damascene interconnect structures having different materials for line and via conductors |
US7300867B2 (en) | 2003-06-23 | 2007-11-27 | International Business Machines Corporation | Dual damascene interconnect structures having different materials for line and via conductors |
US20060131754A1 (en) * | 2003-07-18 | 2006-06-22 | Nec Corporation | Semiconductor device having trench interconnection and manufacturing method of semiconductor device |
US7622808B2 (en) * | 2003-07-18 | 2009-11-24 | Nec Corporation | Semiconductor device and having trench interconnection |
US7220665B2 (en) | 2003-08-05 | 2007-05-22 | Micron Technology, Inc. | H2 plasma treatment |
US7504674B2 (en) | 2003-08-05 | 2009-03-17 | Micron Technology, Inc. | Electronic apparatus having a core conductive structure within an insulating layer |
US20050085073A1 (en) * | 2003-10-16 | 2005-04-21 | Advanced Micro Devices, Inc. | Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper deposition |
US7169706B2 (en) | 2003-10-16 | 2007-01-30 | Advanced Micro Devices, Inc. | Method of using an adhesion precursor layer for chemical vapor deposition (CVD) copper deposition |
CN101091243B (en) * | 2003-10-21 | 2010-05-26 | 齐普特洛尼克斯公司 | Single mask via method and device |
US20080150153A1 (en) * | 2003-10-21 | 2008-06-26 | Ziptronix, Inc. | Single mask via method and device |
US7341938B2 (en) * | 2003-10-21 | 2008-03-11 | Ziptronix, Inc. | Single mask via method and device |
US20050181542A1 (en) * | 2003-10-21 | 2005-08-18 | Ziptronix, Inc. | Single mask via method and device |
US7714446B2 (en) | 2003-10-21 | 2010-05-11 | Ziptronix, Inc. | Single mask via method and device |
US7309651B2 (en) * | 2003-10-30 | 2007-12-18 | Texas Instruments Incorporated | Method for improving reliability of copper interconnects |
US20050095843A1 (en) * | 2003-10-30 | 2005-05-05 | West Jeffrey A. | Method for improving reliability of copper interconnects |
US7589417B2 (en) * | 2004-02-12 | 2009-09-15 | Intel Corporation | Microelectronic assembly having thermoelectric elements to cool a die and a method of making the same |
US20050178423A1 (en) * | 2004-02-12 | 2005-08-18 | Shriram Ramanathan | Microelectronic assembly having thermoelectric elements to cool a die and a method of making the same |
US7329600B2 (en) * | 2004-04-02 | 2008-02-12 | International Business Machines Corporation | Low dielectric semiconductor device and process for fabricating the same |
CN1327509C (en) * | 2004-04-02 | 2007-07-18 | 国际商业机器公司 | Low dielectric semiconductor device and process for fabricating the same |
US20050227480A1 (en) * | 2004-04-02 | 2005-10-13 | International Business Machines Corporation (Ibm) | Low dielectric semiconductor device and process for fabricating the same |
US20050250321A1 (en) * | 2004-05-06 | 2005-11-10 | Eui-Seong Hwang | Method for fabricating semiconductor device having diffusion barrier layer |
US20050272258A1 (en) * | 2004-06-04 | 2005-12-08 | Toshiyuki Morita | Method of manufacturing a semiconductor device and semiconductor device |
US7288205B2 (en) | 2004-07-09 | 2007-10-30 | Applied Materials, Inc. | Hermetic low dielectric constant layer for barrier applications |
US20060024954A1 (en) * | 2004-08-02 | 2006-02-02 | Zhen-Cheng Wu | Copper damascene barrier and capping layer |
US7915162B2 (en) | 2005-02-24 | 2011-03-29 | International Business Machines Corporation | Method of forming damascene filament wires |
US20070278624A1 (en) * | 2005-02-24 | 2007-12-06 | Anderson Brent A | Damascene filament wire structure |
US20080096384A1 (en) * | 2005-02-24 | 2008-04-24 | Anderson Brent A | Method of forming damascene filament wires |
US7846833B2 (en) * | 2005-08-30 | 2010-12-07 | Fujitsu Limited | Manufacture method for semiconductor device suitable for forming wirings by damascene method and semiconductor device |
US20100178762A1 (en) * | 2005-08-30 | 2010-07-15 | Fujitsu Limited | Manufacture method for semiconductor device suitable for forming wirings by damascene method and semiconductor device |
US8072075B2 (en) | 2006-09-04 | 2011-12-06 | Nicolas Jourdan | CuSiN/SiN diffusion barrier for copper in integrated-circuit devices |
US20090273085A1 (en) * | 2006-09-04 | 2009-11-05 | Nicolas Jourdan | CuSiN/SiN DIFFUSION BARRIER FOR COPPER IN INTEGRATED-CIRCUIT DEVICES |
WO2008028850A1 (en) * | 2006-09-04 | 2008-03-13 | Koninklijke Philips Electronics N.V. | CuSiN/SiN DIFFUSION BARRIER FOR COPPER IN INTEGRATED-CIRCUIT DEVICES |
US8300127B2 (en) * | 2008-01-21 | 2012-10-30 | Sony Corporation | Solid-state imaging device, method of fabricating solid-state imaging device, and camera |
US20090185060A1 (en) * | 2008-01-21 | 2009-07-23 | Sony Corporation | Solid-state imaging device, method of fabricating solid-state imaging device, and camera |
US8039964B2 (en) * | 2008-02-27 | 2011-10-18 | International Business Machines Corporation | Fluorine depleted adhesion layer for metal interconnect structure |
US8765597B2 (en) | 2008-02-27 | 2014-07-01 | International Business Machines Corporation | Fluorine depleted adhesion layer for metal interconnect structure |
US20110281432A1 (en) * | 2008-02-27 | 2011-11-17 | International Business Machines Corporation | Fluorine depleted adhesion layer for metal interconnect structure |
US8563423B2 (en) * | 2008-02-27 | 2013-10-22 | International Business Machines Corporation | Fluorine depleted adhesion layer for metal interconnect structure |
US8871636B2 (en) * | 2008-02-27 | 2014-10-28 | International Business Machines Corporation | Fluorine depleted adhesion layer for metal interconnect structure |
US20090212439A1 (en) * | 2008-02-27 | 2009-08-27 | International Business Machines Corporation | Fluorine depleted adhesion layer for metal interconnect structure |
CN102468430B (en) * | 2010-11-05 | 2015-06-10 | 中芯国际集成电路制造(北京)有限公司 | Implementation method for improving adhesiveness of phase change material |
CN102468430A (en) * | 2010-11-05 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | Implementation method for improving adhesiveness of phase change material |
US8461043B2 (en) * | 2011-04-11 | 2013-06-11 | Micron Technology, Inc. | Barrier layer for integrated circuit contacts |
US8810033B2 (en) | 2011-04-11 | 2014-08-19 | Micron Technology, Inc. | Barrier layer for integrated circuit contacts |
TWI483407B (en) * | 2011-06-17 | 2015-05-01 | Globalfoundries Us Inc | Integrated circuits including barrier polish stop layers and methods for the manufacture thereof |
US9209078B2 (en) | 2011-07-28 | 2015-12-08 | Freescale Semiconductor, Inc. | Method of making a die with recessed aluminum die pads |
US8722530B2 (en) * | 2011-07-28 | 2014-05-13 | Freescale Semiconductor, Inc. | Method of making a die with recessed aluminum die pads |
US20130029485A1 (en) * | 2011-07-28 | 2013-01-31 | Spencer Gregory S | Method of making a die with recessed alumium die pads |
US20140134848A1 (en) * | 2012-11-09 | 2014-05-15 | Tokyo Electron Limited | Plasma etching method and plasma etching apparatus |
US9330935B2 (en) * | 2012-11-09 | 2016-05-03 | Tokyo Electron Limited | Plasma etching method and plasma etching apparatus |
US9425093B2 (en) * | 2014-12-05 | 2016-08-23 | Tokyo Electron Limited | Copper wiring forming method, film forming system, and storage medium |
US20180061702A1 (en) * | 2016-08-30 | 2018-03-01 | International Business Machines Corporation | Interconnect structure |
US9953864B2 (en) * | 2016-08-30 | 2018-04-24 | International Business Machines Corporation | Interconnect structure |
US20180151420A1 (en) * | 2016-08-30 | 2018-05-31 | International Business Machines Corporation | Interconnect structure |
US10128147B2 (en) * | 2016-08-30 | 2018-11-13 | International Business Machines Corporation | Interconnect structure |
WO2019067579A1 (en) * | 2017-09-27 | 2019-04-04 | Invensas Corporation | Interconnect structures and methods for forming same |
US11195748B2 (en) | 2017-09-27 | 2021-12-07 | Invensas Corporation | Interconnect structures and methods for forming same |
US11444039B2 (en) * | 2020-05-29 | 2022-09-13 | Sandisk Technologies Llc | Semiconductor die including diffusion barrier layers embedding bonding pads and methods of forming the same |
US11450624B2 (en) * | 2020-05-29 | 2022-09-20 | Sandisk Technologies Llc | Semiconductor die including diffusion barrier layers embedding bonding pads and methods of forming the same |
Also Published As
Publication number | Publication date |
---|---|
KR19990013826A (en) | 1999-02-25 |
KR100505513B1 (en) | 2005-10-25 |
JPH1140671A (en) | 1999-02-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5821168A (en) | Process for forming a semiconductor device | |
US7265038B2 (en) | Method for forming a multi-layer seed layer for improved Cu ECP | |
US6949461B2 (en) | Method for depositing a metal layer on a semiconductor interconnect structure | |
US6797608B1 (en) | Method of forming multilayer diffusion barrier for copper interconnections | |
US6958291B2 (en) | Interconnect with composite barrier layers and method for fabricating the same | |
US5893752A (en) | Process for forming a semiconductor device | |
US6716753B1 (en) | Method for forming a self-passivated copper interconnect structure | |
US7030023B2 (en) | Method for simultaneous degas and baking in copper damascene process | |
US8026605B2 (en) | Interconnect structure and method of manufacturing a damascene structure | |
US5918149A (en) | Deposition of a conductor in a via hole or trench | |
US5850102A (en) | Semiconductor device having a second insulating layer which includes carbon or fluorine at a density lower than a first insulating layer | |
US5677244A (en) | Method of alloying an interconnect structure with copper | |
US7176571B2 (en) | Nitride barrier layer to prevent metal (Cu) leakage issue in a dual damascene structure | |
US6074942A (en) | Method for forming a dual damascene contact and interconnect | |
US20110256715A1 (en) | Barrier layer for copper interconnect | |
US20070197023A1 (en) | Entire encapsulation of Cu interconnects using self-aligned CuSiN film | |
EP1570517B1 (en) | A method for depositing a metal layer on a semiconductor interconnect structure having a capping layer | |
US6534404B1 (en) | Method of depositing diffusion barrier for copper interconnect in integrated circuit | |
US20040175926A1 (en) | Method for manufacturing a semiconductor component having a barrier-lined opening | |
US6048788A (en) | Method of fabricating metal plug | |
US20060281299A1 (en) | Method of fabricating silicon carbide-capped copper damascene interconnect | |
JP2005005383A (en) | Semiconductor device and method of manufacturing the same | |
US6211072B1 (en) | CVD Tin Barrier process with improved contact resistance | |
US20060040490A1 (en) | Method of fabricating silicon carbide-capped copper damascene interconnect | |
US6943096B1 (en) | Semiconductor component and method of manufacture |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MOTOROLA, INC., ILLINOIS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:JAIN, AJAY;REEL/FRAME:008688/0742 Effective date: 19970702 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MOTOROLA, INC.;REEL/FRAME:015698/0657 Effective date: 20040404 Owner name: FREESCALE SEMICONDUCTOR, INC.,TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MOTOROLA, INC.;REEL/FRAME:015698/0657 Effective date: 20040404 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: CITIBANK, N.A. AS COLLATERAL AGENT, NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNORS:FREESCALE SEMICONDUCTOR, INC.;FREESCALE ACQUISITION CORPORATION;FREESCALE ACQUISITION HOLDINGS CORP.;AND OTHERS;REEL/FRAME:018855/0129 Effective date: 20061201 Owner name: CITIBANK, N.A. AS COLLATERAL AGENT,NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNORS:FREESCALE SEMICONDUCTOR, INC.;FREESCALE ACQUISITION CORPORATION;FREESCALE ACQUISITION HOLDINGS CORP.;AND OTHERS;REEL/FRAME:018855/0129 Effective date: 20061201 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: CITIBANK, N.A., AS COLLATERAL AGENT,NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:024397/0001 Effective date: 20100413 Owner name: CITIBANK, N.A., AS COLLATERAL AGENT, NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:024397/0001 Effective date: 20100413 |
|
AS | Assignment |
Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YOR Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:030633/0424 Effective date: 20130521 |
|
AS | Assignment |
Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YOR Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:031591/0266 Effective date: 20131101 |
|
AS | Assignment |
Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037354/0225 Effective date: 20151207 Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037356/0553 Effective date: 20151207 Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037356/0143 Effective date: 20151207 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:037486/0517 Effective date: 20151207 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:037518/0292 Effective date: 20151207 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: SUPPLEMENT TO THE SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:039138/0001 Effective date: 20160525 |
|
AS | Assignment |
Owner name: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040925/0001 Effective date: 20160912 Owner name: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC., NE Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040925/0001 Effective date: 20160912 |
|
AS | Assignment |
Owner name: NXP B.V., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040928/0001 Effective date: 20160622 |
|
AS | Assignment |
Owner name: NXP USA, INC., TEXAS Free format text: CHANGE OF NAME;ASSIGNOR:FREESCALE SEMICONDUCTOR INC.;REEL/FRAME:040652/0180 Effective date: 20161107 |
|
AS | Assignment |
Owner name: NXP USA, INC., TEXAS Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME;ASSIGNOR:FREESCALE SEMICONDUCTOR INC.;REEL/FRAME:041354/0148 Effective date: 20161107 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:041703/0536 Effective date: 20151207 |
|
AS | Assignment |
Owner name: SHENZHEN XINGUODU TECHNOLOGY CO., LTD., CHINA Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITYINTEREST IN PATENTS.;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:048734/0001 Effective date: 20190217 |
|
AS | Assignment |
Owner name: NXP B.V., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:050744/0097 Effective date: 20190903 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITYINTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:053547/0421 Effective date: 20151207 |
|
AS | Assignment |
Owner name: NXP B.V., NETHERLANDS Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVEAPPLICATION 11759915 AND REPLACE IT WITH APPLICATION11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITYINTEREST;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:052915/0001 Effective date: 20160622 |
|
AS | Assignment |
Owner name: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC., NETHERLANDS Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVEAPPLICATION 11759915 AND REPLACE IT WITH APPLICATION11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITYINTEREST;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:052917/0001 Effective date: 20160912 |