US5875482A - Method and apparatus for programmable chip select negation in a data processing system - Google Patents
Method and apparatus for programmable chip select negation in a data processing system Download PDFInfo
- Publication number
- US5875482A US5875482A US08/660,620 US66062096A US5875482A US 5875482 A US5875482 A US 5875482A US 66062096 A US66062096 A US 66062096A US 5875482 A US5875482 A US 5875482A
- Authority
- US
- United States
- Prior art keywords
- chip select
- signal
- bus cycle
- bus
- negation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000012545 processing Methods 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims abstract description 16
- 230000015654 memory Effects 0.000 claims description 37
- 230000004044 response Effects 0.000 claims description 12
- 230000005055 memory storage Effects 0.000 claims 2
- 230000007704 transition Effects 0.000 description 19
- 238000012546 transfer Methods 0.000 description 17
- 238000010586 diagram Methods 0.000 description 16
- 230000006870 function Effects 0.000 description 10
- 230000001360 synchronised effect Effects 0.000 description 7
- 230000007246 mechanism Effects 0.000 description 6
- 238000013461 design Methods 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- 230000004913 activation Effects 0.000 description 3
- 230000003213 activating effect Effects 0.000 description 2
- 102100040605 1,2-dihydroxy-3-keto-5-methylthiopentene dioxygenase Human genes 0.000 description 1
- 101000966793 Homo sapiens 1,2-dihydroxy-3-keto-5-methylthiopentene dioxygenase Proteins 0.000 description 1
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000009849 deactivation Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 230000002779 inactivation Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 238000010200 validation analysis Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
- G06F12/0879—Burst mode
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
Definitions
- the present invention relates in general to a data processing system, and more particularly to a chip select logic circuits for integrated circuit microprocessors and microcomputers.
- Integrated circuit microprocessors must, in many cases, be connected with other integrated circuit devices in order to provide certain functions.
- a microprocessor uses internal chip select circuitry to interface with other integrated circuits, often significantly reducing the cost of the system design and improving performance.
- a major concern associated with the integration of chip select logic onto a microprocessor integrated circuit involves the provision of sufficient flexibility to the user.
- the use of "glue" logic is extremely flexible, since the system designer has wide latitude in the placement of each external device with the microprocessor's memory map and the timing and other characteristics of the chip select signals themselves. This flexibility is very useful, since the variety of possible system designs and chip select requirements for particular peripheral devices is great. Providing sufficient flexibility in an integrated chip select unit while constraining the size of the unit within reasonable limits is quite difficult.
- Peripheral devices have a variety of characteristics and requirements.
- One type of peripheral device operates synchronously with the microprocessor by use of both chip enable or chip select (CE) signals and output enable (OE) signals.
- Chip select signals are used to indicate the particular device to access, and output enable signals are used to synchronize the access. Device access therefore requires additional bus cycles to accomodate synchronization.
- Other devices have slow bus interface logic and require additional time after negation of CE, to allow for synchronout OE response and any number of functions particular to each device type. It is desireable to increase the flexibility of chip select signal timing in a data processing system to allow efficient system design for a broad range of peripheral devices.
- FIG. 1 illustrates in block diagram form a data processing system according to the present invention.
- FIG. 2 illustrates in block diagram form a first portion of the chip select circuit of FIG. 1.
- FIG. 3 illustrates a state diagram of the HPCE state machine of FIG. 2.
- FIG. 4 illustrates a state diagram of the BCS state machine of FIG. 2.
- FIG. 5 illustrates a timing diagram useful in understanding the operation of the first portion of the chip select circuit of FIG. 2.
- FIG. 6 illustrates in partial block form and partial logic diagram form the burst address generator of FIG. 2.
- FIG. 7 illustrates a block diagram of a second portion of the chip select circuit of FIG. 1.
- FIG. 8 illustrates a timing diagram useful in understanding the operation of the second portion of the chip select circuit of FIG. 2.
- a data processing system has a burst chip select module which addresses the competing interests of high speed memory access and low power consumption performance.
- the chip select circuit allows the user to decide on a power/performance ratio for a particular application.
- a high performance chip enable (HPCE) signal is functionally programmable to remain asserted for a predetermined number of bus cycles after the last valid device access based on an access duty cycle.
- the access duty cycle considers the potential number of accesses to a particular device. Asserting HPCE without matching on every access removes clock cycles associated with address decode and chip selection assertion and thus increases the speed of access to a device. In one example, HPCE remains asserted always, never, four cycles after a valid address match, or eight cycles after a valid match.
- a speculative access is begun without regard to any match criteria.
- the burst chip select initiates a memory access by asserting a load burst address (LBA) signal before receiving access validation.
- LBA load burst address
- the speculative access allows the device to prepare for access while the data processing system determines which device to access. Where the next access is to another device, the speculative access is aborted. There is no backing out steps required for the data processing system, as there was no actual access but merely device preparation.
- a chip select signal may be negated one bus cycle prior to assertion of a data acknowledge signal giving slower memories additional time to deactivate.
- the early negation of a chip select signal provides an efficient method of interface with devices having synchronous output enable requirements and provides additional bus decoupling time.
- a burst address generator (BAG) module has a programmable transfer mode applicable to both cache type architecture and pre-fetch type architecture.
- the dual application ability adds a level of flexibility to system design.
- the BAG terminates a bus cycle with a data acknowledge signal upon a programmable termination condition corresponding to the type of transfer.
- the termination condition may be a predetermined number of data transfers (e.g. 2 N ) or a physical boundary (e.g. 2.sup.(N) -1) and allows for access in the middle of a row of an external memory device.
- a burst counter determines when a cache line width limit is reached (i.e. cache line is full) and in response asserts a data acknowledge signal.
- the pre-fetch type architecture utilizes an address incrementor to detect the crossing of a row boundary and in response asserts a data acknowledge signal.
- the burst address is provided externally for devices without address increment capability.
- the present invention addresses the conflicting requirements of high speed access and low power consumption with a range of solutions and application.
- the present invention is a flexible approach to increasing the speed of device access while considering the process of system design.
- bus will be used to refer to a plurality of signals or conductors which may be used to transfer one or more various types of information, such as data, addresses, control, or status.
- assert and “negate” will be used when referring to the rendering of a signal, status bit, or similar apparatus into its logically true or logically false state, respectively. If the logically true state is a logic level one, the logically false state will be a logic level zero. And if the logically true state is a logic level zero, the logically false state will be a logic level one.
- FIG. 1 illustrates in block diagram form a data processing system 20.
- Data processing system 20 includes generally a data processor 22 connected via an external bus 24 to an asynchronous memory 26 and a synchronous memory 28.
- data processor 22 includes chip select circuitry which provides three chip select signals to asynchronous memory 26 and four chip select signals to synchronous memory 28 which will be described in greater detail hereinafter.
- Data processor 22 includes generally a central processing unit (CPU) 32 connected via an internal bus 36 to various other components of data processor 22. These other components include internal devices 34, an external bus interface (EBI) 38, and a chip select circuit 40.
- CPU 32 may use any conventional CPU architecture such as complex instruction set computer (CISC), reduced instruction set computer (RISC), digital signal processor (DSP), or any other known architecture.
- Internal devices 34 represent additional functions such as input/output peripherals, interrupt controllers, timers, and the like.
- EBI 38 is adapted to couple address and data signals conducted on internal bus 36 to external bus 24 for the transmission of data to and from asynchronous memory 26, synchronous memory 28, and other devices which may be connected to external bus 24.
- Chip select circuit 40 is an integrated chip select signal generator which is able to activate signals to drive actual physical memory chips.
- chip select circuit 40 provides three signals for interfacing to asynchronous memory 26, designated “CE1”, “OE1”, and “WE1". These signals form the chip enable, output enable, and write enable inputs, respectively, of conventional integrated circuit memories.
- Chip select circuit 40 also is able to access synchronous memory devices and in order to access these devices, provides four signals labeled "CE2", “LBA2”, “OE2”, and "WE2".
- chip select circuit 40 also provides signal LBA2 which serves as a synchronous cycle start signal.
- synchronous memory 28 will be a burstable memory device, in which case signal LBA2 will signal the start of a burst access.
- chip select circuit 40 will generally provide additional chip select signals which are omitted from FIG. 1 in order to ease discussion of the present invention.
- FIG. 2 illustrates in block diagram form a first portion 50 of chip select circuit 40 of FIG. 1.
- Portion 50 includes generally a base address register 51, an option register 52, a base address comparator 53, a burst state machine 54, and an option register 56.
- Base address register 51 stores bits representing a base address and size of the region associated with portion 50 and provides them as an input to base address comparator 53.
- Base address comparator 53 also has a second input for receiving critical bits of the address conducted on internal bus 36 labeled IADDR (23:15).
- Base address comparator 53 also has a control input for receiving a cycle start signal labeled "ICYS" from internal bus 36.
- base address comparator 53 compares IADDR (23:15) to the base address from base address register 51.
- Base address comparator 53 activates an output signal labeled "MATCH" to indicate that the address represented by critical address bits IADDR (23:15) are within the range defined in base address register 51.
- Option register 52 is a 16-bit register which includes several bits defining programmable characteristics associated with the region. The definition of these bits is illustrated in TABLE I below.
- the HPCE field allows users to selectively tailor their systems for an optimal tradeoff between lower power consumption and higher performance.
- the HPCE field determines the number of cycles which access another region for which burst state machine 54 keeps signal CE active. When the HPCE field is set to 00, burst state machine keeps signal CE active for four consecutive accesses to another region. At the start of a fifth consecutive access to another region, burst state machine deactivates signal CE. Also if an access to this region occurs before the start of the fifth access, then burst state machine 54 begins counting again from zero.
- An encoding of 01 is similar to an encoding of 00 except that burst state machine 54 keeps signal CE active for eight consecutive accesses to another region, and deactivates signal CE at the start of the ninth consecutive access to another region.
- An encoding of 10 causes burst state machine 54 to always inactivate signal CE at the end of a cycle, even if the next cycle is also to this region.
- an encoding of 11 cause burst state machine to keep signal CE active continuously after a first access to this region until the chip is reset.
- Burst state machine 54 is an access state machine which upon a match to the region associated with portion 50 generates chip select output signals. These chip select output signals include a chip enable signal labeled "HPCE”, a burst address advance signal labeled "BAA”, a burst write enable signal labeled “BWE”, a load burst address signal labeled "LBA”, an output enable signal labeled "BOE”.
- BCS state machine 70 outputs a bus clock signal labeled "BCLK”.
- burst state machine 54 is connected to internal bus 36 and receives address signals IADDR(5:1) therefrom.
- burst state machine 54 provides two signals to internal bus 36 labeled "DTACK” and "BTACK” which inform CPU 32 of the termination of an access cycle, or a transfer of each word of the burst, respectively.
- Burst state machine 54 includes two state machines which are important in understanding the present invention.
- the two state machines are the HPCE state machine 60 and the BCS state machine 70.
- HPCE state machine 60 is used to implement the chip enable mechanism according to the present invention wherein the chip enable signal may remain active between cycles to reduce access time and in which the user may selectively tradeoff power consumption and access time.
- BCS state machine 70 is used to provide signal LBA speculatively in response to the prediction made by HPCE state machine 60 of whether an access to the region is likely to be encountered based on its history.
- burst state machine 54 Additionally contained in burst state machine 54 is a burst address generator (BAG) 55 which provides signal DTACK to internal bus 36 and generates burst address values forming the LOWER ADDRESS presented to external bus 24.
- BAG burst address generator
- a second register, option register 56 is a 16-bit register which includes several bits defining programmable characteristics associated with burst chip select.
- Option register 56 provides burst chip select information to burst state machine 54 and to pin functional logic. The definition of these bits is illustrated in TABLE II below.
- BAG 55 terminates a bus cycle by asserting signal DTACK after a predetermined number of data transfers.
- the predetermined number is determined by the size of the memory device, the length of the cache line and the capabilities of the external and internal busses. The BAG decision and options are further discussed with reference to FIG. 6 below.
- FIG. 3 illustrates a state diagram of HPCE state machine 60 of FIG. 2.
- HPCE state machine 60 is capable of assuming one of two states 61 and 62. Associated with states 61 and 62 are state transitions 64, 65, 66, and 67. State 61 is labeled "CE -- OFF" and represents the condition in which the chip enable associated with the region is to be inactive. HPCE state machine 60 remains in state 61 as long as there is no match or whenever there is a reset, which is represented by state transition 64.
- HPCE state machine 60 transitions to state 62, which is labeled "CE -- ON", whenever there is a match to the region while reset is inactive, or if the option register 1 indicates that the CE signal is never to be negated and reset is inactive, and is represented by state transition 65.
- Chip select circuit 40 keeps the chip enable signal active continuously as long as HPCE state machine 60 remains in state 62.
- HPCE state machine 60 may be implemented with conventional logic circuitry as is well known in the art. However note that a separate hardware timer to count the number of cycles that have elapsed since the last access to the region is preferred. In this case while in state 62, HPCE state machine 60 will decrement the timer once every cycle is started and will reload the counter every time there is a match to the region associated with HPCE state machine 60.
- FIG. 4 illustrates a state diagram associated with BCS state machine 70 and includes states 71-76 and state transitions 80-85 and 90-92.
- State 71 is labeled "M0" and represents the idle state of BCS state machine 70. Note that in state M0 71 if HPCE state machine 60 is in CE -- ON state 62, then BCS state machine 70 activates signal LBA upon the occurrence of the beginning of an access cycle. Note that BCS state machine 70 remains in M0 state 71 as long as there is no address match to the region. BCS state machine 70 also remains in M0 state 71 if it recognizes an external bus request, labeled "EBR". BCS state machine 70 leaves M0 state 71 when it recognizes an address match.
- EBR external bus request
- BCS state machine 70 makes transition 90 into a state 75 labeled "M1W", and further makes transition 91 into a state 76 labeled "M2W” in order to initially power up the memory through the activation of signal HPCE before the access begins.
- M1W state 75 signal LBA is activated and a transition 90 to M1W state 75 corresponds to HPCE state machine 60 making transition 65.
- An additional half dock period occurs through transition 91 into M2W state 76, which then transitions through state transition 92 into M1/M3 state 72.
- BCS state machine 70 remains in M1/M3 state 72 while initial wait states are expiring for a minimum bus cycle time. BCS state machine 70 remains in M1/M3 state 72 for a minimum of one-half clock period, but may remain in M1/M3 state 72 for additional wait states, represented by transition 81. BCS state machine 70 makes transition 82 into a state 73 labeled "M2/MW" to begin a data phase of the transfer. In M2/MW state 73, BCS state machine 70 activates signals BTACK and BAA. Note that signal BTACK is provided to internal bus 36 to recognize the termination of one segment or "beat" of the burst.
- the BURST DATA TIMING bit in option register 52 determines whether there are wait states during the data phase of the burst transfer and if the BURST DATA TIMING bit is set, signals BTACK and BAA are only activated only every other dock cycle.
- BCS state machine 70 makes transition 83 into a state 74 labeled "M5/M3" at the expiration of the prescribed number of wait states before the data transfer and in M5/M3 state 74, the data is actually transferred. If there are additional beats of data remaining in the burst then BCS state machine 70 makes transition 84 back into state 73. At the end of the burst, BCS state machine 70 makes transition 85 back into M0 state 71 and activates signal DTACK to internal bus 36.
- HPCE state machine 60 was used as the mechanism to decide whether to speculatively activate signal LBA.
- other mechanisms which are based on the history of accesses to the region may be used.
- another mechanism could use the relative frequency of accesses to the region to predict the likelihood of a next access to the region, in a manner similar to branch prediction used in high performance microprocessors.
- Burst Address Generator (BAG) 55 is made up of two modulo counters, address incrementor 101, and burst counter 102, and is coupled to internal bus 36, MUX 103, and MUX 104.
- Address incrementor 101 receives a MATCH signal and an initial address on a portion of internal bus 36 labeled IADDR (5:1).
- Address incrementor 101 also receives a BTACK signal which is used to increment the address stored in address incrementor 101.
- a BOUNDARY DETECT signal is provided to Multiplexer (MUX) 103.
- BAG 55 has logic to control MUX 104 to output the burst address on the external bus 24.
- BAG 55 generates each individual burst address during a burst cycle, and terminates the burst cycle based on the architectural requirements.
- BAG 55 latches the starting burst address in address incrementor 101 and increments the burst address by one word or one increment IADDR (1) every time BTACK is asserted.
- the burst address e.g. burst portion of the address or IADDR (5:1)
- burst devices requiring an incremented burst address for every data transfer are satisfied.
- MUX 104 is supplied a burst start address from IADDR (5:1) and an incremented burst address from address incrementor 101.
- the option register 52 MEMORY TYPE selection of PIPELINE FLASH indicates whether to provide the incremented address or the burst start address to the external address bus 24.
- the PIPELINE FLASH information is provided to MUX 104 and selects between generation of continuous burst start address or incremented burst address to external bus 24.
- Alternate embodiments are available for determining external address provision based on system requirements, such as signals from the data processor, control register state, or signals from external devices. Note that alternate embodiments may have various lengths of significant burst address and that the amount of data information provided may be predetermined or programmable. Note that the upper portion of address bits is provided to external bus 24.
- Termination of burst cycle in BAG 55 is based on either the physical address reached in address incrementor 101 or the number of burst transfers counted in burst counter 102.
- DTACK signal if the burst cycle accesses memory location (2 N- 1) the bus cycle terminates by internal assertion of DTACK signal. Note that such an assertion of DTACK signal restarts burst operation on the next bus cycle starting at address 2 N .
- this field is programmed to select the burst length according to TABLE I, where the burst cycle is terminated after the number of data transfers indicated by DEVICE BOUNDARY bits.
- the MATCH signal and the BTACK signal are both also supplied to a burst counter 102.
- the BAG MODE bit indicates the type of transaction to be performed, either cache type or pre-fetch type. Assertion of the BAG M0DE bit in option register 56 indicates a cache access to burst counter 102 and to MUX 103.
- burst counter 102 In response to the MATCH signal, burst counter 102 initializes and counts to a predetermined number of data transfers, which is determined by the cache line size.
- FIG. 7 illustrates in block diagram form a second portion 110 of chip select circuit 40 of FIG. 1.
- Portion 110 includes generally base address register 111, an option register 112, a base address comparator 113, and an asynchronous state machine 114.
- Base address register 111 stores bits including a base address and size of the region associated with portion 110 and provides them as an input to base address comparator 113.
- Base address comparator 113 also has a second input for receiving critical bits of the address conducted on the internal bus 36 labeled IADDR (23:15).
- Base address comparator 113 activates an output labeled "MATCH" which indicates that the address represented by critical address bits IADDR (23:15) are within the range defined in base address register 111.
- asynchronous state machine 114 selectably negates signal CSi early in the cycle if the NEGATE EARLY bit is set in option register 112.
- FIG. 8 illustrates a timing diagram of a bus cycle. Shown in FIG. 8 are six half clock periods which form three full dock periods of a minimum-length bus cycle, labeled "S0", “S1”, “S2”, “S3”, “S4", and "S5". The cycle begins when CPU 32 activates signal ICYS one half clock before S0.
- signal CSi may be activated during period S1 at a time point labeled "t1" if the STRB bit in option register 112 indicates that signal CSi should be activated synchronously with the address strobe signal.
- signal CSi is deactivated at the end of the bus cycle in state S5 at a time labeled "t3". This "normal” operation is shown by the deactivation of signal CSi at time point t3 (state S5) during one cycle in which there are no wait states, and at time point t6 (state S5) during another cycle in which there are two wait states.
Abstract
Description
TABLE I ______________________________________ Bit(s) Name Encoding ______________________________________ 2:0 INITIAL TIMING 000-111 = 0 through 7 3BURST DATA TIMING 0 = no waits betweenburst data 1 = 1 wait between burst data 5:4 DEVICE BOUNDARY 00 = 4 01 = 8 10 = 16 11 = 32 7:6 MEMORY TYPE 00 = burst flash, and SRAM 01 = undefined 10 = pipeline flash 11 = asynchronous SRAM and flash 9:8 HPCE 00 = negate 4 bus cycles after last access 01 = negate 8 bus cycles after last access 10 = always negate after cycle 11 = never negate 10WRITE HOLD 0 = negate BWE and WE.sub.LO inS5 1 = negate BWE and WE.sub.LO on clock before S5 11MSIZE 0 = 16-bit 1 = 8-bit 12 R/W 0 = read only 1 = read/write 13SPACE 0 =user space 1 = supervisor/user 15:14 BURST RESPONSE 00 = disable BCS 01 = burst R/W operation 10 = burst read/non-burst write operation 11 = non-burst write operation ______________________________________
TABLE II ______________________________________ Bit(s) Name Encoding ______________________________________ 7:0 RESERVED 0000 0000 8BCS TRIGGER 0 = only onBCS match 1 = on BCS match or on asynchronous chip select match 9BAG MODE 0 =Pre-fetch mode 1 = Cache mode 10LBA FUNCTION 0 = asHPCE 1 = as a memory strobe 11BAA FUNCTION 0 = asHPCE 1 = as a memory strobe 12-15 RESERVED 000 ______________________________________
TABLE III ______________________________________ Bit(s) Name Encoding ______________________________________ 3:0 DTACK (WAITS) 0000-1110 = 0-14 wait states 1111 = external termination 4STRB 0 =CE 1 =DS 5SIPL 0 = no IPL checking 1 = only match assigned IPL 6 RSVD Reserved. 7 NEGATE EARLY 0 = negate CS inS5 1 = negate CS one clock before cycle ends 9:8 Prog/Data 00 = data or program 01 = data space 10 = program space 11 = reserved 11:10 SPACE 00 = CPU space 01 = user space 10 = supervisor space 11 = supervisor or user space 13:12 R/W 00 = chip select disabled 01 = read only 10 = write only 11 = both 15:14 PSIZ 00 = 8-bit port 01 = 16-bit port, lower byte 10 = 16-bit port, upper byte 11 = 16-bit port, both bytes ______________________________________
Claims (10)
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/660,620 US5875482A (en) | 1996-06-06 | 1996-06-06 | Method and apparatus for programmable chip select negation in a data processing system |
EP97108577A EP0811921B1 (en) | 1996-06-06 | 1997-05-28 | Method for accessing memory |
EP01129841A EP1197867A3 (en) | 1996-06-06 | 1997-05-28 | Method for accessing memory |
DE69718846T DE69718846T2 (en) | 1996-06-06 | 1997-05-28 | Memory access method |
JP9162003A JPH1083343A (en) | 1996-06-06 | 1997-06-04 | Method for accessing memory |
TW086107699A TW363153B (en) | 1996-06-06 | 1997-06-04 | Method for accessing memory |
KR1019970023303A KR100457478B1 (en) | 1996-06-06 | 1997-06-05 | Memory access method and data processing system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/660,620 US5875482A (en) | 1996-06-06 | 1996-06-06 | Method and apparatus for programmable chip select negation in a data processing system |
Publications (1)
Publication Number | Publication Date |
---|---|
US5875482A true US5875482A (en) | 1999-02-23 |
Family
ID=24650266
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/660,620 Expired - Lifetime US5875482A (en) | 1996-06-06 | 1996-06-06 | Method and apparatus for programmable chip select negation in a data processing system |
Country Status (1)
Country | Link |
---|---|
US (1) | US5875482A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5944815A (en) * | 1998-01-12 | 1999-08-31 | Advanced Micro Devices, Inc. | Microprocessor configured to execute a prefetch instruction including an access count field defining an expected number of access |
US6173368B1 (en) * | 1995-12-18 | 2001-01-09 | Texas Instruments Incorporated | Class categorized storage circuit for storing non-cacheable data until receipt of a corresponding terminate signal |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4309754A (en) * | 1979-07-30 | 1982-01-05 | International Business Machines Corp. | Data interface mechanism for interfacing bit-parallel data buses of different bit width |
US4841488A (en) * | 1986-04-08 | 1989-06-20 | Nec Corporation | Semiconductor memory circuit with improved timing and delay control for data read out |
US5329178A (en) * | 1991-11-27 | 1994-07-12 | North American Philips Corporation | Integrated circuit device with user-programmable conditional power-down means |
US5688769A (en) * | 1979-09-21 | 1997-11-18 | Roussel Uclaf | Treatment method |
-
1996
- 1996-06-06 US US08/660,620 patent/US5875482A/en not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4309754A (en) * | 1979-07-30 | 1982-01-05 | International Business Machines Corp. | Data interface mechanism for interfacing bit-parallel data buses of different bit width |
US5688769A (en) * | 1979-09-21 | 1997-11-18 | Roussel Uclaf | Treatment method |
US4841488A (en) * | 1986-04-08 | 1989-06-20 | Nec Corporation | Semiconductor memory circuit with improved timing and delay control for data read out |
US5329178A (en) * | 1991-11-27 | 1994-07-12 | North American Philips Corporation | Integrated circuit device with user-programmable conditional power-down means |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6173368B1 (en) * | 1995-12-18 | 2001-01-09 | Texas Instruments Incorporated | Class categorized storage circuit for storing non-cacheable data until receipt of a corresponding terminate signal |
US5944815A (en) * | 1998-01-12 | 1999-08-31 | Advanced Micro Devices, Inc. | Microprocessor configured to execute a prefetch instruction including an access count field defining an expected number of access |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6571308B1 (en) | Bridging a host bus to an external bus using a host-bus-to-processor protocol translator | |
JP3739797B2 (en) | Reduced instruction set computer microprocessor structure | |
US5455927A (en) | Dual socket upgradeable computer motherboard with automatic detection and enablement of inserted upgrade CPU chip | |
US4787032A (en) | Priority arbitration circuit for processor access | |
EP0426329B1 (en) | Combined synchronous and asynchronous memory controller | |
EP0700003B1 (en) | Data processor with controlled burst memory accesses and method therefor | |
US6493803B1 (en) | Direct memory access controller with channel width configurability support | |
US6460107B1 (en) | Integrated real-time performance monitoring facility | |
US5109521A (en) | System for relocating dynamic memory address space having received microprocessor program steps from non-volatile memory to address space of non-volatile memory | |
JP3740250B2 (en) | Method and apparatus for determining a standby state for each cycle in a data processor | |
JP2002539527A (en) | Microprocessing device with programmable wait state | |
US5796968A (en) | Bus arbiter used in a computer system | |
US5664168A (en) | Method and apparatus in a data processing system for selectively inserting bus cycle idle time | |
US6658508B1 (en) | Expansion module with external bus for personal digital assistant and design method therefor | |
US5448742A (en) | Method and apparatus for local memory and system bus refreshing with single-port memory controller and rotating arbitration priority | |
US5813041A (en) | Method for accessing memory by activating a programmable chip select signal | |
JPH0528097A (en) | Microprocessor | |
US6678838B1 (en) | Method to track master contribution information in a write buffer | |
US5577214A (en) | Programmable hold delay | |
US6006288A (en) | Method and apparatus for adaptable burst chip select in a data processing system | |
US5905887A (en) | Clock frequency detection for computer system | |
US5590316A (en) | Clock doubler and smooth transfer circuit | |
US6477609B1 (en) | Bridge state-machine progression for data transfers requested by a host bus and responded to by an external bus | |
EP0811921B1 (en) | Method for accessing memory | |
US5557782A (en) | Flexible deterministic state machine |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MOTOROLA, INC., ILLINOIS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MCINTYRE, KENNETH L. JR.;COLLINS COLLEEN M.;REIPOLD, ANTHONY M.;AND OTHERS;REEL/FRAME:008121/0901 Effective date: 19960724 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MOTOROLA, INC.;REEL/FRAME:015698/0657 Effective date: 20040404 Owner name: FREESCALE SEMICONDUCTOR, INC.,TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MOTOROLA, INC.;REEL/FRAME:015698/0657 Effective date: 20040404 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: CITIBANK, N.A. AS COLLATERAL AGENT, NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNORS:FREESCALE SEMICONDUCTOR, INC.;FREESCALE ACQUISITION CORPORATION;FREESCALE ACQUISITION HOLDINGS CORP.;AND OTHERS;REEL/FRAME:018855/0129 Effective date: 20061201 Owner name: CITIBANK, N.A. AS COLLATERAL AGENT,NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNORS:FREESCALE SEMICONDUCTOR, INC.;FREESCALE ACQUISITION CORPORATION;FREESCALE ACQUISITION HOLDINGS CORP.;AND OTHERS;REEL/FRAME:018855/0129 Effective date: 20061201 |
|
AS | Assignment |
Owner name: CITIBANK, N.A., AS COLLATERAL AGENT,NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:024397/0001 Effective date: 20100413 Owner name: CITIBANK, N.A., AS COLLATERAL AGENT, NEW YORK Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:024397/0001 Effective date: 20100413 |
|
FPAY | Fee payment |
Year of fee payment: 12 |
|
AS | Assignment |
Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YOR Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:030633/0424 Effective date: 20130521 |
|
AS | Assignment |
Owner name: CITIBANK, N.A., AS NOTES COLLATERAL AGENT, NEW YOR Free format text: SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:031591/0266 Effective date: 20131101 |
|
AS | Assignment |
Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037356/0143 Effective date: 20151207 Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037354/0225 Effective date: 20151207 Owner name: FREESCALE SEMICONDUCTOR, INC., TEXAS Free format text: PATENT RELEASE;ASSIGNOR:CITIBANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:037356/0553 Effective date: 20151207 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:037486/0517 Effective date: 20151207 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:037518/0292 Effective date: 20151207 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: SUPPLEMENT TO THE SECURITY AGREEMENT;ASSIGNOR:FREESCALE SEMICONDUCTOR, INC.;REEL/FRAME:039138/0001 Effective date: 20160525 |
|
AS | Assignment |
Owner name: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040925/0001 Effective date: 20160912 Owner name: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC., NE Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040925/0001 Effective date: 20160912 |
|
AS | Assignment |
Owner name: NXP B.V., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:040928/0001 Effective date: 20160622 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:041703/0536 Effective date: 20151207 |
|
AS | Assignment |
Owner name: SHENZHEN XINGUODU TECHNOLOGY CO., LTD., CHINA Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITYINTEREST IN PATENTS.;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:048734/0001 Effective date: 20190217 |
|
AS | Assignment |
Owner name: NXP B.V., NETHERLANDS Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:050744/0097 Effective date: 20190903 |
|
AS | Assignment |
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., MARYLAND Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITYINTEREST IN PATENTS;ASSIGNOR:CITIBANK, N.A.;REEL/FRAME:053547/0421 Effective date: 20151207 |
|
AS | Assignment |
Owner name: NXP B.V., NETHERLANDS Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVEAPPLICATION 11759915 AND REPLACE IT WITH APPLICATION11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITYINTEREST;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:052915/0001 Effective date: 20160622 |
|
AS | Assignment |
Owner name: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC., NETHERLANDS Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVEAPPLICATION 11759915 AND REPLACE IT WITH APPLICATION11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITYINTEREST;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC.;REEL/FRAME:052917/0001 Effective date: 20160912 |