|Número de publicación||US5977791 A|
|Tipo de publicación||Concesión|
|Número de solicitud||US 08/834,426|
|Fecha de publicación||2 Nov 1999|
|Fecha de presentación||14 Abr 1997|
|Fecha de prioridad||15 Abr 1996|
|También publicado como||US6242946|
|Número de publicación||08834426, 834426, US 5977791 A, US 5977791A, US-A-5977791, US5977791 A, US5977791A|
|Inventores||Kerry S. Veenstra|
|Cesionario original||Altera Corporation|
|Exportar cita||BiBTeX, EndNote, RefMan|
|Citas de patentes (63), Otras citas (68), Citada por (74), Clasificaciones (7), Eventos legales (6)|
|Enlaces externos: USPTO, Cesión de USPTO, Espacenet|
This application claims the benefit of Provisional Application Ser. No. 60/015,443, filed Apr. 15, 1996, incorporated herein by reference.
The present invention relates generally to the field of integrated circuits and their operation, and more specifically to devices known in the industry as programmable logic devices. In particular, one embodiment of the present invention provides a programmable logic device with enhancements for efficient implementation of a first-in, first-out (FIFO) memory device.
Programmable logic devices have found particularly wide application in the industry. Their versatility, low design cost, and ease of use have combined to make these devices widely used in the logic design process. Programmable logic devices (sometimes referred to as PLDs, PALs, PLAs, FPLAs, EPLDs, EEPLDs, LCAs, or FPGAs,) are well known integrated circuits that combine the advantages of fixed integrated circuits with the flexibility of custom-designed integrated circuits.
The distinguishing feature of a programmable logic device is the ability of a user to electronically program a standard, off-the-shelf part to perform logic functions to meet the user's individual needs. Their use is well-known in the industry and are described, for example, in U.S. Pat. No. 4,617,479, which is incorporated herein by reference for all purposes. Such devices are currently represented, for example, by Altera's MAX® series of PLDs and Altera's FLEX® series of embedded PLDs.
A technique by which programmable logic devices have been implemented uses multiple blocks of configurable logic which are interconnected by some type of interconnection system. These configurable logic blocks are electronically programmable to provide desired logic functions. In order to provide efficient implementation of different functions, the configurable logic blocks are sometimes specially designed for certain applications. For example, one type of configurable logic block is a logic array block (LAB). LABs are designed to be useful in implementing generalized logic functions. Another type is an embedded array block (EAB). EABs are specially designed for implementing memories and other specialized logic functions. Often, different types of configurable logic blocks are provided within a single programmable logic device. This gives a user flexibility in realizing desired logic functions.
The configurable logic blocks are typically coupled together by an interconnection system. For example, a popular programmable logic device provides an interconnect grid to connect different configurable logic blocks to each other and also to input/output ports. This interconnect grid typically comprises sets of horizontal conductors and vertical conductors which are programmably connected to the configurable logic blocks and the input/output ports.
In addition to the interconnect grid, often each of the configurable logic blocks have local interconnect systems. These local interconnects are conductors which provide either fixed or programmable routing of signals within the configurable logic block.
Altera's FLEX® 10K line is an example of a product that provides both logic array blocks and embedded array blocks in a single programmable logic device. The embedded array blocks and logic array blocks are coupled by an innovative interconnect system. The FLEX® 10K line is described, for example, in the Altera Data Book, June 1996 and U.S. Pat. Nos. 5,241,224 and 4,871,930, which are included herein by reference for all purposes.
A common application for which a programmable logic device may be used is a first in, first-out (FIFO) memory. A FIFO is a particular memory scheme in which data is read out from the memory in the same order in which it was written into the memory. As is well known in the art, the implementation of such a device may include, for example, two counters and a memory array. One of the counters is a pointer to the next address from which data is to be read, while the second counter is a pointer to the next address to which data is to be written.
According to the present state of the art, multiple configurable logic blocks are used to design such a FIFO in a programmable logic device. Typically, for example, the counters are implemented in a logic array block or other configurable logic block. The memory array is implemented in a second configurable logic block, for example, an embedded array block. In such an arrangement, two sets of address lines are routed from the counters in the logic array block to the memory array in the embedded array block.
Routing of signals throughout a programmable logic device is a significant issue. Often, the number of available conductors is limited. The space required for introducing more conductors is significant. In a generalized device such as a programmable logic device, it is particularly desirable that the number of interconnections be as low as possible, while still allowing the user to implement common functions. By keeping the number of interconnections at a minimum, more of the space is available for implementing logic functions.
It is apparent from the above, that an improved programmable logic device is desirable. The present invention recognizes the desirability of implementing a FIFO memory in a programmable logic device while saving the number of conductors of the interconnect system that must be utilized.
The present invention provides a configurable logic block for use in a programmable logic device which allows for the implementation of a first-in, first-out memory while saving programmable interconnect lines.
In accordance with the present invention is a configurable logic block for a programmable logic device that is configurable as a first-in, first-out memory in a first mode (i.e. FIFO mode). The configurable logic block comprises a memory array having a plurality of memory cells arranged in a random access memory format with address lines for uniquely addressing each of the memory cells. The configurable logic block further comprises a first register which is coupled to the address lines of the memory array. The first register contains the write address for the memory array when in the FIFO mode. A second register is coupled to address lines of the memory array and contains the read address for the memory when in the FIFO mode. The first and second registers may be implemented, for example, using counters. Finally, the configurable logic block has a local interconnect that is coupled to the memory array, the first register, and the second register.
In one embodiment, the memory array has separate write address lines coupled with the first register and read address lines coupled with the second register, thereby forming a dual-port memory. Another embodiment of the present invention has an address input multiplexer that selectively couples the first register and the second register to the address lines of the memory arrays. During a write phase, the first register is connected to the address lines and during a read phase the second register is connected to the address lines.
According to the present invention, to save interconnect lines, the first register and the second register may be coupled to the address lines of the memory array without using the local interconnect. The local interconnect is used to provide control signals to the first and second register, along with control signals for the memory array.
The configurable logic blocks described above may be programmably cascaded and combined together to create larger blocks of memory. In this manner, different sizes of memories may be created, depending on the needs of the user.
The configurable logic block of the present invention may be implemented as part of a programmable logic device. For example, the programmable logic device may have a first type of configurable logic block that provides general logic, and a second type of configurable logic block that is configurable as a random access memory or as a FIFO as described above. These two types of configurable logic blocks may be located within an interconnection grid that allows each of the blocks to be programmably coupled together.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.
FIG. 1 is a diagram of a digital system incorporating a programmable logic device;
FIG. 2 is a block diagram of a programmable logic device;
FIG. 3 is a more detailed diagram of a logic array block (LAB) in a programmable logic device;
FIG. 4 is a more detailed diagram of an embedded array block (EAB) in a programmable logic device;
FIG. 5 is a block diagram of a first-in, first-out memory implemented in a programmable logic device;
FIG. 6 is a block diagram of a first-in, first-out memory implemented in the enhanced programmable logic device of the present invention;
FIG. 7 is a diagram of a first-in, first-out memory with the read address register and the write address register multiplexed to a single address port;
FIG. 8 is a diagram of a first-in, first-out memory with the read address register and the write address register coupled to separate read address and write address ports;
FIG. 9 is a diagram of a first-in, first-out memory with an enhanced write address register that is operable as a counter or as a data register; and
FIG. 10 is a diagram of a first-in, first-out memory with the read address counter and the write address counter duplicated in a logic array block.
FIG. 1 illustrates a typical environment in which the present invention may be embodied. A digital system has a processing unit 101 which is coupled with a memory 105 and an input/output device 111. A personal computer is one example of such a digital system. However, a wide variety of electronics and consumer products will find beneficial use from the present invention. For example, the present invention will be useful in digital systems in the areas of telecommunications, switches, networking systems, and many other applications.
Processing unit 101 contains one or more programmable logic devices 121 of the type described in the present invention. In other embodiments of this invention, one or more programmable logic devices 121 are contained within input/output device 111 or memory 105.
The digital system of FIG. 1 may be embodied on a single board, on multiple boards, or even within multiple enclosures. Furthermore, the system may have any multiple or combination of the elements shown. For example, a digital system may have multiple processing units 101, or no processing unit 101 at all. One of the advantages of programmable logic device 121 is its logical flexibility. Consequently, one of skill in the art can readily see many applications for utilizing such a device within a variety of digital systems.
By way of example, FIG. 2 depicts the layout an Altera FLEX® 10K embedded programmable logic device. This is one example of a device for which the present invention is well suited. The device is comprised of logic arrays blocks 220, embedded array blocks 240, interconnect grid 260, and input/output elements 280. Logic array blocks 220 are depicted in more detail in FIG. 3 and embedded array blocks 240 are shown in FIG. 4.
Interconnect grid 260 is comprised of sets of horizontal conductors 262 and sets of vertical conductors 264 that are configured in a grid pattern. Within interconnect grid 260 is an array of logic array blocks 220 and embedded array blocks 240. Each of these blocks are programmably connectable to horizontal conductors 262 and vertical conductors 264 of interconnect grid 260. Interconnect grid 260 is also programmably connectable to input/output elements 280. By programming a connection between input/output elements 280, logic array blocks 220 and embedded array blocks 240 through horizontal conductors 262 and vertical conductors 264, the user may create desired logical functions. Interconnect grid 260 is described in detail, for example, in U.S. Pat. No. 5,260,610, which is incorporated herein by reference for all purposes.
Referring to FIG. 3, an example of logic array block 220 is depicted. Logic array block 220 is a configurable logic block which can be configured to provide general logic functions. Each logic array block 220 has a set of logic elements 300 which perform the logical operations. Each logic element 300 provides desired logical outputs based on the inputs provided to it. For example, logic element 300 may be a look-up table, a set of AND-gates, NAND-gates, OR-gates and/or NOR-gates that provide sum of products terms, product of sum terms, or other methods of producing desired logical functions.
In the example of FIG. 3, logic array block 220 contains a set of eight logic elements 300. Each of logic elements 300 has four inputs 302 and one output 304. There are also separate carry-in inputs 306, cascade-in inputs 308 and other control inputs 309 which simplify the chaining of multiple logic array blocks 220 together. The output 304 of a logic element 300 is determined by looking up in a configurable table the desired output for each combination of inputs.
Each logic array block 220 also has an LAB local interconnect 310 which provides local connections between logic elements 300 and also local connections between horizontal conductors 262 of interconnect grid 260 and inputs to the logic elements 300. LAB local interconnect 310 is programmably configurable to allow flexibility to the user in designing logic function.
The outputs of logic elements 300 are also programmable coupled to horizontal conductors 262 and vertical conductors 264 of interconnect grid 260. By this structure, the output of the LAB may be routed to other configurable logic blocks 300 within the programmable logic device.
The structure of the logic array block is described in more detail in, for example, the Altera Data Book, June 1996, and U.S. Pat. No. 5,260,611, which are incorporated herein by reference for all purposes.
FIG. 4 is a diagram of an example of embedded array block 240. It is a configurable logic block which is comprised of a memory array 410; a local interconnect 430; input registers 450, 454, and 460; an output register 470; and numerous routing multiplexers 452, 456, 462, 472, and 490. Local interconnect 430 routes data, address, and control information within embedded array block 240. It is programmably connectable to interconnect grid 260.
Embedded array block 240 may be operated either synchronously or asynchronously. Synchronous operation is that in which the write enable input (WE) to memory array 410 is timed with respect to the system clock. The user does not have to be concerned with separate timing specifications for the memory array 410 and need only meet the setup and hold times of the system clock. For asynchronous operation, the user provides the write enable input (WE) and the data and address input signals must meet the required timing specifications in relation to the write enable signal. Internal registers 450, 454, 460, and 470 are provided which allow the input signals to be latched for synchronous operation or bypassed for asynchronous operation. The details of this arrangement are described below.
Memory array 410 is comprised of a plurality of memory cells arranged as a random access memory. Memory array 410 may be programmably configurable to different sizes. For example, it may be programmably configurable as a 256×8, 512×4, 1024×2 or 2,048×1 memory block. A two-bit register (not shown) may be provided whereby each of the four configurations is identified by different combinations of bits in the two-bit register. More configurations may be implemented by increasing the size of the register to allow each configuration to be uniquely identified. Furthermore, it is anticipated that larger or smaller memory arrays may be implemented without departing from the spirit of the present invention.
The first number in the configuration descriptions above (i.e. 256×8) is the depth of the memory array. The depth of the memory array is the number of memory locations that are addressable. The second number is the width of the memory array or the number of bits in each memory location. For example, a 256×8 memory block is a memory block that contains 256 eight-bit memory locations. Similarly a 2,048×1 memory block contains 2,048 unique one-bit locations. A user of embedded array block 240 may programmably configure memory array 410 to be whichever size is more applicable to the application for which it is being used. As would be recognized by one of skill in the art, the number of address lines used to uniquely address each of these configurations is 8, 9, 10, and 11 respectively. For example, eight address lines are needed to uniquely address 256 locations.
Data is input to memory array 410 on data-in lines of memory array 410 via local interconnect 430. These data-in lines are coupled either directly to local interconnect 430 or though a data input register 450. Whether the connection is direct or through data input register 450, is determined by a routing multiplexer 452 which is programmably configurable by the user. This provides the user with a choice of synchronous operation by using data input register 450, or asynchronous operation by bypassing it.
Similarly, the address is input on the address lines of memory array 410 through local interconnect 430 either directly or through an address input register 454. Whether the address lines are connected directly to local interconnect 430, or pass through address input register 454 is determined programmably by the user through a second routing multiplexer 456.
Memory array 410 also has a write enable input (WE). When this signal is asserted, the data on the data-in lines is written to whatever address of memory array 410 is specified on the address lines. The write enable signal is generated by global control signals and control signals from the local interconnect 430. As with the data and address signals, using routing multiplexer 462, the user may select either a direct signal or one that has been latched in write enable register 460.
The output data is latched into data output register 470. A routing multiplexer 480 selectively connects either the latched data or the raw output data to interconnect output multiplexer 490. Interconnect output multiplexer 490 routes the signal to either horizontal conductors 262 or vertical conductors 264 of interconnect grid 260.
Data is written to memory array 410 by placing the data on the data-in lines, a write address on the address lines and asserting the write enable line. Data is read from memory array 410 by placing a read address on the address lines and sampling the data output lines.
Referring to FIG. 5, a block diagram of a known implementation of a FIFO is depicted for the programmable logic device of FIG. 2 using the embedded array block 240 that is shown in FIG. 4. Embedded array block 240 has a local interconnect 502, input control logic 504 (which contains all of the routing logic and registers between local interconnect 502 and memory array 506), memory array 506, and output control logic 508 (which contains the data output register and routing control).
Logic array block 220 is configured as a read address counter 512 and a write address counter 514. The function of read address counter 512 is to maintain the address of the next address location from which data is to be read. Each time data is read from the FIFO, read address counter 512 is incremented. Similarly, the write address counter maintains the address of the next address location to which data is to be written. Each time that data is written to an address, write address counter 514 is incremented.
Control signals for memory array 506, read counter 512 and the write address counter 514 are generated from read/write control logic 520. Typically, these functions require a read clock (RDclk), a read enable line (RDena), a write clock (WRclk), a write enable line (WRena) and a reset line (RESET). When the reset line is asserted, both address counters 512 and 514 are reset to an initial value. When the write enable line and the write clock line are simultaneously asserted, the data is written into the first address of memory array 530 and write address counter 514 is incremented.
When the read clock is asserted when the read enable line is active, memory array 506 places the data that is located at the address pointed to by read address counter 512 on data out line 532 and the read address counter 512 is incremented. Additional logic (not shown) is typically provided in order to prevent reading from an empty FIFO and writing to a full FIFO. Often, it is desirable to know when the FIFO is nearly full to give the user advanced warning before it is entirely full. For example, an application in which data is written to memory array 506 in blocks of data must know in advance to tell the sender to stop sending when there is only enough room for one more block of data. These functions can be implemented in several ways as is clear to one of skill in the art.
One way of determining the status of a FIFO is to compare the values in read address counter 512 and write address counter 514. Read address counter 512 will be equal to write address counter 514 when the FIFO is either empty or full. If only a write operation has just occurred and the counters are equal, the FIFO must be full. If only a read operation has just occurred, the FIFO must be empty. If a read and a write operation have both just occured, the FIFO remains in whatever state it was before, full, empty, or neither. of course, other methods of determining the status for the FIFO will be readily apparent to one of skill in the art.
Another state that may be of interest is when the FIFO is nearly full. If a comparison of read address counter 512 and write address counter 514 shows the difference to be less than a defined value, then the FIFO is nearly full. The defined value may be programmable so that the application software is able to vary how full the FIFO is when it is warned of a nearly full condition by the hardware. A person of skill in the art can readily conceive of many alternative ways of accomplishing the same result. For example, a separate counter may be used that keeps track of the number of data values in the FIFO and the status may be derived from the value in the separate counter.
As specified above, embedded array block 240 is configurable to have from 256 addresses to 2,048 addresses. Hence, from 8 to 11 address lines are needed to uniquely identify each address location, depending upon the configuration of memory array 506. Since both read address counter 512 and write address counter 514 are used in the implementation of a FIFO, 16 to 22 address lines extend from the address counters 512 and 514 in logic array block 220 to the address lines of memory array 506 in embedded array block 240. Furthermore, along with the address lines, data and control lines also extend from logic array block 220 to embedded array block 500. It is desirable to not use so many interconnect lines. By reducing the number of interconnect lines, more room is available on the device for additional logic.
Past innovative designs have resolved this problem by multiplexing the read address counter and the write address counter within logic array block 220. Address multiplexer 540 allows read address counter 512 to be coupled to the interconnect lines during one-half of the clock cycle and the write address to be coupled to the interconnect lines during the other half of the cycle. By sharing interconnect lines in this way, the number of interconnect lines needed to provide memory array 506 with address information is cut in half.
Referring now to FIG. 6, a block diagram of an embodiment of a programmable logic device of the present invention is depicted. The programmable logic device has an embedded array block 610 and a logic array block 620. Embedded array block 610 has a read address register 630 and a write address register 640. The outputs of read address register 630 and write address register 640 are coupled to the address lines of memory array 650 through input control logic 660.
Logic array block 620 is configured with read/write control logic 670 to generate the necessary control lines for a FIFO. Typically, these include a read enable line (RDena), a read clock (RDclk), a write enable line (WRena), a write clock (WRclk) and a reset line (RESET). The output of the read/write control logic is coupled with input control logic 660, read address register 630, and write address register 640 through interconnect grid 260 and local interconnect 690.
Because read address register 630 and write address register 640 are located within embedded array block 610, the control lines mentioned above and the data lines are the only connections that must be made through the local interconnect 690 or interconnection grid 260. This allows for a more compact and efficient FIFO design.
FIG. 7 shows a more detailed diagram of embodiment of the present invention. An embedded array block 700 is a configurable logic block for use in a programmable logic device. Embedded array block 700 has two modes. The first mode is as a RAM memory that is randomly accessible to any address the user specifies on the address lines. The second mode is as a FIFO. An enhanced input address register 710 has two operating modes depending on the mode of embedded array block 700. When in RAM mode, enhanced input data register 710 operates as described above with reference to FIG. 4. That is, the address lines of memory array 714 are selectively coupled by routing multiplexer 730, either directly from local interconnect 720 or through enhanced input data register 710.
When in FIFO mode, enhanced input data register 710 operates as a counter to provide the function of a write address counter. As a counter, enhanced input data register 710 accepts control input from local interconnect 720. Its output is selectively coupled to the address lines of memory array 714 through routing multiplexer 730.
Embedded array block 700 also includes a read address counter 750. Read address counter 750 receives control input from local interconnect 720 and its output is selectively coupled to the address lines of memory array 714 through routing multiplexer 730.
By this arrangement, there is no need to use interconnect grid 260 or local interconnect 720 to couple the address lines from logic array block 220 to embedded array block 700. Write address counter 710 and read address counter 750 are located physically close to where the information they hold will be used. This saves on interconnection resources. It also improves the delay time associated with the address lines.
FIG. 8 shows another embodiment of the present invention that is a further improvement on the state of the art. An embedded array block 800 is a configurable logic block with an enhanced memory array 810. Enhanced memory array 810 has additional address inputs which allow it to be used as a simultaneous dual-port memory. That is, separate read and write address ports are available and enhanced memory array 810 can perform a write operation simultaneously with a read operation.
Embedded array block 800 also has a read address register 820 and a write address register 830. In RAM mode, the addresses are provided from data input register 840. However, when in FIFO mode, memory array 810 has its read address lines coupled to read address register 820 and its write address lines coupled to write address register 830. The control lines necessary for read address register 820 and write address register 830 are provided through local interconnect 850 and interconnect grid 260. Write address routing multiplexer 860 and read address routing multiplexer 862 select the source of the read address and the write address. In RAM mode the addresses come from data input register 840 or local interconnect 850. In FIFO mode, the addresses are provided by address counters 820 and 830.
Several advantageous features are readily apparent in the embodiment of the present invention shown in FIG. 8. As mentioned previously, the number of interconnect lines utilized by both local interconnect 850 and interconnection grid 260 in the implementation of a FIFO are minimized. Furthermore, in this embodiment, embedded array block 800 is operable as a simultaneous dual-port FIFO.
A dual-port FIFO is desirable in many applications. The key feature of a dual-port FIFO is that data may be written to the FIFO and read from the FIFO simultaneously. Separate read address lines and write address lines are provided so that each can be addressed individually.
Referring now to FIG. 9, another embodiment of the present invention is depicted. Additional logic is added to input data register 840 (shown in FIG. 8) to create an enhanced input data register 900 as shown in FIG. 9. The additional logic allows enhanced input data register 900 to operate in two separate modes. In RAM mode, it operates as a data register that latches whatever data is presented at the input. In the FIFO mode, enhanced data register 900 operates as a counter, incrementing its value by one for each clock pulse when the increment (INC) line is asserted.
This has the advantage of saving space in embedded array block 910. Since the write counter function is not used in RAM mode, and the input data register function is not used in FIFO mode, the extra register is a redundancy that is eliminated in this embodiment.
FIG. 10 depicts yet another embodiment of the present invention. Therein, read address register 1010 and write address register 1020 of embedded array block 1030 are duplicated in logic array block 1040. In some applications, it is desirable to extract address information from read address register 1010 and write address register 1020 to determine the status of the FIFO such as when it is empty, full or nearly full.
In order to save interconnect lines in interconnect grid 260 and local interconnect 1050 as described above, address counters 1010 and 1020 remain within embedded array block 1030. Hence, the information contained in address counters 1010 and 1020 is not available outside of embedded array block 1030. By duplicating address registers 1010 and 1020 outside of embedded array block 1030, the information contained in them is accessible, without using precious resources of local interconnect 1050 and interconnect grid 260.
Logic array block 1040 is configured to contain status logic 1060. Status logic 1060 monitors duplicate read address register 1070 and duplicate write address register 1080. The outputs of status register 1060 are status flags indicating the status of the FIFO. For example, the output in this embodiment indicates when the FIFO is nearly full. Other embodiments, for example, indicate when the FIFO is full or empty. The status may be determined, for example, in the manner described above.
It will be understood that the foregoing embodiments are merely illustrative of the principles of this invention. Various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention. For example, the size of the memory array can be altered, the logic can be spread around to multiple logic array blocks, and variations can be made to the interconnections. The examples given above are intended to aid in the understanding of the present invention, and are not intended to imply any limitation, other than those specified in the claims.
|Patente citada||Fecha de presentación||Fecha de publicación||Solicitante||Título|
|US34363 *||11 Feb 1862||Improvement in machinery for cleaning cotton|
|US34444 *||18 Feb 1862||Improvement in pumps for deep wells|
|US3473160 *||10 Oct 1966||14 Oct 1969||Stanford Research Inst||Electronically controlled microelectronic cellular logic array|
|US4020469 *||9 Abr 1975||26 Abr 1977||Frank Manning||Programmable arrays|
|US4124899 *||23 May 1977||7 Nov 1978||Monolithic Memories, Inc.||Programmable array logic circuit|
|US4293783 *||1 Nov 1978||6 Oct 1981||Massachusetts Institute Of Technology||Storage/logic array|
|US4546273 *||11 Ene 1983||8 Oct 1985||Burroughs Corporation||Dynamic re-programmable PLA|
|US4609986 *||14 Jun 1984||2 Sep 1986||Altera Corporation||Programmable logic array device using EPROM technology|
|US4617479 *||3 May 1984||14 Oct 1986||Altera Corporation||Programmable logic array device using EPROM technology|
|US4642487 *||26 Sep 1984||10 Feb 1987||Xilinx, Inc.||Special interconnect for configurable logic array|
|US4670749 *||13 Abr 1984||2 Jun 1987||Zilog, Inc.||Integrated circuit programmable cross-point connection technique|
|US4677318 *||12 Abr 1985||30 Jun 1987||Altera Corporation||Programmable logic storage element for programmable logic devices|
|US4706216 *||27 Feb 1985||10 Nov 1987||Xilinx, Inc.||Configurable logic element|
|US4713792 *||6 Jun 1985||15 Dic 1987||Altera Corporation||Programmable macrocell using eprom or eeprom transistors for architecture control in programmable logic circuits|
|US4717912 *||7 Oct 1982||5 Ene 1988||Advanced Micro Devices, Inc.||Apparatus for producing any one of a plurality of signals at a single output|
|US4758985 *||28 Mar 1986||19 Jul 1988||Xilinx, Inc.||Microprocessor oriented configurable logic element|
|US4780846 *||28 Jun 1985||25 Oct 1988||Fujitsu Limited||Master slice type semiconductor circuit device|
|US4825414 *||24 Jun 1988||25 Abr 1989||Fujitsu Limited||Semiconductor integrated circuit device having gate array and memory and input-output buffer|
|US4831591 *||8 Jul 1986||16 May 1989||Nec Corporation||Semiconductor memory capable of executing logical operation|
|US4855958 *||17 Ago 1988||8 Ago 1989||Fujitsu Limited||Semiconductor integrated circuit device having logic macro and random access memory macro|
|US4870302 *||19 Feb 1988||26 Sep 1989||Xilinx, Inc.||Configurable electrical circuit having configurable logic elements and configurable interconnects|
|US4871930 *||5 May 1988||3 Oct 1989||Altera Corporation||Programmable logic device with array blocks connected via programmable interconnect|
|US4899067 *||22 Jul 1988||6 Feb 1990||Altera Corporation||Programmable logic devices with spare circuits for use in replacing defective circuits|
|US4912342 *||14 Sep 1989||27 Mar 1990||Altera Corporation||Programmable logic device with array blocks with programmable clocking|
|US4940909 *||12 May 1989||10 Jul 1990||Plus Logic, Inc.||Configuration control circuit for programmable logic devices|
|US4975601 *||29 Sep 1989||4 Dic 1990||Sgs-Thomson Microelectronics, Inc.||User-writable random access memory logic block for programmable logic devices|
|US5042004 *||16 Ene 1990||20 Ago 1991||Advanced Micro Devices, Inc.||Programmable logic device with subroutine stack and random access memory|
|US5121006 *||22 Abr 1991||9 Jun 1992||Altera Corporation||Registered logic macrocell with product term allocation and adjacent product term stealing|
|US5241224 *||25 Abr 1991||31 Ago 1993||Altera Corporation||High-density erasable programmable logic device architecture using multiplexer interconnections|
|US5247478 *||6 Mar 1992||21 Sep 1993||Altera Corporation||Programmable transfer-devices|
|US5258668 *||8 May 1992||2 Nov 1993||Altera Corporation||Programmable logic array integrated circuits with cascade connections between logic modules|
|US5260610 *||3 Sep 1991||9 Nov 1993||Altera Corporation||Programmable logic element interconnections for programmable logic array integrated circuits|
|US5260611 *||8 May 1992||9 Nov 1993||Altera Corporation||Programmable logic array having local and long distance conductors|
|US5274600 *||13 Dic 1990||28 Dic 1993||Texas Instruments Incorporated||First-in first-out memory|
|US5294975 *||15 Oct 1992||15 Mar 1994||Altera Corporation||Laser alignment target for semiconductor integrated circuits|
|US5313119 *||28 Oct 1991||17 May 1994||Crosspoint Solutions, Inc.||Field programmable gate array|
|US5317212 *||19 Mar 1993||31 May 1994||Wahlstrom Sven E||Dynamic control of configurable logic|
|US5329460 *||1 Feb 1993||12 Jul 1994||Advanced Micro Devices, Inc.||Programmable gate array with improved interconnect structure, input/output structure and configurable logic block|
|US5338982 *||26 Mar 1992||16 Ago 1994||Kawasaki Steel Corporation||Programmable logic device|
|US5343406 *||28 Jul 1989||30 Ago 1994||Xilinx, Inc.||Distributed memory architecture for a configurable logic array and method for using distributed memory|
|US5343437 *||19 Feb 1993||30 Ago 1994||Motorola Inc.||Memory having nonvolatile and volatile memory banks|
|US5350954 *||29 Mar 1993||27 Sep 1994||Altera Corporation||Macrocell with flexible product term allocation|
|US5352940 *||27 May 1993||4 Oct 1994||Altera Corporation||Ram convertible look-up table based macrocell for PLDs|
|US5357132 *||8 Sep 1993||18 Oct 1994||Sgs-Thomson Microelectronics, Inc.||Dynamic random access memory cell|
|US5362999 *||18 Mar 1993||8 Nov 1994||Xilinx, Inc.||EPLD chip with hybrid architecture optimized for both speed and flexibility|
|US5365125 *||23 Jul 1992||15 Nov 1994||Xilinx, Inc.||Logic cell for field programmable gate array having optional internal feedback and optional cascade|
|US5375086 *||24 Ago 1993||20 Dic 1994||Wahlstrom; Sven E.||Dynamic control of configurable logic|
|US5406525 *||6 Jun 1994||11 Abr 1995||Motorola, Inc.||Configurable SRAM and method for providing the same|
|US5414377 *||18 Oct 1994||9 May 1995||Xilinx, Inc.||Logic block with look-up table for configuration and memory|
|US5432719 *||1 Ago 1994||11 Jul 1995||Xilinx, Inc.||Distributed memory architecture for a configurable logic array and method for using distribution memory|
|US5550782 *||18 May 1994||27 Ago 1996||Altera Corporation||Programmable logic array integrated circuits|
|US5560123 *||19 Feb 1993||1 Oct 1996||Valmet Paper Machinery Inc.||Method and device for ensuring the run of the web in the multi-cylinder dryer of a papermachine|
|US5570040 *||22 Mar 1995||29 Oct 1996||Altera Corporation||Programmable logic array integrated circuit incorporating a first-in first-out memory|
|US5572148 *||22 Mar 1995||5 Nov 1996||Altera Corporation||Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory|
|US5668771 *||24 May 1996||16 Sep 1997||Altera Corporation||Programmable logic array integrated circuits|
|US5804986 *||29 Dic 1995||8 Sep 1998||Cypress Semiconductor Corp.||Memory in a programmable logic device|
|US5809281 *||28 Ene 1997||15 Sep 1998||Altera Corporation||Field programmable gate array with high speed SRAM based configurable function block configurable as high performance logic or block of SRAM|
|*||USB14617479||Título no disponible|
|EP0410759A2 *||26 Jul 1990||30 Ene 1991||Xilinx, Inc.||Configurable logic array and method|
|EP0420389A1 *||29 Jun 1990||3 Abr 1991||SGS-THOMSON MICROELECTRONICS, INC. (a Delaware corp.)||Logic block for programmable logic devices|
|EP0507507A2 *||26 Mar 1992||7 Oct 1992||AT&T Corp.||Field programmable function element|
|JPH0191525A *||Título no disponible|
|WO1995016993A1 *||13 Dic 1994||22 Jun 1995||Lattice Semiconductor Corporation||Application specific modules in a programmable logic device|
|1||"AT&T's Orthogonal ORCA Targets the FPGA Future," 8029 Electronic Engineering, 64, No. 786, Jun. 1992, Woolwich, London, GB, pp. 9-10.|
|2||Actel Corp., "Actel's Reprogrammable SPGAs," Preliminary Advance Information, Oct. 10, 1996, pp. 1-25.|
|3||Actel Corp., "Integrator Series FPGAs 1200 XL and 3200DX Famile," Apr. 1996, pp. 1-7 to 1-72.|
|4||*||Actel Corp., Actel s Reprogrammable SPGAs, Preliminary Advance Information, Oct. 10, 1996, pp. 1 25.|
|5||*||Actel Corp., Integrator Series FPGAs 1200 XL and 3200DX Famile, Apr. 1996, pp. 1 7 to 1 72.|
|6||Altera Corp., "Configuring FLEX 10K Devices," Dec. 1995, Version 1, Application Note 59, pp. 1-24.|
|7||Altera Corp., "Embedded Programmable Logic Family FLEX 10K," Data Sheet, Jul. 1995, Version 1, pp. 1-55.|
|8||Altera Corp., "Implementing FIFO Buffers in FLEX 10K Devices," Jan. 1996, Version 1, Application Note 66, pp. 1-12.|
|9||Altera Corp., "Implementing RAM Functions in FLEX 10K Devices," Application Note 52, Nov. 1995, Version 1, pp. 1-8.|
|10||Altera Corp., "MAX 5000," Data Book, Aug. 1993, version 1, pp. 149-160, (presentation of the book included pp. iii-ix).|
|11||Altera Corp., "MAX 9000 Programmable Logic Device Family," Data Book, Mar. 1995, version 2, pp. 119-152, (Presentation of the book included pp. iii-viii).|
|12||*||Altera Corp., Configuring FLEX 10K Devices, Dec. 1995, Version 1, Application Note 59, pp. 1 24.|
|13||*||Altera Corp., Embedded Programmable Logic Family FLEX 10K, Data Sheet, Jul. 1995, Version 1, pp. 1 55.|
|14||*||Altera Corp., Implementing FIFO Buffers in FLEX 10K Devices, Jan. 1996, Version 1, Application Note 66, pp. 1 12.|
|15||*||Altera Corp., Implementing RAM Functions in FLEX 10K Devices, Application Note 52, Nov. 1995, Version 1, pp. 1 8.|
|16||*||Altera Corp., MAX 5000, Data Book, Aug. 1993, version 1, pp. 149 160, (presentation of the book included pp. iii ix).|
|17||*||Altera Corp., MAX 9000 Programmable Logic Device Family, Data Book, Mar. 1995, version 2, pp. 119 152, (Presentation of the book included pp. iii viii).|
|18||AT&T Microelectronics, "Optimized Reconfigurable Cell Array (ORCA) 2C Series Field-Programmable Gate Arrays (ATT2C12, ATT2C15, and ATT2C22)," Preliminary Data Sheet, Apr. 1994, pp. 1-103.|
|19||AT&T Microelectronics, "Optimized Reconfigurable Cell Array (ORCA) Series Field-Programmable Gate Arrays," Advance Data Sheet, Feb. 1993, pp. 1-87.|
|20||*||AT&T Microelectronics, Optimized Reconfigurable Cell Array (ORCA) 2C Series Field Programmable Gate Arrays (ATT2C12, ATT2C15, and ATT2C22), Preliminary Data Sheet, Apr. 1994, pp. 1 103.|
|21||*||AT&T Microelectronics, Optimized Reconfigurable Cell Array (ORCA) Series Field Programmable Gate Arrays, Advance Data Sheet, Feb. 1993, pp. 1 87.|
|22||*||AT&T s Orthogonal ORCA Targets the FPGA Future, 8029 Electronic Engineering, 64, No. 786, Jun. 1992, Woolwich, London, GB, pp. 9 10.|
|23||Bursky, Dave, "Denser, Faster FPGAs Vie for Gate-Array Applications," 2328 Electronic Design, 41, No. 11, May 27, 1993, Cleveland, OH, pp. 55-75.|
|24||Bursky, Dave, "FPGA Advances Cut Delays, Add Flexibility," Electronic Design, 40, No. 20, Oct. 1, 1992, Cleveland, OH, pp. 35-43.|
|25||Bursky, Dave, "Shrink Systems with One-Chip Decoder, EPROM, and RAM," Electronic Design, Jul. 28, 1988, pp. 91-94.|
|26||*||Bursky, Dave, Denser, Faster FPGAs Vie for Gate Array Applications, 2328 Electronic Design, 41, No. 11, May 27, 1993, Cleveland, OH, pp. 55 75.|
|27||*||Bursky, Dave, FPGA Advances Cut Delays, Add Flexibility, Electronic Design, 40, No. 20, Oct. 1, 1992, Cleveland, OH, pp. 35 43.|
|28||*||Bursky, Dave, Shrink Systems with One Chip Decoder, EPROM, and RAM, Electronic Design, Jul. 28, 1988, pp. 91 94.|
|29||Cartier. "Implementing FIFOs in XC4000E RAM". Xilinx, Inc., Oct. 9, 1995, pp. 1-15.|
|30||*||Cartier. Implementing FIFOs in XC4000E RAM . Xilinx, Inc., Oct. 9, 1995, pp. 1 15.|
|31||Chip Express Press Release, "Chip Express Announces Low-Production Volume ONEMASK® Gate Arrays Screened to Military Standard 883, Rapid-Turn Laser-Prototyping Used by the Military," Product & Services, Technical Press Releases, www.chipexpress.com/products/pressreleases/onemask.html, Santa Clara, CA, Aug. 21, 1995, pp. 1-2.|
|32||Chip Express Press Release, "Chip Express Unviels a 200,000 Gate LPGA Family with Configurable Embedded SRAM: The CX2000 New Gate Array Architecture Eases Deep Sub-micron Designs," www.chipexpress.com, corporate/pressreleases/cx2000.html, Las Vegas, NV, Jun. 3, 1996, one page.|
|33||Chip Express Press Release, "CX2000, 0.6μ High-Performance, Fast-Turn ASIC," www.chipexpress.com/products/datasheets/cx2000.htlm, Dec. 12, 1996, pp. 1-3.|
|34||Chip Express Press Release, "Technical Overview: RAM Block Diagrams," Product & Services, Technical Information, Nov. 25, 1996, www.chipexpress.com/products/appnotes/ramblock.htm., pp. 1-2.|
|35||Chip Express Press Release, "The Chip Express QYH500 Laser Gate Array (LPGA) Family Now Supports 3-Volt Custom Designs," Santa Clara, CA, May 17, 1996, www.chipexpress.com/corporate/pressreleases/voltage.html, one page.|
|36||*||Chip Express Press Release, Chip Express Announces Low Production Volume ONEMASK Gate Arrays Screened to Military Standard 883, Rapid Turn Laser Prototyping Used by the Military, Product & Services, Technical Press Releases, www.chipexpress.com/products/pressreleases/onemask.html, Santa Clara, CA, Aug. 21, 1995, pp. 1 2.|
|37||*||Chip Express Press Release, Chip Express Unviels a 200,000 Gate LPGA Family with Configurable Embedded SRAM: The CX2000 New Gate Array Architecture Eases Deep Sub micron Designs, www.chipexpress.com, corporate/pressreleases/cx2000.html, Las Vegas, NV, Jun. 3, 1996, one page.|
|38||*||Chip Express Press Release, CX2000, 0.6 High Performance, Fast Turn ASIC, www.chipexpress.com/products/datasheets/cx2000.htlm, Dec. 12, 1996, pp. 1 3.|
|39||*||Chip Express Press Release, Technical Overview: RAM Block Diagrams, Product & Services, Technical Information, Nov. 25, 1996, www.chipexpress.com/products/appnotes/ramblock.htm., pp. 1 2.|
|40||*||Chip Express Press Release, The Chip Express QYH500 Laser Gate Array (LPGA) Family Now Supports 3 Volt Custom Designs, Santa Clara, CA, May 17, 1996, www.chipexpress.com/corporate/pressreleases/voltage.html, one page.|
|41||Dave Bursky, "Combination RAM/PLD Opens New Application Options, Packing 2048 Bits Of RAM Plus Four 500-Gate Configurable Logic Blocks Lets An EPLD Compete With Standard Cells, Arrays," Product Innovation, Electronic Design, May 23, 1991, pp. 138 and 140.|
|42||Dave Bursky, "CPDLs Add Dedicated Memory Counters To Up Performance," Electronic Design, Mar. 4, 1996, pp. 141-142.|
|43||*||Dave Bursky, Combination RAM/PLD Opens New Application Options, Packing 2048 Bits Of RAM Plus Four 500 Gate Configurable Logic Blocks Lets An EPLD Compete With Standard Cells, Arrays, Product Innovation, Electronic Design, May 23, 1991, pp. 138 and 140.|
|44||*||Dave Bursky, CPDLs Add Dedicated Memory Counters To Up Performance, Electronic Design, Mar. 4, 1996, pp. 141 142.|
|45||EDN Design Feature, "Embedded Memory Enhances Programmable Logic For Complex, Compact Designs," Nov. 7, 1996, pp. 91, 92, 94, 96, 98, 100, 101, 102, 106.|
|46||*||EDN Design Feature, Embedded Memory Enhances Programmable Logic For Complex, Compact Designs, Nov. 7, 1996, pp. 91, 92, 94, 96, 98, 100, 101, 102, 106.|
|47||Kawana, Keiichi et al., "An Efficient Logic Block Interconnect Architecture for User-Reprogrammable Gate Array," IEEE 1990 Custom Integrated Circuits Conference, May 1990, CH2860-5/90/0000-0164, pp. 31.3.1-4.|
|48||*||Kawana, Keiichi et al., An Efficient Logic Block Interconnect Architecture for User Reprogrammable Gate Array, IEEE 1990 Custom Integrated Circuits Conference, May 1990, CH2860 5/90/0000 0164, pp. 31.3.1 4.|
|49||Landry, Steve, "Application-Specific ICs, Relying on RAM, Implement Almost Any Logic Function," Electronic Design, Oct. 31, 1985, pp. 123-130.|
|50||*||Landry, Steve, Application Specific ICs, Relying on RAM, Implement Almost Any Logic Function, Electronic Design, Oct. 31, 1985, pp. 123 130.|
|51||Lattice Semiconductor Corp., "6000 Family Architectural Description," 1996, Data Book, pp. 2-39 to 2-41.|
|52||Lattice Semiconductor Corp., "ispLSI and pLSI 6192, High Density Programmable Logic With Dedicated Memory and Register/Counter Modules," 1996, Data Book, pp. 2-287 to 2-347.|
|53||*||Lattice Semiconductor Corp., 6000 Family Architectural Description, 1996, Data Book, pp. 2 39 to 2 41.|
|54||*||Lattice Semiconductor Corp., ispLSI and pLSI 6192, High Density Programmable Logic With Dedicated Memory and Register/Counter Modules, 1996, Data Book, pp. 2 287 to 2 347.|
|55||Masumoto, Rodney T., "Configurable On-Chip RAM Incorporated into High Speed Logic Array," IEEE Custom Integrated Circuits Conference, Jun. 1985, CH2157-6/85/0000-0240, pp. 240-243.|
|56||*||Masumoto, Rodney T., Configurable On Chip RAM Incorporated into High Speed Logic Array, IEEE Custom Integrated Circuits Conference, Jun. 1985, CH2157 6/85/0000 0240, pp. 240 243.|
|57||*||Ngai, Kai Kit Tony, An SRAM Programmable Field Reconfigurable Memory, UMI Dissertation Services, Jun. 1994, University of Toronto, pp. i 68.|
|58||Ngai, Kai-Kit Tony, "An SRAM-Programmable Field-Reconfigurable Memory," UMI Dissertation Services, Jun. 1994, University of Toronto, pp. i-68.|
|59||Plus Logic "FPSL5110 Intelligent Data Buffer" Product Brief, Plus Logic, Inc., San Jose, California, Oct. 1990, pp. 1-6.|
|60||*||Plus Logic FPSL5110 Intelligent Data Buffer Product Brief, Plus Logic, Inc., San Jose, California, Oct. 1990, pp. 1 6.|
|61||Plus Logic, "FPSL5110 Intelligent Data Buffer," Data Sheet, pp. 1-3.|
|62||*||Plus Logic, FPSL5110 Intelligent Data Buffer, Data Sheet, pp. 1 3.|
|63||Shubat, Alexander et al., "A Family of User-Programmable Peripherals with a Functional Unit Architecture," IEEE Jor. of Solid-State Circuits, vol. 27, No. 4, Apr. 1992, 0018-9200/92$03.00, pp. 515-529.|
|64||*||Shubat, Alexander et al., A Family of User Programmable Peripherals with a Functional Unit Architecture, IEEE Jor. of Solid State Circuits, vol. 27, No. 4, Apr. 1992, 0018 9200/92$03.00, pp. 515 529.|
|65||Smith, Daniel, "Intel's FLEXlogic FPGA Architecture," IEEE 1063-6390/93, Wilton , 1993 pp. 378-384.|
|66||*||Smith, Daniel, Intel s FLEXlogic FPGA Architecture, IEEE 1063 6390/93, Wilton 29 , 1993 pp. 378 384.|
|67||Xilinx Corp., "XC4000, XC4000A, XC4000H Logic Cell Array Families," 1994, Revised Apr. 1995, pp. 2-7 to 2-102 (Presentation of the book included).|
|68||*||Xilinx Corp., XC4000, XC4000A, XC4000H Logic Cell Array Families, 1994, Revised Apr. 1995, pp. 2 7 to 2 102 (Presentation of the book included).|
|Patente citante||Fecha de presentación||Fecha de publicación||Solicitante||Título|
|US6242946 *||5 Ago 1999||5 Jun 2001||Altera Corporation||Embedded memory block with FIFO mode for programmable logic device|
|US6255848 *||13 Ago 1999||3 Jul 2001||Xilinx, Inc.||Method and structure for reading, modifying and writing selected configuration memory cells of an FPGA|
|US6262596 *||13 Ago 1999||17 Jul 2001||Xilinx, Inc.||Configuration bus interface circuit for FPGAS|
|US6265895 *||15 Mar 2000||24 Jul 2001||Altera Corporation||Programmable logic device incorporating a memory efficient interconnection device|
|US6266746 *||22 Jul 1998||24 Jul 2001||Yamaha Corporation||Control apparatus for random access memories|
|US6388464 *||30 Dic 1999||14 May 2002||Cypress Semiconductor Corp.||Configurable memory for programmable logic circuits|
|US6429682||25 May 2001||6 Ago 2002||Xilinx, Inc.||Configuration bus interface circuit for FPGAs|
|US6433578||5 May 2000||13 Ago 2002||Morphics Technology, Inc.||Heterogeneous programmable gate array|
|US6467017 *||29 Jul 1998||15 Oct 2002||Altera Corporation||Programmable logic device having embedded dual-port random access memory configurable as single-port memory|
|US6512395||18 Dic 2001||28 Ene 2003||Cypress Semiconductor Corp.||Configurable memory for programmable logic circuits|
|US6593772 *||19 Jun 2002||15 Jul 2003||Altera Corporation||Embedded memory blocks for programmable logic|
|US6608500||31 Mar 2000||19 Ago 2003||Cypress Semiconductor Corp.||I/O architecture/cell design for programmable logic device|
|US6732068 *||2 Ago 2001||4 May 2004||Quickturn Design Systems Inc.||Memory circuit for use in hardware emulation system|
|US6765408 *||26 Abr 2002||20 Jul 2004||Lattice Semiconductor Corporation||Device and method with generic logic blocks|
|US6864710 *||30 Dic 1999||8 Mar 2005||Cypress Semiconductor Corp.||Programmable logic device|
|US6903573||14 Jul 2003||7 Jun 2005||Lattice Semiconductor Corporation||Programmable logic device with enhanced wide input product term cascading|
|US6912164 *||22 Ago 2003||28 Jun 2005||Altera Corporation||Techniques for preloading data into memory on programmable circuits|
|US6915323||13 Feb 2003||5 Jul 2005||Lattice Semiconductor Corporation||Macrocells supporting a carry cascade|
|US7360026 *||6 Oct 2003||15 Abr 2008||Altera Corporation||Method and apparatus for synchronizing data with a reduced clock cycle response time|
|US7463544||2 Jun 2003||9 Dic 2008||Altera Corporation||Device programmable to operate as a multiplexer, demultiplexer, or memory device|
|US7606081||19 Nov 2008||20 Oct 2009||Altera Corporation||Device programmable to operate as a multiplexer, demultiplexer, or memory device|
|US7737724||27 Dic 2007||15 Jun 2010||Cypress Semiconductor Corporation||Universal digital block interconnection and channel routing|
|US7761845||9 Sep 2002||20 Jul 2010||Cypress Semiconductor Corporation||Method for parameterizing a user module|
|US7765095||1 Nov 2001||27 Jul 2010||Cypress Semiconductor Corporation||Conditional branching in an in-circuit emulation system|
|US7768430 *||20 May 2008||3 Ago 2010||Altera Corporation||Look-up table based memory|
|US7770113||19 Nov 2001||3 Ago 2010||Cypress Semiconductor Corporation||System and method for dynamically generating a configuration datasheet|
|US7774190||19 Nov 2001||10 Ago 2010||Cypress Semiconductor Corporation||Sleep and stall in an in-circuit emulation system|
|US7796464||7 Jun 2004||14 Sep 2010||Cypress Semiconductor Corporation||Synchronous memory with a shadow-cycle counter|
|US7825688||30 Abr 2007||2 Nov 2010||Cypress Semiconductor Corporation||Programmable microcontroller architecture(mixed analog/digital)|
|US7844437||19 Nov 2001||30 Nov 2010||Cypress Semiconductor Corporation||System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit|
|US7893724||13 Nov 2007||22 Feb 2011||Cypress Semiconductor Corporation||Method and circuit for rapid alignment of signals|
|US7893772||3 Dic 2008||22 Feb 2011||Cypress Semiconductor Corporation||System and method of loading a programmable counter|
|US8026739||27 Dic 2007||27 Sep 2011||Cypress Semiconductor Corporation||System level interconnect with programmable switching|
|US8040266||31 Mar 2008||18 Oct 2011||Cypress Semiconductor Corporation||Programmable sigma-delta analog-to-digital converter|
|US8049569||5 Sep 2007||1 Nov 2011||Cypress Semiconductor Corporation||Circuit and method for improving the accuracy of a crystal-less oscillator having dual-frequency modes|
|US8067948||21 Feb 2007||29 Nov 2011||Cypress Semiconductor Corporation||Input/output multiplexer bus|
|US8069405||19 Nov 2001||29 Nov 2011||Cypress Semiconductor Corporation||User interface for efficiently browsing an electronic document using data-driven tabs|
|US8069428||12 Jun 2007||29 Nov 2011||Cypress Semiconductor Corporation||Techniques for generating microcontroller configuration information|
|US8069436||10 Ago 2005||29 Nov 2011||Cypress Semiconductor Corporation||Providing hardware independence to automate code generation of processing device firmware|
|US8078894||27 Mar 2008||13 Dic 2011||Cypress Semiconductor Corporation||Power management architecture, method and configuration system|
|US8078970||9 Nov 2001||13 Dic 2011||Cypress Semiconductor Corporation||Graphical user interface with user-selectable list-box|
|US8085067||21 Dic 2006||27 Dic 2011||Cypress Semiconductor Corporation||Differential-to-single ended signal converter circuit and method|
|US8085100||19 Feb 2008||27 Dic 2011||Cypress Semiconductor Corporation||Poly-phase frequency synthesis oscillator|
|US8092083||1 Oct 2007||10 Ene 2012||Cypress Semiconductor Corporation||Temperature sensor with digital bandgap|
|US8103496||1 Nov 2001||24 Ene 2012||Cypress Semicondutor Corporation||Breakpoint control in an in-circuit emulation system|
|US8103497||28 Mar 2002||24 Ene 2012||Cypress Semiconductor Corporation||External interface for event architecture|
|US8120408||14 Jul 2008||21 Feb 2012||Cypress Semiconductor Corporation||Voltage controlled oscillator delay cell and method|
|US8130025||17 Abr 2008||6 Mar 2012||Cypress Semiconductor Corporation||Numerical band gap|
|US8149048||29 Ago 2001||3 Abr 2012||Cypress Semiconductor Corporation||Apparatus and method for programmable power management in a programmable analog circuit block|
|US8176296||22 Oct 2001||8 May 2012||Cypress Semiconductor Corporation||Programmable microcontroller architecture|
|US8358150||11 Oct 2010||22 Ene 2013||Cypress Semiconductor Corporation||Programmable microcontroller architecture(mixed analog/digital)|
|US8370791||3 Jun 2008||5 Feb 2013||Cypress Semiconductor Corporation||System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit|
|US8402313||20 Nov 2007||19 Mar 2013||Cypress Semiconductor Corporation||Reconfigurable testing system and method|
|US8476928||3 Ago 2011||2 Jul 2013||Cypress Semiconductor Corporation||System level interconnect with programmable switching|
|US8482313||2 May 2011||9 Jul 2013||Cypress Semiconductor Corporation||Universal digital block interconnection and channel routing|
|US8499270||28 Jun 2011||30 Jul 2013||Cypress Semiconductor Corporation||Configuration of programmable IC design elements|
|US8516025||16 Abr 2008||20 Ago 2013||Cypress Semiconductor Corporation||Clock driven dynamic datapath chaining|
|US8527949||13 Jul 2011||3 Sep 2013||Cypress Semiconductor Corporation||Graphical user interface for dynamically reconfiguring a programmable device|
|US8533677||27 Sep 2002||10 Sep 2013||Cypress Semiconductor Corporation||Graphical user interface for dynamically reconfiguring a programmable device|
|US8555032||27 Jun 2011||8 Oct 2013||Cypress Semiconductor Corporation||Microcontroller programmable system on a chip with programmable interconnect|
|US8717042||29 Nov 2011||6 May 2014||Cypress Semiconductor Corporation||Input/output multiplexer bus|
|US8736303||16 Dic 2011||27 May 2014||Cypress Semiconductor Corporation||PSOC architecture|
|US8793635||28 Nov 2011||29 Jul 2014||Cypress Semiconductor Corporation||Techniques for generating microcontroller configuration information|
|US8909960||8 Jul 2011||9 Dic 2014||Cypress Semiconductor Corporation||Power management architecture, method and configuration system|
|US9448964||22 Abr 2010||20 Sep 2016||Cypress Semiconductor Corporation||Autonomous control in a programmable system|
|US9564902||31 Dic 2007||7 Feb 2017||Cypress Semiconductor Corporation||Dynamically configurable and re-configurable data path|
|US9594723 *||13 Mar 2013||14 Mar 2017||Altera Corporation||Apparatus, system and method for configuration of adaptive integrated circuitry having fixed, application specific computational elements|
|US20020161568 *||2 Ago 2001||31 Oct 2002||Quickturn Design Systems, Inc.||Memory circuit for use in hardware emulation system|
|US20040000928 *||26 Abr 2002||1 Ene 2004||Lattice Semiconductor Corporation||Device and method with generic logic blocks|
|US20040238809 *||1 Jul 2002||2 Dic 2004||Pavel Adamec||Electron emission device|
|US20080024165 *||28 Jul 2006||31 Ene 2008||Raminda Udaya Madurawe||Configurable embedded multi-port memory|
|US20080218207 *||29 Abr 2008||11 Sep 2008||Actel Corporation||Synchronous first-in/first-out block memory for a field programmable gate array|
|US20130304960 *||13 Mar 2013||14 Nov 2013||Altera Corporation||Apparatus, System and Method For Configuration of Adaptive Integrated Circuitry Having Fixed, Application Specific Computational Elements|
|WO2000069073A1 *||5 May 2000||16 Nov 2000||Morphics Technology Inc.||Heterogeneous programmable gate array|
|Clasificación de EE.UU.||326/40, 326/41|
|Clasificación cooperativa||H03K19/1776, H03K19/17704|
|Clasificación europea||H03K19/177H3, H03K19/177B|
|16 Abr 1997||AS||Assignment|
Owner name: ALTERA CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:VEENSTRA, KERRY S.;REEL/FRAME:008522/0838
Effective date: 19970411
|20 Mar 1998||AS||Assignment|
Owner name: ALTERA CORPORATION, A DELAWARE CORP., CALIFORNIA
Free format text: MERGER;ASSIGNOR:ALTERA COPORATION, A CALIFORNIA CORP.;REEL/FRAME:009056/0393
Effective date: 19970325
|31 Mar 2003||FPAY||Fee payment|
Year of fee payment: 4
|21 May 2003||REMI||Maintenance fee reminder mailed|
|20 Mar 2007||FPAY||Fee payment|
Year of fee payment: 8
|22 Abr 2011||FPAY||Fee payment|
Year of fee payment: 12