US5994783A - Semiconductor chip package and fabrication method thereof - Google Patents

Semiconductor chip package and fabrication method thereof Download PDF

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Publication number
US5994783A
US5994783A US08/923,817 US92381797A US5994783A US 5994783 A US5994783 A US 5994783A US 92381797 A US92381797 A US 92381797A US 5994783 A US5994783 A US 5994783A
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chip
package
chip package
conductive
semiconductor chip
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US08/923,817
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Joong Ha You
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SK Hynix Inc
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LG Semicon Co Ltd
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Priority to US09/416,272 priority Critical patent/US6277670B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors

Definitions

  • FIG. 2 is a cross-sectional view of a bump electrode in FIG. 1.
  • the chip pads 12 are formed on the top surface of the semiconductor chip 11, and a passivation film 18 is formed on the semiconductor chip 11, except on the top surface of the chip pads 12.
  • the metal wiring pattern 13 is formed on the chip passivation film 18, wherein one end of the metal wiring pattern 13 is connected to the chip pad 12 and the other end thereof 13 is connected to the internal bump bonding pad 17.
  • a polyimide film 10 is formed on the above construction, except at the internal bump connecting pads 17, and the internal bumps 16 are attached to the exposed internal bump connecting pads 17 by means of a solder adhesive 20 composed of Pb or Sn.
  • a molding resin 14 encapsulates the semiconductor chip 11 by surrounding the same on the entire surface of the above construction except for the top surface of the internal bumps 16, and the external bumps 15 are attached to the internal bumps 16.
  • An object of the present invention is to solve the problems of the related art.
  • An object of the present invention is to minimize the size of a semiconductor package.
  • Another object of the present invention is to simplify the fabrication process.
  • Still another object of the present invention is to form the shortest conductive or electrical path for transmitting signals sent from the chip pads of the integrated circuit.
  • an improved fabrication method for making a semiconductor package comprising the steps of forming a passivation film on a first surface of a wafer such that a plurality of chip pads of the wafer are exposed; forming a metal layer on the passivation film; forming a patterned photoresist layer on the metal layer, etching the metal layer by using the photoresist layer as a mask, stripping the photoresist layer and forming a patterned metal wiring conductively coupled to the plurality of chip pads; printing a solder paste on each metal wiring, mounting a solder ball, performing an infrared reflow process, removing a remaining solder paste, and attaching the solder ball serving as an external ball to each metal wiring; forming a molding resin layer on the wafer and metal wiring by performing a first molding process with a resin such that an upper portion of the solder ball is exposed; carrying out a foil mounting on a second surface of the wafer; and cutting the wafer into a semiconductor chip
  • the present invention may be achieved in whole or in part by a method for fabricating a chip package comprising the steps of: a) forming a passivation film on a wafer having a plurality of individual integrated chips with a plurality of chip pads exposed on a first surface of the plurality of individual integrated chips; b) forming a plurality of conductive wires on the first surface of each individual integrated chip to couple corresponding chip pads to corresponding conductive wires; c) forming a plurality of conductive media, each having a first prescribed height and a corresponding conductive media being formed on a corresponding conductive wires of each individual integrated chip; and d) forming a molding layer on the plurality of conductive wires, the molding layer having a prescribed thickness which is less than the prescribed height such that portions of the plurality of conductive media protrude from the molding layer of each individual integrated chip.
  • FIG. 2 is a cross-sectional view showing a portion of a bump electrode in FIG. 1 according to the related art
  • FIG. 3 is a perspective view showing a partly cut away chip-size semiconductor package according to an embodiment of the present invention.
  • FIG. 5 is a perspective view showing a partly cut away chip-size semiconductor package according to another embodiment of the present invention in FIG. 3;
  • FIG. 6 is a flow chart for explaining the process of a fabrication method for a chip-size semiconductor package according to an embodiment of the present invention
  • FIG. 7 is a perspective view showing a partly cut away chip-size semiconductor package according to another embodiment of the present invention.
  • FIG. 9 is a perspective view showing a partly cut away chip-size semiconductor package according to another embodiment of the present invention in FIG. 7;
  • FIG. 10 is a flow chart for explaining the process of a fabrication method for the chip-size semiconductor package according to another embodiment of the present invention.
  • FIGS. 4A and 4B are longitudinal cross-sectional views showing a partly portion of FIG. 3, wherein FIG. 4A is a longitudinal cross-sectional view of a chip pad and FIG. 4B is that of an external ball.
  • the passivation film 33 is formed in such a manner that the chip pad 32 formed on the upper surface of the semiconductor chip 31 is exposed, and the metal wiring 34 connected to the chip pad 32 is formed on the passivation film 33 with the external ball 36 attached to the metal wiring 34.
  • the molding resin layer 35 for protecting the metal wiring 34 and the chip pad 31 is formed on the upper portion of the semiconductor chip 31, the molding resin layer 35 for protecting the metal wiring 34 and the chip pad 31 is formed.
  • the molding resin lay 35 has a thickness of about half the height of the external balls 36.
  • FIG. 5 is a perspective view showing a partly cut away chip-size semiconductor package according to another embodiment of the present invention in FIG. 3.
  • the semiconductor chip 31 is attached to an inner bottom surface of an outer protection member or plate 38 in the shape of a cavity or a recess, and a resin 37 seals the gap between the sides of the semiconductor chip 31 and the outer protection plate 38.
  • the outer protection plate 38 is preferable since it protects the bottom surface and sides of the semiconductor chip 31.
  • the other structures of the elements are the same as that of FIG. 3.
  • a first molding process is carried out to form a molding resin layer having a thickness of about half the height of the solder ball.
  • a foil mounting process is performed on the bottom of the wafer, and then a sawing process of cutting the wafer into an individual semiconductor chip is performed.
  • the foil is removed to complete a chip-size semiconductor package shown in FIG. 3
  • the first molding process can be carried out after the sawing process is performed.
  • a chip-size semiconductor package shown in FIG. 3 can be applied to many uses which do not require sensitive thermal characteristics.
  • a die bonding process for attaching the bottom surface of each semiconductor chip to the inner bottom surface of the outer protection plate having a cavity or a recess shape and a second molding process for sealing the gap between the sides of the semiconductor chip and the outer protection plate with a molding resin are carried out to complete a chip-size semiconductor package in FIG. 5.
  • the first molding process can be performed together with the second molding process.
  • the chip-size semiconductor package in FIG. 5 has an improved thermal characteristic due to a safe protection of the surface of the semiconductor chip, resulting in enhancing a reliability of the package.
  • An inner end of the external ball 48 is attached to the metal wiring 44 electrically connected to the chip pad 42, and the molding resin layer 43 is formed to protect the metal wiring 44 and the chip pad 42 in such a manner that an outer end of the external ball 48 protrudes out of the molding resin layer 43.
  • FIG. 10 is a flow chart of the method for fabricating the chip-size semiconductor package according to another embodiment of the present invention.
  • a wafer is prepared on which a passivation film (Passivation+PIQ or Passivation only) is formed in such a manner that a plurality of chip pads are exposed.
  • a foil mounting is performed on the bottom surface of the wafer, and a sawing process is carried out to cut the wafer into an individual semiconductor chip.
  • a separate metal wiring layer is attached to the semiconductor chip with an adherent, and then a metal deposition process is performed to connect each metal wiring and chip pad formed on the semiconductor chip.
  • the external solder wire is shaped into a ball by carrying out an infrared reflow process, and a residual solder paste is removed. A final check is performed to complete a chip-size semiconductor package in FIG. 7. Such a chip-size semiconductor package can be applied to many uses which do not require sensitive thermal characteristics.
  • a die bonding process is performed such that the bottom surface of each semiconductor chip is attached to the inner bottom surface of the external protection plate in the shape of a cavity or recess.
  • a second molding process is carried out such that the gap between the external protection plate and the semiconductor chip is completely sealed with a molding resin. Then, a final test is conducted to complete a chip-size semiconductor package of FIG. 9. The reliability of the semiconductor package of FIG. 9 can be enhanced since the surface of the semiconductor chip is safely protected and consequently the thermal characteristic is improved.
  • the chip-size semiconductor package and the fabrication method thereof according to an embodiment of the present invention has the advantages as follows:
  • the fabrication method is simplified. Since the arrangement of the external balls can be made irrespective of the position of the chip pads, the design of the package can be made easy. Further, since the size of the semiconductor package which is nearly the chip size can be fabricated, the mounting rate can be advantageously raised to the maximum, and a plurality of external balls can be effectively formed.

Abstract

A chip package according to an embodiment of the present invention includes an integrated chip having a plurality of chip pads formed thereon, and a passivation film formed in such a manner that the chip pads are exposed. A plurality of metal wirings are connected to the chip pads on the upper surface of the passivation film, and externals balls electrically connected to the metal wirings. A molding resin layer is formed on the upper portion of the semiconductor chip such that the upper surfaces of the external balls protrude therefrom.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a package and a fabrication method thereof, and in particular, to an improved integrated chip package and the fabrication method thereof.
2. Background of the Related Art
FIG. 1 is a perspective view showing a partly cut away PMEB (Plastic Molded Extended Bump) type chip-size semiconductor package. As shown in this drawing, a metal wiring pattern 13 is formed to connect a plurality of chip pads 12 formed on the semiconductor chip 11 with internal bump bonding pads 17. Conductive internal bumps 16 are attached on the internal bump bonding pad 17 and tapes (not shown) are attached to the top surfaces of the conductive internal bumps 16. Then the semiconductor chip 11 is surrounded and molded with a molding resin 14. When the tapes are removed, the top surfaces of the internal bumps 16 are exposed. A solder paste is applied on the internal bumps 16, external electrode bumps 15 are placed thereon and the external bumps 15 and the internal bumps 16 are attached through an infrared reflow process, resulting in a completed PMEB-type chip-size semiconductor package, a description of which was published at the "SEMICON JAPAN '94 SYMPOSIUM" held by the MITSUBISHI corporation in Japan.
FIG. 2 is a cross-sectional view of a bump electrode in FIG. 1. The chip pads 12 are formed on the top surface of the semiconductor chip 11, and a passivation film 18 is formed on the semiconductor chip 11, except on the top surface of the chip pads 12. The metal wiring pattern 13 is formed on the chip passivation film 18, wherein one end of the metal wiring pattern 13 is connected to the chip pad 12 and the other end thereof 13 is connected to the internal bump bonding pad 17. A polyimide film 10 is formed on the above construction, except at the internal bump connecting pads 17, and the internal bumps 16 are attached to the exposed internal bump connecting pads 17 by means of a solder adhesive 20 composed of Pb or Sn. A molding resin 14 encapsulates the semiconductor chip 11 by surrounding the same on the entire surface of the above construction except for the top surface of the internal bumps 16, and the external bumps 15 are attached to the internal bumps 16.
As described above, a bump bonding pattern for transmitting an electrical signal of the chip pads 12 to the external bumps 15 is formed through a separate formation process of a metal wiring pattern (a pre-assembly process). The metal wiring pattern 13 is formed from the chip pads 12 of the semiconductor chip 11 to the internal bump connecting pads 17 to be electrically connected, respectively, and the conductive internal bumps 16 are attached to the internal bump connecting pads 17. The molding resin 14 surrounds and seals the above entire construction, and the external bumps 15, serving as external leads, are attached to the internal bumps 16 to form a completed chip-size semiconductor package. Although the PMEB-type chip-size semiconductor package allows the overall size of the entire semiconductor package to be smaller, a separate formation process for the metal wiring pattern (pre-assembly process in the published data) and an bonding process for internal and external bumps are necessary. Further, the fabrication process is complicated and the fabrication cost is increased.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
SUMMARY OF THE INVENTION
An object of the present invention is to solve the problems of the related art.
An object of the present invention is to minimize the size of a semiconductor package.
Another object of the present invention is to facilitate the provision of numerous pins of a package.
Another object of the present invention is to simplify the fabrication process.
A further object of the present invention is to enhance the electrical characteristics of the chip package.
Still another object of the present invention is to form the shortest conductive or electrical path for transmitting signals sent from the chip pads of the integrated circuit.
To achieve the above object, there is provided a semiconductor chip package, comprising a semiconductor chip having a plurality of chip pads formed thereon; a passivation film formed on the semiconductor chip with the chip pads exposed; a plurality of metal wirings coupled to the chip pads on the passivation film; external balls electrically connected to the metal wirings; and a molding resin layer formed on a first surface of the semiconductor chip such that upper portions of the external balls protrude from the molding resin layer.
To achieve the above object, there is provided an improved fabrication method for making a semiconductor package, comprising the steps of forming a passivation film on a first surface of a wafer such that a plurality of chip pads of the wafer are exposed; forming a metal layer on the passivation film; forming a patterned photoresist layer on the metal layer, etching the metal layer by using the photoresist layer as a mask, stripping the photoresist layer and forming a patterned metal wiring conductively coupled to the plurality of chip pads; printing a solder paste on each metal wiring, mounting a solder ball, performing an infrared reflow process, removing a remaining solder paste, and attaching the solder ball serving as an external ball to each metal wiring; forming a molding resin layer on the wafer and metal wiring by performing a first molding process with a resin such that an upper portion of the solder ball is exposed; carrying out a foil mounting on a second surface of the wafer; and cutting the wafer into a semiconductor chip package.
To achieve such objects, advantages and features in part or in whole, the present invention includes a chip package, comprising an integrated chip having a plurality of chip pads on a first surface; a passivation film formed on the first surface of the integrated chip with the plurality of chip pads exposed; a plurality of conductive wires formed on the passivation film such that a corresponding conductive wire is conductively coupled to a corresponding chip pad; a plurality of conductive media, each having a first prescribed height and a corresponding conductive media being formed on a corresponding conductive wire; and a molding layer formed on the plurality of conductive wires, the molding layer having a prescribed thickness which is less than the prescribed height such that portions of the plurality of conductive media protrude from the molding layer.
The present invention may be achieved in whole or in part by a method for fabricating a chip package comprising the steps of: a) forming a passivation film on a wafer having a plurality of individual integrated chips with a plurality of chip pads exposed on a first surface of the plurality of individual integrated chips; b) forming a plurality of conductive wires on the first surface of each individual integrated chip to couple corresponding chip pads to corresponding conductive wires; c) forming a plurality of conductive media, each having a first prescribed height and a corresponding conductive media being formed on a corresponding conductive wires of each individual integrated chip; and d) forming a molding layer on the plurality of conductive wires, the molding layer having a prescribed thickness which is less than the prescribed height such that portions of the plurality of conductive media protrude from the molding layer of each individual integrated chip.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention will be described in detail with reference to the following drawings in which like reference numerals refer to like elements wherein:
FIG. 1 is a perspective view showing the partly cut away PMEB (Plastic Molded Extended Bump) type chip-size semiconductor package according to the related art;
FIG. 2 is a cross-sectional view showing a portion of a bump electrode in FIG. 1 according to the related art;
FIG. 3 is a perspective view showing a partly cut away chip-size semiconductor package according to an embodiment of the present invention;
FIGS. 4A and 4B are longitudinal cross-sectional views of FIG. 3, wherein FIG. 4A is a longitudinal cross-sectional view of a chip pad and FIG. 4B is that of an external ball according to an embodiment of the present invention;
FIG. 5 is a perspective view showing a partly cut away chip-size semiconductor package according to another embodiment of the present invention in FIG. 3;
FIG. 6 is a flow chart for explaining the process of a fabrication method for a chip-size semiconductor package according to an embodiment of the present invention;
FIG. 7 is a perspective view showing a partly cut away chip-size semiconductor package according to another embodiment of the present invention;
FIGS. 8A and 8B are longitudinal cross-sectional views of FIG. 7, wherein FIG. 8A is a longitudinal cross-sectional view of a chip pad and FIG. 8B is that of an external ball according to another embodiment of the present invention;
FIG. 9 is a perspective view showing a partly cut away chip-size semiconductor package according to another embodiment of the present invention in FIG. 7; and
FIG. 10 is a flow chart for explaining the process of a fabrication method for the chip-size semiconductor package according to another embodiment of the present invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
FIG. 3 is a perspective view showing a partly cut away chip-size semiconductor package according to an embodiment of the present invention. As shown in this drawing, a plurality of chip pads 32 is formed on the upper surface of an integrated chip, i.e., a semiconductor chip, and a passivation film 33 is formed in such a manner that the chip pads 32 are exposed. A plurality of metal wirings 34 connected to the chip pads 32 are formed on the passivation film. On the metal wirings, external balls 36 are conductively coupled, e.g., electrically connected, to the metal wirings. A molding layer 35 of, e.g., resin, is formed on the upper surface of the semiconductor chip 31 such that the upper portions of the external balls 36 protrude therefrom. A preferred material for the metal wiring 34 is copper (Cu) or gold (Au).
FIGS. 4A and 4B are longitudinal cross-sectional views showing a partly portion of FIG. 3, wherein FIG. 4A is a longitudinal cross-sectional view of a chip pad and FIG. 4B is that of an external ball. As shown in these drawings, the passivation film 33 is formed in such a manner that the chip pad 32 formed on the upper surface of the semiconductor chip 31 is exposed, and the metal wiring 34 connected to the chip pad 32 is formed on the passivation film 33 with the external ball 36 attached to the metal wiring 34. On the upper portion of the semiconductor chip 31, the molding resin layer 35 for protecting the metal wiring 34 and the chip pad 31 is formed. Preferably, the molding resin lay 35 has a thickness of about half the height of the external balls 36.
FIG. 5 is a perspective view showing a partly cut away chip-size semiconductor package according to another embodiment of the present invention in FIG. 3. As shown in this drawing, the semiconductor chip 31 is attached to an inner bottom surface of an outer protection member or plate 38 in the shape of a cavity or a recess, and a resin 37 seals the gap between the sides of the semiconductor chip 31 and the outer protection plate 38. The outer protection plate 38 is preferable since it protects the bottom surface and sides of the semiconductor chip 31. The other structures of the elements are the same as that of FIG. 3.
FIG. 6 is a flow chart of the method for fabricating a chip-size semiconductor package according to an embodiment of the present invention. First, a passivation film is formed on a wafer so that a plurality of chip pads are exposed and the wafer is prepared for testing. Then, a metal layer is formed on the upper surface of the wafer, and a patterned photoresist layer is formed thereon. The metal layer is etched using the photoresist layer as a mask, and then the photoresist layer is stripped, resulting in the formation of a patterned metal wiring electrically connected to each chip pad.
Next, solder pastes are printed on each metal wiring to mount solder balls (external balls), and an infrared rays reflow is performed. Then, a residual paste is rinsed and the solder balls serving as an external ball are attached to each metal wiring.
A first molding process is carried out to form a molding resin layer having a thickness of about half the height of the solder ball. Next, a foil mounting process is performed on the bottom of the wafer, and then a sawing process of cutting the wafer into an individual semiconductor chip is performed. Finally, the foil is removed to complete a chip-size semiconductor package shown in FIG. 3 The first molding process can be carried out after the sawing process is performed. A chip-size semiconductor package shown in FIG. 3 can be applied to many uses which do not require sensitive thermal characteristics.
After the sawing process, a die bonding process for attaching the bottom surface of each semiconductor chip to the inner bottom surface of the outer protection plate having a cavity or a recess shape and a second molding process for sealing the gap between the sides of the semiconductor chip and the outer protection plate with a molding resin are carried out to complete a chip-size semiconductor package in FIG. 5. The first molding process can be performed together with the second molding process. The chip-size semiconductor package in FIG. 5 has an improved thermal characteristic due to a safe protection of the surface of the semiconductor chip, resulting in enhancing a reliability of the package.
FIG. 7 is a perspective view showing a partly cut away chip-size semiconductor package according to another embodiment of the present invention. As shown in this drawing, a passivation film 45 is formed in such a manner that a plurality of chip pads 42 formed on the upper surface of the semiconductor chip 41 are exposed. Metal wirings 44, connected to each chip pad 42, are attached to the passivation film 45 with an adherent 46. On the metal wirings 44, external balls 48 electrically connected thereto are formed, and a molding resin layer 43 is formed on the upper portion of the semiconductor chip 41 in such a manner that the upper portions of the external balls 48 protrude therefrom. The metal wirings 44 are patterned to be a separate metal wiring pattern, the material of which is composed of copper (Cu) or gold (Au).
FIGS. 8A and 8B are longitudinal cross-sectional views of FIG. 7, wherein FIG. 8A is a longitudinal cross-sectional view of a chip pad and FIG. 8B is that of an external ball according to another embodiment of the present invention. As shown in these drawings, the passivation film 45 is formed in such a manner that each chip pad 42 formed on the upper surface of the semiconductor chip 41 is exposed, and the metal wirings 44 are attached with an adherent 46 to the passivation film 45. On the passivation film 45, the metal wirings 44 are attached with the adherent 46, and the metal wirings and the chip pads 42 are electrically connected by a connecting member 50, e.g., metal. An inner end of the external ball 48 is attached to the metal wiring 44 electrically connected to the chip pad 42, and the molding resin layer 43 is formed to protect the metal wiring 44 and the chip pad 42 in such a manner that an outer end of the external ball 48 protrudes out of the molding resin layer 43.
FIG. 9 is a perspective view showing a partly cut away chip-size semiconductor package according to another embodiment of the present invention in FIG. 7. As shown in this drawing, the semiconductor chip 41 is attached with an adherent 49 to the inner bottom surface of an external protection plate 47 in the shape of a cavity or a recess, a molding resin seals the gap between the sides of the semiconductor chip 41 and the external protection plate 47 so that the bottom surface and sides of the semiconductor chip 41 are enclosed for protection. The other structures are the same as those of FIG. 7.
FIG. 10 is a flow chart of the method for fabricating the chip-size semiconductor package according to another embodiment of the present invention. First, a wafer is prepared on which a passivation film (Passivation+PIQ or Passivation only) is formed in such a manner that a plurality of chip pads are exposed. Then, a foil mounting is performed on the bottom surface of the wafer, and a sawing process is carried out to cut the wafer into an individual semiconductor chip. A separate metal wiring layer is attached to the semiconductor chip with an adherent, and then a metal deposition process is performed to connect each metal wiring and chip pad formed on the semiconductor chip.
Then, an inner end of a solder wire is attached to the metal wiring, and the solder wire is cut to have a predetermined length. Then a first molding process is carried out to mold the upper surface of the semiconductor chip with a molding resin. Here, the solder wire is molded in such a manner that an outer end thereof protrudes therefrom.
The external solder wire is shaped into a ball by carrying out an infrared reflow process, and a residual solder paste is removed. A final check is performed to complete a chip-size semiconductor package in FIG. 7. Such a chip-size semiconductor package can be applied to many uses which do not require sensitive thermal characteristics.
After the removing of the remaining solder paste is done, a die bonding process is performed such that the bottom surface of each semiconductor chip is attached to the inner bottom surface of the external protection plate in the shape of a cavity or recess. A second molding process is carried out such that the gap between the external protection plate and the semiconductor chip is completely sealed with a molding resin. Then, a final test is conducted to complete a chip-size semiconductor package of FIG. 9. The reliability of the semiconductor package of FIG. 9 can be enhanced since the surface of the semiconductor chip is safely protected and consequently the thermal characteristic is improved.
As described in detail above, the chip-size semiconductor package and the fabrication method thereof according to an embodiment of the present invention has the advantages as follows:
Since the direct attaching of the external balls to the metal wiring removes the necessity of an internal bump in the conventional PMEB package, the fabrication method is simplified. Since the arrangement of the external balls can be made irrespective of the position of the chip pads, the design of the package can be made easy. Further, since the size of the semiconductor package which is nearly the chip size can be fabricated, the mounting rate can be advantageously raised to the maximum, and a plurality of external balls can be effectively formed.
Further, the attachment of the patterned metal wiring layer on the semiconductor with an adherent removes the necessity of a separate process of a metal wiring formation (pre-assembly process in the conventional PMEB), the fabrication method can be simplified. A separate base frame is also advantageously not necessary to form an internal bump in the conventional PMEB package according to the present invention.
The foregoing embodiment is merely exemplary and not to be construed as limiting the present invention. The present scheme may be readily applied to other types of packages. In the foregoing embodiments, the surfaces were referred to as upper and lower surfaces or top and bottom surfaces for convenience to illustrate the present invention in view of the figures. As can be appreciated, the surface reference is dependent upon the orientation of the package. Moreover, the present invention is applicable for packaging various integrated chips, and various conductive materials can be used for conductive coupling, including metal and solder. The description of the present invention is intended to be illustrative, and not limiting the scope of the claims. Many alternatives, modifications and variations will be apparent to those skilled in the art.

Claims (33)

What is claimed is:
1. A semiconductor chip package, comprising;
a semiconductor chip having a plurality of chip pads formed thereon;
a passivation film formed on said semiconductor chip with the chip pads exposed;
a plurality of metal wirings directly coupled to the chip pads formed on the passivation film;
external balls directly electrically connected to each of the metal wirings; and
a molding resin layer formed on a first surface of the semiconductor chip such that upper portions of the external balls protrude from said molding resin layer.
2. The package of claim 1, wherein said plurality of metal wiring comprises one of copper (Cu) and gold (Au).
3. The package of claim 1, wherein the external balls are made of solder.
4. The package of claim 1, further comprises an external protection plate to enclose the sides and a second surface of the semiconductor chip and a resin to seal the gap between the semiconductor chip and the external protection plate.
5. A semiconductor chip package, comprising:
a semiconductor chip having a plurality of chip pads formed thereon;
a passivation film formed on said semiconductor chip such that said plurality of chip pads of the semiconductor chip are exposed;
a plurality of metal wiring layers attached to the passivation film with an adherent;
a connecting metal for conductively coupling each metal wiring layer and each chip pad;
a plurality of external balls attached to each metal wiring layer; and
a molding resin layer formed on a first surface of the semiconductor chip such that an outer end of each external ball protrudes from said molding resin.
6. The package of claim 5, wherein said metal wiring layer comprises one of copper (Cu) or gold (Au).
7. The package of claim 5, wherein the external ball is made of solder.
8. The package of claim 5, further comprising an external protection plate to enclose sides and a second surface of the semiconductor chip and a resin to seal the gap between the semiconductor chip and the external protection plate.
9. A chip package, comprising:
an integrated chip having a plurality of chip pads on a first surface;
a passivation film formed on the first surface of said integrated chip with said plurality of chip pads exposed;
a plurality of conductive wires formed on the passivation film such that a corresponding conductive wire is conductively coupled to a corresponding chip pad;
a plurality of conductive media formed of a single piece, each having a first prescribed height and a corresponding conductive media being formed on a corresponding conductive wire; and
a molding layer formed on said plurality of conductive wires, said molding layer having a prescribed thickness which is less than the prescribed height such that portions of said plurality of conductive media protrude from said molding layer.
10. The chip package of claim 9, wherein said molding layer is directly formed on said plurality of conductive wires.
11. The chip package of claim 9, wherein said integrated chip is a semiconductor chip.
12. The chip package of claim 9, wherein each of said plurality of conductive wires is directly connected to each of said plurality of chip pads.
13. The chip package of claim 9, wherein each of said plurality of conductive wires is conductively coupled to each of said plurality of chip pads by a conductive connecting member.
14. The chip package of claim 13, wherein said plurality of conductive wires is made of a metallic material.
15. The chip package of claim 14, wherein the metallic material is one of copper and gold.
16. The chip package of claim 9, wherein said plurality of conductive wires is attached to the passivation film by an adherent.
17. The chip package of claim 9, wherein said molding layer is made of resin.
18. The chip package of claim 9, wherein each of said plurality of conductive media is a solder ball.
19. The chip package of claim 9, wherein said portions protruding above the molding layer has a circular shape.
20. The chip package of claim 19, wherein said plurality of conductive media is made of solder.
21. The chip package of claim 9, wherein the thickness of the molding layer is about half the height of the conductive media.
22. The chip package of claim 9, further comprising a protection member bonded to a second surface of said integrated chip, the first and second surfaces being opposing surfaces.
23. The chip package of claim 22, wherein said protection member includes a recess such that the sides of said integrated chip are enclosed.
24. The chip package of claim 23 further comprising a resin filling any gaps between said integrated chip and said protection member.
25. A chip package, comprising:
an integrated chip having a plurality of chip pads on a first surface;
a passivation film formed on the first surface of the integrated chip such that said plurality of chip pads are exposed;
a plurality of conductive wires, wherein a corresponding one of said plurality of conductive wires is coupled to a corresponding chip pad;
a plurality of conductive media, each having a first prescribed height, wherein a corresponding one of said plurality of conductive media is coupled to a corresponding one of said plurality of conductive wires;
a molding layer formed on the first surface of said integrated chip such that portions of said plurality of conductive media protrude from said molding layer; and
a protection member bonded to a second surface of said integrated chip, the first and second surfaces being opposing surfaces.
26. The chip package of claim 25, wherein said protection member includes a recess to enclose the sides of said integrated chip.
27. The chip package of claim 26, further comprising a resin filling any gaps between said integrated chip and said protection member.
28. The chip package of claim 25, wherein said molding layer is directly formed on the conductive wiring.
29. The chip package of claim 25, wherein said integrated chip is a semiconductor chip.
30. The chip package of claim 25, wherein said plurality of conductive wires comprise metal wires being one of copper (Cu) and gold (Au).
31. The chip package of claim 25, wherein each of said plurality of conductive media comprises a solder ball.
32. The chip package of claim 25, wherein said plurality of conductive wires is attached to the passivation film by an adherent.
33. The chip package of claim 25, wherein said molding layer is made of resin.
US08/923,817 1996-09-11 1997-09-04 Semiconductor chip package and fabrication method thereof Expired - Lifetime US5994783A (en)

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EP1011141A3 (en) * 1998-12-17 2001-06-13 Shinko Electric Industries Co. Ltd. Semiconductor device and process for producing it
US6173887B1 (en) * 1999-06-24 2001-01-16 International Business Machines Corporation Method of making electrically conductive contacts on substrates
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US7977229B2 (en) 2000-04-28 2011-07-12 Oki Semiconductor Co., Ltd. Method for fabricating resin-molded semiconductor device having posts with bumps
US6911722B2 (en) * 2000-04-28 2005-06-28 Oki Electric Industry Co., Ltd. Resin-molded semiconductor device having posts with bumps
US20050194682A1 (en) * 2000-04-28 2005-09-08 Oki Electric Industry Co., Ltd. Resin-molded semiconductor device having posts with bumps and method for fabricating the same
US7307337B2 (en) 2000-04-28 2007-12-11 Oki Electric Industry Co., Ltd. Resin-molded semiconductor device having posts with bumps and method for fabricating the same
US6510976B2 (en) * 2001-05-18 2003-01-28 Advanpack Solutions Pte. Ltd. Method for forming a flip chip semiconductor package
US20080017980A1 (en) * 2004-05-28 2008-01-24 Koninklijke Philips Electronics N.V. Chip Having Two Groups Of Chip Contacts
US9318428B2 (en) 2004-05-28 2016-04-19 Nxp B.V. Chip having two groups of chip contacts
US20140183725A1 (en) * 2012-12-28 2014-07-03 Taiwan Semiconductor Manufacturing Company, Ltd. Post-passivation interconnect structure and method of forming the same
US10483132B2 (en) * 2012-12-28 2019-11-19 Taiwan Semiconductor Manufacturing Company, Ltd. Post-passivation interconnect structure and method of forming the same
US10651055B2 (en) 2012-12-28 2020-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Post-passivation interconnect structure and method of forming the same
US10777431B2 (en) 2012-12-28 2020-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Post-passivation interconnect structure and method of forming the same
US20170200646A1 (en) * 2016-01-13 2017-07-13 Nxp B.V. Integrated circuits and molding approaches therefor
US9842776B2 (en) * 2016-01-13 2017-12-12 Nxp B.V. Integrated circuits and molding approaches therefor
US11362062B2 (en) 2020-05-26 2022-06-14 Samsung Electronics Co., Ltd. Semiconductor package
US11791308B2 (en) 2020-05-26 2023-10-17 Samsung Electronics Co., Ltd. Semiconductor package

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JP2995552B2 (en) 1999-12-27
JPH1098132A (en) 1998-04-14
CN1176492A (en) 1998-03-18
US6277670B1 (en) 2001-08-21
CN1085890C (en) 2002-05-29
KR100239695B1 (en) 2000-01-15
KR19980020672A (en) 1998-06-25

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