US6010934A - Method of making nanometer Si islands for single electron transistors - Google Patents

Method of making nanometer Si islands for single electron transistors Download PDF

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US6010934A
US6010934A US09/033,527 US3352798A US6010934A US 6010934 A US6010934 A US 6010934A US 3352798 A US3352798 A US 3352798A US 6010934 A US6010934 A US 6010934A
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silicon
substrate
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Shye-Lin Wu
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
Texas Instruments Acer Inc
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/902—Specified use of nanostructure
    • Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
    • Y10S977/936—Specified use of nanostructure for electronic or optoelectronic application in a transistor or 3-terminal device
    • Y10S977/937—Single electron transistor

Definitions

  • the present invention relates to a method of manufacturing the nanometer Si islands on silicon wafers, and more specifically, to a method of fabricating single electron transistors on the silicon wafers.
  • the single electron transistor (SET) has become an essential element in electronics.
  • the devices are operated by utilizing the Coulomb Blockade effect.
  • the operation of SET device operation has been limited to below 4 K.
  • the reason is that the smallest capacitance of the SET has been about 100 aF. This means that a charging energy e 2 /(2 C) is much larger than the thermal energy, which could be met at very low temperature.
  • Y. Takajashi et al. reported a Si-SET whose capacitance is only about 2 aF.
  • the Si-SET is reported in this paper shows conductance oscillation even at room temperature is reported in this paper.
  • a SET can be fabricated in a substrate and it is operated at room temperature.
  • a process which is separation by implanted oxygen (SIMOX) is used to form a superficial Si layer.
  • the SET device is fabricated in the superficial Si layer.
  • semiconductor technique the author fabricated an one-dimensional Si wire in the superficial Si layer.
  • the Si wire width can be in the order of nanometer.
  • a method of manufacturing a memory array of single electron transistors is disclosed in the present invention. Initially, a pad oxide is formed over a silicon substrate. An ion implantation is performed on the silicon substrate in order to form an oxygen amorphized region in the silicon substrate. After the ion implantation of the silicon substrate, a high-temperature annealing process is used to form a buried layer and the depth of the buried layer is between about 0.3 to 0.5 micrometers. A thermal oxide is then formed on the silicon substrate to reduce the thickness of the silicon substrate on the buried layer. The thermal oxide is removed and an ultra-thin oxide is formed on the silicon substrate. Afterwards, several silicon nitride blocks are formed on the ultra-thin oxide to define isolation patterns.
  • a polysilicon layer is deposited on the silicon nitride blocks and then etched back to form polysilicon spacers.
  • the silicon nitride blocks are removed by using hot H 3 PO 4 solution.
  • the ultra-thin oxide is etched back using polysilicon spacers as hard mask.
  • the ultra-thin oxide layer on the silicon islands is removed and an ultra-thin oxynitride layer is formed on the surface of the silicon islands.
  • an n+ polysilicon layer is deposited on the surface of the buried layer and the nanometer silicon islands.
  • FIG. 1 is a cross sectional view of a semiconductor substrate illustrating the formation of a pad oxide on the substrate in accordance with the present invention
  • FIG. 2 is a cross sectional view of a semiconductor substrate illustrating a blanket implantation to dope oxygen ions into the substrate in accordance with the present invention
  • FIG. 3 is a cross sectional view of a semiconductor substrate illustrating the formation of a buried oxide in the substrate in accordance with the present invention
  • FIG. 4 is a cross section view of a semiconductor substrate illustrating the formation of a thermal oxide to form nanometer Si substrate in accordance with the present invention
  • FIG. 5 is a cross sectional view of a semiconductor substrate illustrating the removing of the thermal oxide and the formation of an ultra-thin oxide in accordance with the present invention
  • FIG. 6 is a cross sectional view of a semiconductor substrate illustrating the formation of nitride blocks on the ultra-thin oxide in accordance with the present invention
  • FIG. 7 is a cross sectional view of a semiconductor substrate illustrating the formation of polysilicon spacers of the nitride blocks in accordance with the present invention
  • FIG. 8 is a cross sectional view of a semiconductor substrate illustrating the removing of the nitride blocks in accordance with the present invention
  • FIG. 9 is a cross sectional view of a semiconductor substrate illustrating the formation of nanometer Si wires in accordance with the present invention.
  • FIG. 10 is a cross sectional view of a semiconductor substrate illustrating the formation of spacers of the gates and active region in the substrate;
  • FIG. 11 is a cross sectional view of a semiconductor substrate illustrating that a thick oxide layer is formed on the surface of the substrate and a metal contact is formed in the thick oxide layer;
  • FIG. 12 shows a top view of nanometer silicon single electron transistor devices in accordance with the present invention.
  • a method of making nanometer Si islands on a silicon wafer is disclosed here.
  • the nanometer Si islands are fabricated to become single electron transistors.
  • the present invention is explained with a preferred embodiment in following descriptions.
  • a substrate 100 is provided and it is a single crystal P-type substrate with ⁇ 100> crystallography orientation.
  • a pad oxide 105 is formed on the substrate 100 using thermal oxidation in an oxygen ambient and it has a thickness of between about 100 to 500 angstroms.
  • oxygen ions are implanted into the substrate 100 with high dosage and an oxygen amphorized region 110 is formed in the substrate 100.
  • the high dosage is about 5 ⁇ 10 16 to 5 ⁇ 10 19 ions/cm 2 and the implanting energy is about 100 to 300 KeV.
  • a buried oxide layer 115 is formed in the substrate 100 by using a high temperature annealing to convert the oxygen amorphized region 110 into a buried oxide layer.
  • the annealing process is done in the neutral ambient of N 2 or N 2 /O 2 mixture gases.
  • the annealing time requires sufficient time (3-5 hours) and the annealing process uses a high temperature (1050-1250° C.).
  • the depth of the buried oxide layer 115 is between about 0.3-0.5 micrometers.
  • the technique of forming the buried oxide layer is the separation by implanted oxygen (SIMOX) process.
  • a thermal oxide 116 is formed on the substrate 100 using thermal oxidation.
  • the thermal oxidation can reduce the thickness of the single crystal Si region between the thermal oxide 116 and the buried oxide layer 115.
  • the Si substrate 100 between the thermal oxide 116 and the buried oxide layer 115 is about nanometer dimension because process of the silicon substrate 100 on the buried oxide 115 is converted into thermal oxide.
  • the thermal oxide 116 is removed and an ultra-thin oxide 120 is formed on the substrate 100.
  • the thermal oxide 116 is removed by using buffer oxide etching (BOE) solution or diluted HF solution.
  • An ultra-thin oxide 120 is regrown on the substrate 100 using thermal oxidation and it has a thickness between about 20 to 200 angstroms.
  • a silicon nitride layer is deposited on the ultra-thin oxide 120 and is then etched back to form the silicon nitride layer blocks 125.
  • the silicon nitride blocks 125 have a thickness between about 100 to 1000 angstroms.
  • the silicon nitride blocks 125 is deposited by using low pressure chemical vapor deposition (LPCVD) or plasma enhancement chemical vapor deposition (PECVD).
  • LPCVD low pressure chemical vapor deposition
  • PECVD plasma enhancement chemical vapor deposition
  • a polysilicon layer is deposited on the silicon nitride blocks 125 and then etched back to form polysilicon spacers 130.
  • the polysilicon layer is deposited by low pressure chemical vapor deposition (LPCVD) system, at the pressure of 50 to 600 mtorrs and the temperature is between about 400 to 600° C. and the thickness is between about 50 to 500 angstroms.
  • LPCVD low pressure chemical vapor deposition
  • the silicon nitride layer 125 is removed to form silicon islands on the substrate 100.
  • the silicon nitride layer 125 is removed by using hot phosphoric acid (H 3 PO 4 ) solution.
  • the ultra-thin oxide 120 is then drily etched back by using the polysilicon spacers 130 as hard mask.
  • the polysilicon spacers 130 and the remaining ultra-thin oxide films are used as hard mask to form silicon islands on the substrate 100.
  • the Si substrate 100 is etched back to form nanometer Si islands by using the polysilicon spacers 130 and the ultra-thin oxide 120 as hard mask. Afterwards, nanometers Si wires 135 are formed over the buried oxide layer. In the preferred embodiment, a dry etching, such as plasma etching, is performed to form the silicon wire 135 on the substrate 100.
  • a dry etching such as plasma etching
  • an ultra-thin oxynitride film 140 was grown on nanometer Si island by using N 2 O or NO gas.
  • the ultra-thin oxynitride film 140 has a thickness between about 10 to 100 angstroms.
  • a n+ polysilicon layer 145 is deposited as gate material of single electron tunneling (SET) device.
  • the n+ polysilicon layer 145 is formed of in-situ doped polysilicon material and it is deposited by using conventional chemical vapor deposition (CVD), adding phosphorus gas or arsenic gas into CVD reactant gas as a doping source.
  • the thickness of the n+ polysilicon is between about 500 to 2000 angstroms.
  • FIG. 12 a top view of the memory array is demonstrated and FIG. 11 is a cross sectional view of the FIG. 12 along AA' line.
  • the memory array is constructed on the buried oxide layer 115.
  • the n+ doping polysilicon layer 145 is a wide band over the buried oxide layer and the silicon wires 135 is cross the polysilicon layer 145 to form single electron transistors (SET).
  • the dash lines show the oxynitride layer 140 on the silicon wires 135. The two terminals of the silicon wires are connected to a source 10 and a drain 20.
  • the n+ doping polysilicon 145 is connected to a gate 30.
  • the memory array is controlled by using the source 10, the drain 20 and the gate 30.
  • a serial of single electron transistor (SET) is fabricated and nanometer single electron transistors are manufactured in the substrate 100.

Abstract

A method of making nanometer Si islands for single electron transistors is disclosed. Initially, a pad oxide is deposited over a silicon substrate. Oxygen ions are implanted into the silicon substrate to form an oxygen amorphized region and a high-temperature annealing is performed to form a buried oxide layer in the silicon substrate. Then, a thermal silicon oxide is formed to reduce the thickness of the silicon substrate on the buried oxide layer. The thermal oxide is removed and an ultra-thin oxide layer is then formed on the silicon substrate. A plurality of silicon nitride blocks is formed on the ultra-thin silicon oxide. Afterwards, the spacers of the silicon nitride blocks are formed. The silicon nitride blocks are removed by using wet etching technique. The ultra-thin silicon oxide is etched back and the polysilicon spacers are used as hard mask to Si substrate to form a plurality of nanometer silicon islands. The ultra-thin silicon oxide is removed and an ultra-thin oxynitride layer is regrown on the nanometer silicon islands. Finally, a n+ polysilicon layer is conformally deposited onto the silicon substrate and the nanometer silicon islands.

Description

FIELD OF THE INVENTION
The present invention relates to a method of manufacturing the nanometer Si islands on silicon wafers, and more specifically, to a method of fabricating single electron transistors on the silicon wafers.
BACKGROUND OF THE INVENTION
The single electron transistor (SET) has become an essential element in electronics. The devices are operated by utilizing the Coulomb Blockade effect. However, the operation of SET device operation has been limited to below 4 K. The reason is that the smallest capacitance of the SET has been about 100 aF. This means that a charging energy e2 /(2 C) is much larger than the thermal energy, which could be met at very low temperature. In IEDM Tech. Dig. in the page 938 on 1994, Y. Takajashi et al. reported a Si-SET whose capacitance is only about 2 aF. The Si-SET is reported in this paper shows conductance oscillation even at room temperature is reported in this paper. Thus, using semiconductor technique, a SET can be fabricated in a substrate and it is operated at room temperature. In this paper, a process which is separation by implanted oxygen (SIMOX) is used to form a superficial Si layer. The SET device is fabricated in the superficial Si layer. Then, by using semiconductor technique, the author fabricated an one-dimensional Si wire in the superficial Si layer. The Si wire width can be in the order of nanometer.
Recently, the room temperature operation of a single-electron memory was realized by a device using nanometer-sized, polycrystalline fine-grain Si for a floating gate and channel. In IEDM Tech. Dig., in page 952 on 1996, A. Nakajima et al reported a Si single-electron memory with self-aligned floating gate. The authors reported a new Si single-electron memory device comprised of a narrow channel field effect transistor (FET) having an ultra-small self-aligned floating dot gate, which is capable to exhibit clear, single-electron memory effects at room temperature. In this paper, the Si single-electron FET memory has a width of about 30 nanometers and is operated at room temperature.
Many efforts are made to fabricate silicon-based SET devices. The smallest dimension required for SET operation depends on non-artificial process such as grain control and inhomogeneous oxidation, which can be hardly determined in the design stage. In page 955 of IEDM Tech. Dig. on 1996, L. Guo et al reported that a Si single-electron MOS memory (SEMM) is fabricated and the electrical characteristic of the device are detected. The device has a nanoscale floating-gate and a narrow gate. The capacitance for the 7 nm×7 nm floating gate and a 40 nm control oxide is 4×10-20 F, giving single electron charging voltage of 4 V. The SEMM device was fabricated by using silicon on insulator (SOI) technique. The channel of the device was fabricated using e-beam lithography and reactive ion etching. The channel had a width varying from 25 nm to 120 nm.
In page 4161 of vol. 36, Jpn. J. Appl. Phys., on 1997, N. Yoshikawa et al reported a single-electron-tunneling effect in nanoscale granular microbridge. The granular microbridge was fabricated on an oxide step. A thin film was deposited on the oxide step. An ion etching was performed at an angle of 45 degrees and a microbridge was formed beside the oxide step.
In the last two papers, the methods of fabricating the single electron channel are nonartifical and difficult to control. In another words, designers are hard to design a good structure and to control the dimension of the channel. Thus, a simple and stable process method to fabricate the single electron transistor is essentially necessary.
SUMMARY OF THE INVENTION
A method of manufacturing a memory array of single electron transistors is disclosed in the present invention. Initially, a pad oxide is formed over a silicon substrate. An ion implantation is performed on the silicon substrate in order to form an oxygen amorphized region in the silicon substrate. After the ion implantation of the silicon substrate, a high-temperature annealing process is used to form a buried layer and the depth of the buried layer is between about 0.3 to 0.5 micrometers. A thermal oxide is then formed on the silicon substrate to reduce the thickness of the silicon substrate on the buried layer. The thermal oxide is removed and an ultra-thin oxide is formed on the silicon substrate. Afterwards, several silicon nitride blocks are formed on the ultra-thin oxide to define isolation patterns. A polysilicon layer is deposited on the silicon nitride blocks and then etched back to form polysilicon spacers. The silicon nitride blocks are removed by using hot H3 PO4 solution. The ultra-thin oxide is etched back using polysilicon spacers as hard mask. The polysilicon spacers and the remained thin oxides used as hard mask to define nanometer silicon island. The ultra-thin oxide layer on the silicon islands is removed and an ultra-thin oxynitride layer is formed on the surface of the silicon islands. Finally, an n+ polysilicon layer is deposited on the surface of the buried layer and the nanometer silicon islands.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
FIG. 1 is a cross sectional view of a semiconductor substrate illustrating the formation of a pad oxide on the substrate in accordance with the present invention;
FIG. 2 is a cross sectional view of a semiconductor substrate illustrating a blanket implantation to dope oxygen ions into the substrate in accordance with the present invention;
FIG. 3 is a cross sectional view of a semiconductor substrate illustrating the formation of a buried oxide in the substrate in accordance with the present invention;
FIG. 4 is a cross section view of a semiconductor substrate illustrating the formation of a thermal oxide to form nanometer Si substrate in accordance with the present invention;
FIG. 5 is a cross sectional view of a semiconductor substrate illustrating the removing of the thermal oxide and the formation of an ultra-thin oxide in accordance with the present invention;
FIG. 6 is a cross sectional view of a semiconductor substrate illustrating the formation of nitride blocks on the ultra-thin oxide in accordance with the present invention;
FIG. 7 is a cross sectional view of a semiconductor substrate illustrating the formation of polysilicon spacers of the nitride blocks in accordance with the present invention;
FIG. 8 is a cross sectional view of a semiconductor substrate illustrating the removing of the nitride blocks in accordance with the present invention;
FIG. 9 is a cross sectional view of a semiconductor substrate illustrating the formation of nanometer Si wires in accordance with the present invention;
FIG. 10 is a cross sectional view of a semiconductor substrate illustrating the formation of spacers of the gates and active region in the substrate;
FIG. 11 is a cross sectional view of a semiconductor substrate illustrating that a thick oxide layer is formed on the surface of the substrate and a metal contact is formed in the thick oxide layer; and
FIG. 12 shows a top view of nanometer silicon single electron transistor devices in accordance with the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
A method of making nanometer Si islands on a silicon wafer is disclosed here. The nanometer Si islands are fabricated to become single electron transistors. The present invention is explained with a preferred embodiment in following descriptions.
Turning to FIG. 1, a substrate 100 is provided and it is a single crystal P-type substrate with <100> crystallography orientation. A pad oxide 105 is formed on the substrate 100 using thermal oxidation in an oxygen ambient and it has a thickness of between about 100 to 500 angstroms.
Turning to FIG. 2, oxygen ions are implanted into the substrate 100 with high dosage and an oxygen amphorized region 110 is formed in the substrate 100. The high dosage is about 5×1016 to 5×1019 ions/cm2 and the implanting energy is about 100 to 300 KeV.
Next, turning to FIG. 3, a buried oxide layer 115 is formed in the substrate 100 by using a high temperature annealing to convert the oxygen amorphized region 110 into a buried oxide layer. The annealing process is done in the neutral ambient of N2 or N2 /O2 mixture gases. The annealing time requires sufficient time (3-5 hours) and the annealing process uses a high temperature (1050-1250° C.). Typically, the depth of the buried oxide layer 115 is between about 0.3-0.5 micrometers. The technique of forming the buried oxide layer is the separation by implanted oxygen (SIMOX) process.
As be shown in FIG. 4, a thermal oxide 116 is formed on the substrate 100 using thermal oxidation. The thermal oxidation can reduce the thickness of the single crystal Si region between the thermal oxide 116 and the buried oxide layer 115. The Si substrate 100 between the thermal oxide 116 and the buried oxide layer 115 is about nanometer dimension because process of the silicon substrate 100 on the buried oxide 115 is converted into thermal oxide.
Referring to FIG. 5, the thermal oxide 116 is removed and an ultra-thin oxide 120 is formed on the substrate 100. Typically, the thermal oxide 116 is removed by using buffer oxide etching (BOE) solution or diluted HF solution. An ultra-thin oxide 120 is regrown on the substrate 100 using thermal oxidation and it has a thickness between about 20 to 200 angstroms.
As can be seen in FIG. 6, a silicon nitride layer is deposited on the ultra-thin oxide 120 and is then etched back to form the silicon nitride layer blocks 125. The silicon nitride blocks 125 have a thickness between about 100 to 1000 angstroms. In the preferred embodiment, the silicon nitride blocks 125 is deposited by using low pressure chemical vapor deposition (LPCVD) or plasma enhancement chemical vapor deposition (PECVD).
Turning to FIG. 7, a polysilicon layer is deposited on the silicon nitride blocks 125 and then etched back to form polysilicon spacers 130. The polysilicon layer is deposited by low pressure chemical vapor deposition (LPCVD) system, at the pressure of 50 to 600 mtorrs and the temperature is between about 400 to 600° C. and the thickness is between about 50 to 500 angstroms.
Turning to FIG. 8, the silicon nitride layer 125 is removed to form silicon islands on the substrate 100. The silicon nitride layer 125 is removed by using hot phosphoric acid (H3 PO4) solution. The ultra-thin oxide 120 is then drily etched back by using the polysilicon spacers 130 as hard mask. The polysilicon spacers 130 and the remaining ultra-thin oxide films are used as hard mask to form silicon islands on the substrate 100.
As can be seen in FIG. 9, the Si substrate 100 is etched back to form nanometer Si islands by using the polysilicon spacers 130 and the ultra-thin oxide 120 as hard mask. Afterwards, nanometers Si wires 135 are formed over the buried oxide layer. In the preferred embodiment, a dry etching, such as plasma etching, is performed to form the silicon wire 135 on the substrate 100.
As can be shown in FIG. 10, after the silicon wires 135 are formed, an ultra-thin oxynitride film 140 was grown on nanometer Si island by using N2 O or NO gas. The ultra-thin oxynitride film 140 has a thickness between about 10 to 100 angstroms.
Turning to FIG. 11, a n+ polysilicon layer 145 is deposited as gate material of single electron tunneling (SET) device. In one case, the n+ polysilicon layer 145 is formed of in-situ doped polysilicon material and it is deposited by using conventional chemical vapor deposition (CVD), adding phosphorus gas or arsenic gas into CVD reactant gas as a doping source. The thickness of the n+ polysilicon is between about 500 to 2000 angstroms.
After the above process, several nanometer silicon single electron tunneling (SET) devices are fabricated on the substrate 100 and these devices form a memory array. Referring to FIG. 12, a top view of the memory array is demonstrated and FIG. 11 is a cross sectional view of the FIG. 12 along AA' line. In this figure, the memory array is constructed on the buried oxide layer 115. The n+ doping polysilicon layer 145 is a wide band over the buried oxide layer and the silicon wires 135 is cross the polysilicon layer 145 to form single electron transistors (SET). In the drawing, the dash lines show the oxynitride layer 140 on the silicon wires 135. The two terminals of the silicon wires are connected to a source 10 and a drain 20. Besides, the n+ doping polysilicon 145 is connected to a gate 30. The memory array is controlled by using the source 10, the drain 20 and the gate 30. In the present invention, a serial of single electron transistor (SET) is fabricated and nanometer single electron transistors are manufactured in the substrate 100.
As is understood by a person skilled in the art, the foregoing preferred embodiment of the present invention are illustrated of the present invention rather than limiting of the present invention.
While the preferred embodiment of the invention has been illustrated and described, it will be appreciated that various changes can be made therein without departing from the spirit and scope of the invention.

Claims (18)

What is claimed is:
1. A method of manufacturing a single election transistor, the method comprising the steps of:
forming a pad oxide over a substrate;
performing an ion implantation using oxygen ions as dopant into said substrate;
performing an annealing process on said substrate to form a buried oxide layer in said substrate;
forming a thermal oxide layer on said substrate to reduce the thickness of said substrate on said buried layer;
removing said thermal oxide layer;
forming a silicon oxide layer on said substrate;
forming a silicon nitride block over said silicon oxide layer to defined an isolation pattern;
forming polysilicon spacers on said silicon nitride block;
removing said silicon nitride block;
etching back said substrate to form a silicon He by using the polysilicon spacers as a hard mask;
forming an oxynitride layer to be a cap layer of the silicon wire; and
forming a polysilicon layer over said silicon wire to form a single electron transistor (SET).
2. The method of claim 1, wherein said pad oxide has a thickness between about 100 to 500 angstroms.
3. The method of claim 1, wherein said ion implantation has a dosage between about 5×1016 to 5×1019 ions/cm2 and a energy between about 100 to 300 KeV.
4. The method of claim 1, wherein said annealing process has a temperature between about 1050 to 1250° C.
5. The method of claim 1, wherein said anneal is performed in a N2 and N2 /O2 gas ambient.
6. The method of claim 1, wherein forming said oxynitride layer to be a cap layer is formed in a N2 O and NO gas ambient.
7. The method of claim 1, wherein forming said polysilicon layer over said silicon wire is formed of an n+ polysilicon material.
8. The method of claim 1, wherein said oxynitride layer has a thickness between about 10 to 100 angstroms.
9. The method of claim 1, wherein said silicon oxide layer has a thickness between about 20 to 200 angstroms.
10. A method to manufacture a memory array of single electron transistors, the method comprising the steps of:
forming a pad oxide on a silicon substrate;
performing an oxygen ion implantation on said substrate to form an oxygen amorphized region;
performing an annealing process to form a buried oxide layer;
forming a thermal silicon oxide layer on said substrate to form a nanometer silicon island;
removing said thermal silicon oxide layer;
forming a silicon oxide layer on said substrate;
forming polysilicon spacers on said silicon nitride blocks;
removing said silicon nitride blocks;
etching said silicon substrate to form a plurality of silicon wires using said polysilicon spacers as a hard mask;
removing said polysilicon spacers;
forming an oxynitride layer to be a cap layer of said silicon wires; and
forming a polysilicon layer over said oxynitride layer and said buried oxide layer to form a plurality of single electron transistors.
11. The method of claim 10, wherein said pad oxide has a thickness between about 100 to 500 angstroms.
12. The method of claim 10, wherein said ion implantation has a dosage between about 5×1016 to 5×10 19 ions/cm2 and a energy between about 100 to 300 KeV.
13. The method of claim 10, wherein said annealing process has a temperature between about 1050 to 1250° C.
14. The method of claim 10, wherein said anneal is performed in a N2 and N2 /O2 gas ambient.
15. The method of claim 10, wherein forming said oxynitride layer is formed in a N2 O and NO gases ambient.
16. The method of claim 10, wherein forming said polysilicon layer over said silicon wires is formed of a n+ polysilicon material.
17. The method of claim 10, wherein said oxynitride layer has a thickness between about 10 to 100 angstroms.
18. The method of claim 10, wherein said silicon oxide layer has a thickness between about 20 to 200 angstroms.
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US20040061173A1 (en) * 2002-07-04 2004-04-01 Shu-Fen Hu Single-electron transistor and fabrication method thereof
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