US6011310A - Film carrier and semiconductor device using the same - Google Patents
Film carrier and semiconductor device using the same Download PDFInfo
- Publication number
- US6011310A US6011310A US08/722,321 US72232196A US6011310A US 6011310 A US6011310 A US 6011310A US 72232196 A US72232196 A US 72232196A US 6011310 A US6011310 A US 6011310A
- Authority
- US
- United States
- Prior art keywords
- insulating layer
- film carrier
- semiconductor element
- conductive
- via holes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- 239000004020 conductor Substances 0.000 claims description 12
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- 229910052751 metal Inorganic materials 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 239000012790 adhesive layer Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
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- 239000004332 silver Substances 0.000 description 2
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- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
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- 229910017052 cobalt Inorganic materials 0.000 description 1
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- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
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Images
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/4985—Flexible insulating substrates
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
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- H05K3/4007—Surface contacts, e.g. bumps
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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Definitions
- the present invention relates to a film carrier and a semiconductor device using the same.
- a film carrier system As a method of mounting a semiconductor element, a film carrier system has hitherto been employed and for inner bonding of the leads on the film carrier and the electrodes of a semiconductor element, bumps for connection have been utilized.
- the present invention was made for solving the problems in the conventional techniques described above and the object of this invention is to provide a film carrier for a so-called chip-size package, that is a film carrier which can sufficiently correspond to pitch-fining and high-density mounting of a semiconductor element wiring, can surely perform the connecting operation of inner lead bonding and outer lead bonding, and gives the mounting area of as small as possible.
- Another object of this invention is to provide a semiconductor device wherein a semiconductor element is mounted on the foregoing film carrier.
- the inventors have discovered that the foregoing object can be attained by laying a wire in an insulating film such that the circuit is not exposed without forming the circuit on the surface of an insulating film different from a conventional film carrier, exposing on the surface only the end portions of conductive passages connected to the in-land circuit, connecting the end portions to bumps of the electrode portions of a semiconductor element or to the land portions of an outside substrate and have succeeded in accomplishing the present invention based on the discovery.
- a film carrier comprising an insulating layer having laid therein an electrically conductive circuit such that the circuit is not exposed on the surface thereof, wherein conductive passages from the conductive circuit to one surface of the insulating layer are formed in the insulating layer and via holes from said conductive circuit to the other surface of the insulating layer are formed.
- a semiconductor device comprising the foregoing film carrier having mounted thereon a semiconductor element such that the electrodes of said semiconductor element are connected to the surface of the insulating layer of the side wherein the via holes of the film carrier are formed.
- FIGS. 1(A) to 1(E) each is a cross-sectional view showing an example of each production step for obtaining the film carrier of the present invention
- FIG. 2 is a cross-sectional view showing another example of the film carrier of the present invention.
- FIG. 3 is a cross-sectional view showing still another example of the film carrier of the present invention.
- FIG. 4 is a cross-sectional view showing another example of the film carrier of the present invention.
- FIG. 5 is a cross sectional view showing an example of the semiconductor device of the present invention.
- FIG. 6 is a cross sectional view showing other example of the semiconductor device of the present invention.
- FIG. 7 is a cross-sectional view showing another example of the semiconductor device of the present invention.
- FIGS. 1(A) to(E) are cross-sectional views showing an example of the production steps for obtaining the film carrier of the present invention.
- an insulating layer 2' is laminated by heat-press sticking, extrusion molding, cast coating, etc., such that the insulating layer 2' covers the surface of the exposed conductive circuit 1, whereby the conductive circuit 1 becomes a laid state in the insulating layers (see, FIG. 1(C)).
- via holes 3' are formed in the insulating layer 2' by the same manner as described above (see, FIG. 1(D)).
- an electrically conductive material (hereinafter referred to as conductive material) is added to only fill in the via holes 3 formed in the insulating layer 2 to form conductive passages 4, whereby the film carrier of this invention having the conductive passages at only one side is obtained (see, FIG. 1(E)).
- the via holes 3' formed in the insulating layer 2' may be filled by a conductive material electrically connecting the conductive circuit 1 as long as each hole does not reach the surface of the insulating layer 2' (see, FIG. 3).
- the foregoing via holes 3 and 3' may be formed after laminating the insulating layers 2 and 2' and also, the conductive material may be added after forming the via hole 3 and also the conductive material may be added after forming the via holes 3'.
- the insulating layers 2 and 2' being used for the film carrier of the present invention may be ones substantially having an electrical insulating property and practically thermosetting resins or thermoplastic resins, such as a polyester series resin, an epoxy series resin, a urethane series resin, a polystyrene series resin, a polyethylene series resin, a polyamide series resin, a polyimide series resin, a polycarbonate series resin, a silicone series resin, an acrylonitrile-butadiene-styrene (ABS) copolymer resin, etc., are formed in a layer form.
- the polyimide series resin is preferably used in the points of the heat resistance, the dimensional stability by heating, the mechanical strength, etc.
- the thickness of the insulating layer 2 or 2' is generally from 2 to 500 ⁇ m, and preferably from about 5 to 150 ⁇ m from the points of the mechanical strength and the flexibility.
- the insulating layers 2 and 2' may be formed with a same kind of a resin or a different kind of resins.
- the feature of the film carrier of the present invention is that the conductive circuit 1 is laid in the insulating layer 2 and the conductive circuit 1 is not exposed to the surface of the layer.
- the method of laying the conductive circuit 1 in the insulating layer it is preferred to conduct the lamination such that the conductive circuit 1 is interposed between the insulating layer 2 and the insulating layer 2' as described above from the point of easiness of the production.
- the via holes 3 and 3' there are a mechanical punching method, a photolithographic processing method, a chemical etching processing method, a laser processing method, etc., but for corresponding to fining of pitch, the laser processing which can carry out fine processing is preferable in in particular, it is desirable to use a hole drilling method using an ultraviolet laser having oscillation wavelength in the a ultraviolet region.
- the via holes thus formed are generally formed at a diameter of from 5 to 200 ⁇ m, and preferably from about 8 to 100 ⁇ m. Also, by using a photosensitive resin as a material for forming the insulating layers and light-exposing and developing the layers, the fine via holes can be formed.
- a method of filling a conductive material in the via holes 3 and 3' there are a chemical filling method such as a plating method, a chemical vapor deposition (CVD) method, a method of immersing in a molten metal bath to deposit the metal in the holes, etc.; and a physical filling method such as a method of press-injecting the conducting material in the holes, etc., but a method by electroplating using the conductive circuit as the electrode is a simple method and is preferable.
- CVD chemical vapor deposition
- the conductive material being filled in the via holes various kinds of metals and alloys such as gold, silver, copper, nickel, cobalt, a solder, etc., or a conductive paste containing a conductive powder dispersed therein, etc., is used.
- the conductive passages 4 and 4' thus formed each can be formed not only by a single conductive material but also can be a multilayer structure wherein a relatively inexpensive metal such as copper, etc., is used at the portion being in contact with the conductive circuits 1 and 1' and a metal having a high connection reliability by forming an eutectic is used at end portions of the conductive passages being utilized for connection.
- each conductive passage 4 is swelled in a bump form at a height of from about several ⁇ m to several tens ⁇ m, which is effective for the easiness of determining the positions at connecting the land portion of an outside substrate and the certainty of connection.
- bumps such as solder balls exist at the side to be connected, it is unnecessary to swell the ends of the conductive passages in a bump form as shown in the figure.
- FIG. 2 is a cross-sectional view showing another example of the film carrier of the present invention, wherein the surface of the insulating layer 2' is processed in a recessed portion at the mounting portions thereof.
- the semiconductor element may only be put in the recessed portion and thus the determination of position and the connecting operation become very simple. Also, when a semiconductor device is prepared by mounting a semiconductor element, the total thickness becomes thin, which is effective for making a thin-type light-weight semiconductor device.
- FIG. 3 is a cross-sectional view showing another example of the film carrier of the present invention, wherein the pitch of the conductive passages 4 (lower side in the figure) of the outer lead bonding portion is narrower than the pitch of the via holes 3' (upper side in the figure) of the inner lead bonding portion.
- FIG. 4 is a cross-sectional view showing still another example of the film carrier of the present invention, wherein the conductive circuit 1 and the conductive 1', which are laid in insulating layers, are in a multilayer structure.
- the degree of freedom in designing of wiring in a semiconductor element is preferably increased as compared with the case that the conductive circuit is a single layer.
- FIG. 5 is a cross-sectional view showing an example of the semiconductor device of the present invention.
- a semiconductor element 5 is mounted on the film carrier shown in FIG. 1 such that the electrode portions of the semiconductor element 5 are connected to the via holes 3' of the film carrier shown in FIG. 1(E), and for ensuring the connection, an adhesive layer 6 is disposed between the insulting layer 2' and the semiconductor element 5.
- an epoxy series resin, a fluorine series resin, a polyimide series resin, etc. can be used and a thermoplastic resin which exhibits adhesive property by hot pressing is preferably used.
- the adhesive layer 6 may be previously laminated to the semiconductor element side or the film carrier side or a film form adhesive or a ribbon form adhesive can be used by inserting between them and connecting them.
- the film carrier thus mounted thereon the semiconductor element 5 is mounted on an outside substrate 7 by connecting the conductive passages 4 at the other side of the film carrier to the land portions 8 on the outside substrate 7.
- FIG. 6 is a cross-sectional view showing another example of the semiconductor device of this invention.
- FIG. 6 shows the state that a semiconductor element 5 is mounted on the film carrier shown in FIG. 2 by connecting the electrode portions of the semiconductor element 5 to the via holes 3' of the film carrier. Because of the presence of a recessed portion which can fit the form of the semiconductor element 5 to he mounted thereon in the surface of the insulating layer 2', the position fitting for mounting the semiconductor 5 can be easily performed by simply placing the semiconductor element 5 in the recessed potion. Furthermore, when a solder is used as the conductive material of the connecting portions, they can be easily connected by only heating, whereby the production step can be simplified.
- FIG. 7 is a cross-sectional view showing another example of the semiconductor device of the present invention, which is a modified example of the semiconductor device shown in FIG. 6. That is, in the case of using a solder bumps, even when the size of the recessed form processed portion of the surface of the insulating layer 2' is larger than the size of a semiconductor element 5 to some extent, a self alignment effect occurs by welding of the solder and the semiconductor element 5 moves to the direction of the arrow as shown in FIG. 7. Accordingly, accurate position fitting becomes unnecessary.
- the conductive circuit is not formed on the surface of an insulating layer but is laid in the inside of the insulating layer, only the end portions of the conductive passages for connecting the land portions of an outside substrate are exposed to the surface of the insulating layer, and the ends of the conductive passages at the connecting side to a semiconductor element are not exposed, the circuit pattern can be freely designed without being influenced by the pattern on the semiconductor element. Furthermore, by forming the conductive circuit in a multilayer structure, a three-dimensional design becomes easy, and the film carrier or semiconductor device of the present invention can sufficiently correspond to fining of pitch.
Abstract
Description
Claims (5)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7114206A JPH08316271A (en) | 1995-05-12 | 1995-05-12 | Film carrier and semiconductor device using the same |
US08/722,321 US6011310A (en) | 1995-05-12 | 1996-09-27 | Film carrier and semiconductor device using the same |
EP96115745A EP0834917B1 (en) | 1995-05-12 | 1996-10-01 | Film carrier and method of forming a semiconductor device using the same |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7114206A JPH08316271A (en) | 1995-05-12 | 1995-05-12 | Film carrier and semiconductor device using the same |
US08/722,321 US6011310A (en) | 1995-05-12 | 1996-09-27 | Film carrier and semiconductor device using the same |
EP96115745A EP0834917B1 (en) | 1995-05-12 | 1996-10-01 | Film carrier and method of forming a semiconductor device using the same |
Publications (1)
Publication Number | Publication Date |
---|---|
US6011310A true US6011310A (en) | 2000-01-04 |
Family
ID=27237423
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/722,321 Expired - Fee Related US6011310A (en) | 1995-05-12 | 1996-09-27 | Film carrier and semiconductor device using the same |
Country Status (3)
Country | Link |
---|---|
US (1) | US6011310A (en) |
EP (1) | EP0834917B1 (en) |
JP (1) | JPH08316271A (en) |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
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US6297553B1 (en) * | 1998-10-30 | 2001-10-02 | Shinko Electric Industries Co., Ltd | Semiconductor device and process for producing the same |
US6571466B1 (en) | 2000-03-27 | 2003-06-03 | Amkor Technology, Inc. | Flip chip image sensor package fabrication method |
US6627864B1 (en) | 1999-11-22 | 2003-09-30 | Amkor Technology, Inc. | Thin image sensor package |
US6643923B1 (en) * | 1998-07-29 | 2003-11-11 | Sony Chemicals Corp. | Processes for manufacturing flexible wiring boards |
US20040016570A1 (en) * | 2001-10-10 | 2004-01-29 | Reo Yamamoto | Substrate and method of manufacturing the same |
KR100432136B1 (en) * | 2001-09-01 | 2004-05-17 | 동부전자 주식회사 | Chip scale package and fabrication method thereof |
US6849916B1 (en) * | 2000-11-15 | 2005-02-01 | Amkor Technology, Inc. | Flip chip on glass sensor package |
US20050051859A1 (en) * | 2001-10-25 | 2005-03-10 | Amkor Technology, Inc. | Look down image sensor package |
US20050130413A1 (en) * | 2001-09-03 | 2005-06-16 | Nec Corporation | Interconnecting substrate for carrying semiconductor device, method of producing thereof and package of semiconductor device |
US20070290344A1 (en) * | 2006-06-16 | 2007-12-20 | Samsung Electro-Mechanics Co., Ltd. | Printed circuit board for package of electronic components and manufacturing method thereof |
US20080160675A1 (en) * | 2006-12-29 | 2008-07-03 | Tessera, Inc. | Microelectronic package with thermal access |
Families Citing this family (7)
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JP3176307B2 (en) * | 1997-03-03 | 2001-06-18 | 日本電気株式会社 | Mounting structure of integrated circuit device and method of manufacturing the same |
KR100536886B1 (en) * | 1998-02-11 | 2006-05-09 | 삼성전자주식회사 | Chip scale package and method for manufacturing thereof |
JP2000150703A (en) * | 1998-11-06 | 2000-05-30 | Sony Corp | Semiconductor device and assembly method thereof |
JP3197540B2 (en) | 1999-02-05 | 2001-08-13 | ソニーケミカル株式会社 | Substrate piece and flexible substrate |
JP2001257453A (en) * | 2000-03-09 | 2001-09-21 | Shinko Electric Ind Co Ltd | Wiring board, semiconductor device, and method of manufacturing them |
JP2001308220A (en) | 2000-04-24 | 2001-11-02 | Nec Corp | Semiconductor package and its manufacturing method |
KR101134706B1 (en) * | 2010-10-01 | 2012-04-13 | 엘지이노텍 주식회사 | Leadframe and method for manufacturing the same |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH0677293A (en) * | 1992-06-25 | 1994-03-18 | Nitto Denko Corp | Film carrier and semiconductor device using the same |
US5382827A (en) * | 1992-08-07 | 1995-01-17 | Fujitsu Limited | Functional substrates for packaging semiconductor chips |
US5468999A (en) * | 1994-05-26 | 1995-11-21 | Motorola, Inc. | Liquid encapsulated ball grid array semiconductor device with fine pitch wire bonding |
US5521332A (en) * | 1992-08-31 | 1996-05-28 | Kyocera Corporation | High dielectric layer-containing alumina-based wiring substrate and package for semiconductor device |
US5530287A (en) * | 1994-09-14 | 1996-06-25 | Unisys Corporation | High density wire bond pattern for integratd circuit package |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH05175275A (en) * | 1991-12-25 | 1993-07-13 | Nec Corp | Method of mounting semiconductor chip and mounting structure |
-
1995
- 1995-05-12 JP JP7114206A patent/JPH08316271A/en active Pending
-
1996
- 1996-09-27 US US08/722,321 patent/US6011310A/en not_active Expired - Fee Related
- 1996-10-01 EP EP96115745A patent/EP0834917B1/en not_active Expired - Lifetime
Patent Citations (5)
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JPH0677293A (en) * | 1992-06-25 | 1994-03-18 | Nitto Denko Corp | Film carrier and semiconductor device using the same |
US5382827A (en) * | 1992-08-07 | 1995-01-17 | Fujitsu Limited | Functional substrates for packaging semiconductor chips |
US5521332A (en) * | 1992-08-31 | 1996-05-28 | Kyocera Corporation | High dielectric layer-containing alumina-based wiring substrate and package for semiconductor device |
US5468999A (en) * | 1994-05-26 | 1995-11-21 | Motorola, Inc. | Liquid encapsulated ball grid array semiconductor device with fine pitch wire bonding |
US5530287A (en) * | 1994-09-14 | 1996-06-25 | Unisys Corporation | High density wire bond pattern for integratd circuit package |
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Title |
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Patent Abstracts of Japan, vol. 018, No. 326 (E 1565), Jun. 21, 1994 & JP 06 077293 A (Nitto Denko Corp), Mar. 18, 1994, *the whole document*. * |
Patent Abstracts of Japan, vol. 018, No. 326 (E-1565), Jun. 21, 1994 & JP 06 077293 A (Nitto Denko Corp), Mar. 18, 1994, *the whole document*. |
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US7053312B2 (en) | 1998-07-29 | 2006-05-30 | Sony Corporation | Flexible wiring boards |
US6848176B2 (en) | 1998-07-29 | 2005-02-01 | Sony Chemicals Corporation | Process for manufacturing flexible wiring boards |
US6643923B1 (en) * | 1998-07-29 | 2003-11-11 | Sony Chemicals Corp. | Processes for manufacturing flexible wiring boards |
US20040045157A1 (en) * | 1998-07-29 | 2004-03-11 | Sony Chemicals Corp. | Flexible wiring boards |
US20040045737A1 (en) * | 1998-07-29 | 2004-03-11 | Sony Chemicals Corp. | Processes for manufacturing flexible wiring boards |
US6297553B1 (en) * | 1998-10-30 | 2001-10-02 | Shinko Electric Industries Co., Ltd | Semiconductor device and process for producing the same |
US6627864B1 (en) | 1999-11-22 | 2003-09-30 | Amkor Technology, Inc. | Thin image sensor package |
US6571466B1 (en) | 2000-03-27 | 2003-06-03 | Amkor Technology, Inc. | Flip chip image sensor package fabrication method |
US6849916B1 (en) * | 2000-11-15 | 2005-02-01 | Amkor Technology, Inc. | Flip chip on glass sensor package |
KR100432136B1 (en) * | 2001-09-01 | 2004-05-17 | 동부전자 주식회사 | Chip scale package and fabrication method thereof |
US20050130413A1 (en) * | 2001-09-03 | 2005-06-16 | Nec Corporation | Interconnecting substrate for carrying semiconductor device, method of producing thereof and package of semiconductor device |
US7338884B2 (en) * | 2001-09-03 | 2008-03-04 | Nec Corporation | Interconnecting substrate for carrying semiconductor device, method of producing thereof and package of semiconductor device |
US20040016570A1 (en) * | 2001-10-10 | 2004-01-29 | Reo Yamamoto | Substrate and method of manufacturing the same |
US20050051859A1 (en) * | 2001-10-25 | 2005-03-10 | Amkor Technology, Inc. | Look down image sensor package |
US20070290344A1 (en) * | 2006-06-16 | 2007-12-20 | Samsung Electro-Mechanics Co., Ltd. | Printed circuit board for package of electronic components and manufacturing method thereof |
US20080160675A1 (en) * | 2006-12-29 | 2008-07-03 | Tessera, Inc. | Microelectronic package with thermal access |
US7709297B2 (en) * | 2006-12-29 | 2010-05-04 | Tessera, Inc. | Microelectronic package with thermal access |
US20100197081A1 (en) * | 2006-12-29 | 2010-08-05 | Tessera, Inc. | Microelectronic package with thermal access |
US8034665B2 (en) | 2006-12-29 | 2011-10-11 | Tessera, Inc. | Microelectronic package with thermal access |
Also Published As
Publication number | Publication date |
---|---|
EP0834917A1 (en) | 1998-04-08 |
EP0834917B1 (en) | 2002-02-13 |
JPH08316271A (en) | 1996-11-29 |
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