US6128226A - Method and apparatus for operating with a close to ground signal - Google Patents
Method and apparatus for operating with a close to ground signal Download PDFInfo
- Publication number
- US6128226A US6128226A US09/244,439 US24443999A US6128226A US 6128226 A US6128226 A US 6128226A US 24443999 A US24443999 A US 24443999A US 6128226 A US6128226 A US 6128226A
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- United States
- Prior art keywords
- timing
- signal
- cell
- array
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
- G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/32—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/14—Dummy cell management; Sense reference voltage generators
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- Read Only Memory (AREA)
Abstract
Description
V.sub.1 =V.sub.2 +K.sub.1 ·(V.sub.CEL -V.sub.REF) and V.sub.2 =V.sub.0 +K.sub.2 ·V.sub.REF
where V.sub.0 =V.sub.1 =V.sub.2 when V.sub.CELL =V.sub.REF =0 and
V.sub.DATA =V.sub.DATA-0 +K.sub.3 ·(V.sub.2 -V.sub.1)=V.sub.DATA-0 +K.sub.1 ·K.sub.3 ·(V.sub.CELL-V.sub.REF)
|V.sub.cell -V.sub.ref |≧10 mV
Claims (9)
Priority Applications (1)
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US09/244,439 US6128226A (en) | 1999-02-04 | 1999-02-04 | Method and apparatus for operating with a close to ground signal |
Applications Claiming Priority (1)
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US09/244,439 US6128226A (en) | 1999-02-04 | 1999-02-04 | Method and apparatus for operating with a close to ground signal |
Publications (1)
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US6128226A true US6128226A (en) | 2000-10-03 |
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US09/244,439 Expired - Lifetime US6128226A (en) | 1999-02-04 | 1999-02-04 | Method and apparatus for operating with a close to ground signal |
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Cited By (57)
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US6233180B1 (en) * | 1999-02-04 | 2001-05-15 | Saifun Semiconductors Ltd. | Device for determining the validity of word line conditions and for delaying data sensing operation |
US6430077B1 (en) | 1997-12-12 | 2002-08-06 | Saifun Semiconductors Ltd. | Method for regulating read voltage level at the drain of a cell in a symmetric array |
US6459620B1 (en) | 2001-06-21 | 2002-10-01 | Tower Semiconductor Ltd. | Sense amplifier offset cancellation in non-volatile memory circuits by dedicated programmed reference non-volatile memory cells |
EP1248260A1 (en) * | 2001-04-05 | 2002-10-09 | Saifun Semiconductors Ltd | Architecture and scheme for a non-strobed read sequence |
US6469351B1 (en) * | 1998-06-02 | 2002-10-22 | Seiko Instruments Inc. | Electrostatic breakdown prevention circuit for semiconductor device |
US6522585B2 (en) | 2001-05-25 | 2003-02-18 | Sandisk Corporation | Dual-cell soft programming for virtual-ground memory arrays |
US6535434B2 (en) | 2001-04-05 | 2003-03-18 | Saifun Semiconductors Ltd. | Architecture and scheme for a non-strobed read sequence |
US6584017B2 (en) | 2001-04-05 | 2003-06-24 | Saifun Semiconductors Ltd. | Method for programming a reference cell |
US20030117861A1 (en) * | 2001-12-20 | 2003-06-26 | Eduardo Maayan | NROM NOR array |
US20030142544A1 (en) * | 2002-01-31 | 2003-07-31 | Eduardo Maayan | Mass storage array and methods for operation thereof |
US6614692B2 (en) | 2001-01-18 | 2003-09-02 | Saifun Semiconductors Ltd. | EEPROM array and method for operation thereof |
US6633496B2 (en) | 1997-12-12 | 2003-10-14 | Saifun Semiconductors Ltd. | Symmetric architecture for memory cells having widely spread metal bit lines |
US6633499B1 (en) | 1997-12-12 | 2003-10-14 | Saifun Semiconductors Ltd. | Method for reducing voltage drops in symmetric array architectures |
US6636440B2 (en) | 2001-04-25 | 2003-10-21 | Saifun Semiconductors Ltd. | Method for operation of an EEPROM array, including refresh thereof |
US6643181B2 (en) | 2001-10-24 | 2003-11-04 | Saifun Semiconductors Ltd. | Method for erasing a memory cell |
US6671206B2 (en) | 2001-08-31 | 2003-12-30 | Micron Technology, Inc. | High voltage low power sensing device for flash memory |
US6677805B2 (en) | 2001-04-05 | 2004-01-13 | Saifun Semiconductors Ltd. | Charge pump stage with body effect minimization |
US6687161B2 (en) | 2001-01-03 | 2004-02-03 | Micron Technology, Inc. | Sensing scheme for low-voltage flash memory |
US6775186B1 (en) | 2003-07-03 | 2004-08-10 | Tower Semiconductor Ltd. | Low voltage sensing circuit for non-volatile memory device |
US20040165464A1 (en) * | 2001-01-03 | 2004-08-26 | Micron Technology, Inc. | Fast sensing scheme for floating-gate memory cells |
US6803299B2 (en) | 1997-07-30 | 2004-10-12 | Saifun Semiconductors Ltd. | Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
EP1473732A1 (en) * | 2003-04-29 | 2004-11-03 | Saifun Semiconductors Ltd | Apparatus and method of multi-level sensing in a memory array |
US20040218426A1 (en) * | 2003-04-29 | 2004-11-04 | Oleg Dadashev | Apparatus and methods for multi-level sensing in a memory array |
US6826107B2 (en) | 2002-08-01 | 2004-11-30 | Saifun Semiconductors Ltd. | High voltage insertion in flash memory cards |
US6829172B2 (en) | 2000-05-04 | 2004-12-07 | Saifun Semiconductors Ltd. | Programming of nonvolatile memory cells |
US20050057953A1 (en) * | 2003-09-16 | 2005-03-17 | Eli Lusky | Reading array cell with matched reference cell |
US20050088878A1 (en) * | 2003-10-27 | 2005-04-28 | Tower Semiconductor Ltd. | Neighbor effect cancellation in memory array architecture |
US20050180212A1 (en) * | 2004-02-16 | 2005-08-18 | Matsushita Electric Industrial Co., Ltd. | Non-volatile semiconductor memory device |
US20050232024A1 (en) * | 2004-04-19 | 2005-10-20 | Shahar Atir | Method for reading a memory array with neighbor effect cancellation |
US6963505B2 (en) | 2002-10-29 | 2005-11-08 | Aifun Semiconductors Ltd. | Method circuit and system for determining a reference voltage |
US6967896B2 (en) | 2003-01-30 | 2005-11-22 | Saifun Semiconductors Ltd | Address scramble |
US6992932B2 (en) | 2002-10-29 | 2006-01-31 | Saifun Semiconductors Ltd | Method circuit and system for read error detection in a non-volatile memory array |
US20060126389A1 (en) * | 2004-12-14 | 2006-06-15 | Tower Semiconductor Ltd. | Integrator-based current sensing circuit for reading memory cells |
US20070064479A1 (en) * | 2005-09-22 | 2007-03-22 | Nec Electronics Corporation | Non-volatile semiconductor memory device |
US20070159887A1 (en) * | 2006-01-09 | 2007-07-12 | Macronix International Co., Ltd. | Method and Apparatus for Programming Nonvolatile Memory |
US7257025B2 (en) | 2004-12-09 | 2007-08-14 | Saifun Semiconductors Ltd | Method for reading non-volatile memory cells |
US20080130359A1 (en) * | 2002-07-10 | 2008-06-05 | Eduardo Maayan | Multiple use memory chip |
US20090129164A1 (en) * | 2007-11-15 | 2009-05-21 | Makoto Kojima | Semiconductor non-volatile memory |
US20090129166A1 (en) * | 2007-11-15 | 2009-05-21 | Eduardo Maayan | Method, circuit and system for sensing a cell in a non-volatile memory array |
US20090135651A1 (en) * | 2006-07-10 | 2009-05-28 | Matsushita Electric Industrial Co., Ltd. | Current or voltage measurement circuit, sense circuit, semiconductor non-volatile memory, and differential amplifier |
US7652930B2 (en) | 2004-04-01 | 2010-01-26 | Saifun Semiconductors Ltd. | Method, circuit and system for erasing one or more non-volatile memory cells |
US7668017B2 (en) | 2005-08-17 | 2010-02-23 | Saifun Semiconductors Ltd. | Method of erasing non-volatile memory cells |
US7675782B2 (en) | 2002-10-29 | 2010-03-09 | Saifun Semiconductors Ltd. | Method, system and circuit for programming a non-volatile memory array |
US7692961B2 (en) | 2006-02-21 | 2010-04-06 | Saifun Semiconductors Ltd. | Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection |
US7701779B2 (en) | 2006-04-27 | 2010-04-20 | Sajfun Semiconductors Ltd. | Method for programming a reference cell |
US7743230B2 (en) | 2003-01-31 | 2010-06-22 | Saifun Semiconductors Ltd. | Memory array programming circuit and a method for using the circuit |
US7760554B2 (en) | 2006-02-21 | 2010-07-20 | Saifun Semiconductors Ltd. | NROM non-volatile memory and mode of operation |
US7786512B2 (en) | 2005-07-18 | 2010-08-31 | Saifun Semiconductors Ltd. | Dense non-volatile memory array and method of fabrication |
US7808818B2 (en) | 2006-01-12 | 2010-10-05 | Saifun Semiconductors Ltd. | Secondary injection for NROM |
US7864612B2 (en) | 2003-09-16 | 2011-01-04 | Spansion Israel Ltd | Reading array cell with matched reference cell |
US7964459B2 (en) | 2004-10-14 | 2011-06-21 | Spansion Israel Ltd. | Non-volatile memory structure and method of fabrication |
US8053812B2 (en) | 2005-03-17 | 2011-11-08 | Spansion Israel Ltd | Contact in planar NROM technology |
US8253452B2 (en) | 2006-02-21 | 2012-08-28 | Spansion Israel Ltd | Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same |
US8400841B2 (en) | 2005-06-15 | 2013-03-19 | Spansion Israel Ltd. | Device to program adjacent storage cells of different NROM cells |
US20160019972A1 (en) * | 2013-03-15 | 2016-01-21 | Silicon Storage Technology, Inc. | Self-Timer For Sense Amplifier In Memory Device |
US11423984B2 (en) | 2020-04-06 | 2022-08-23 | Crossbar, Inc. | Distinct chip identifier sequence utilizing unclonable characteristics of resistive memory on a chip |
US11823739B2 (en) | 2020-04-06 | 2023-11-21 | Crossbar, Inc. | Physically unclonable function (PUF) generation involving high side programming of bits |
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US4916671A (en) * | 1988-09-06 | 1990-04-10 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having sense amplifier having improved activation timing thereof and operating method thereof |
US5812456A (en) * | 1996-10-01 | 1998-09-22 | Microchip Technology Incorporated | Switched ground read for EPROM memory array |
US5936888A (en) * | 1997-07-07 | 1999-08-10 | Nec Corporation | Semiconductor non-volatile memory device having floating gate type reference cell short-circuited between control gate electrode and floating gate electrode |
-
1999
- 1999-02-04 US US09/244,439 patent/US6128226A/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US4916671A (en) * | 1988-09-06 | 1990-04-10 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device having sense amplifier having improved activation timing thereof and operating method thereof |
US5812456A (en) * | 1996-10-01 | 1998-09-22 | Microchip Technology Incorporated | Switched ground read for EPROM memory array |
US5936888A (en) * | 1997-07-07 | 1999-08-10 | Nec Corporation | Semiconductor non-volatile memory device having floating gate type reference cell short-circuited between control gate electrode and floating gate electrode |
Cited By (88)
Publication number | Priority date | Publication date | Assignee | Title |
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US6803299B2 (en) | 1997-07-30 | 2004-10-12 | Saifun Semiconductors Ltd. | Non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
US6633496B2 (en) | 1997-12-12 | 2003-10-14 | Saifun Semiconductors Ltd. | Symmetric architecture for memory cells having widely spread metal bit lines |
US6430077B1 (en) | 1997-12-12 | 2002-08-06 | Saifun Semiconductors Ltd. | Method for regulating read voltage level at the drain of a cell in a symmetric array |
US6633499B1 (en) | 1997-12-12 | 2003-10-14 | Saifun Semiconductors Ltd. | Method for reducing voltage drops in symmetric array architectures |
US6469351B1 (en) * | 1998-06-02 | 2002-10-22 | Seiko Instruments Inc. | Electrostatic breakdown prevention circuit for semiconductor device |
US6233180B1 (en) * | 1999-02-04 | 2001-05-15 | Saifun Semiconductors Ltd. | Device for determining the validity of word line conditions and for delaying data sensing operation |
US6829172B2 (en) | 2000-05-04 | 2004-12-07 | Saifun Semiconductors Ltd. | Programming of nonvolatile memory cells |
US20070140004A1 (en) * | 2001-01-03 | 2007-06-21 | Micron Technology, Inc. | Sensing scheme for low-voltage flash memory |
US7403423B2 (en) | 2001-01-03 | 2008-07-22 | Micron Technology, Inc. | Sensing scheme for low-voltage flash memory |
US20050041469A1 (en) * | 2001-01-03 | 2005-02-24 | Micron Technology, Inc. | Sensing scheme for low-voltage flash memory |
US6822904B2 (en) | 2001-01-03 | 2004-11-23 | Micron Technology, Inc. | Fast sensing scheme for floating-gate memory cells |
US6687161B2 (en) | 2001-01-03 | 2004-02-03 | Micron Technology, Inc. | Sensing scheme for low-voltage flash memory |
US7206240B2 (en) | 2001-01-03 | 2007-04-17 | Micron Technology, Inc. | Fast sensing scheme for floating-gate memory cells |
US6813190B2 (en) | 2001-01-03 | 2004-11-02 | Micron Technology, Inc. | Methods of sensing a programmed state of a floating-gate memory cell |
US7200041B2 (en) | 2001-01-03 | 2007-04-03 | Micron Technology, Inc. | Sensing scheme for low-voltage flash memory |
US20040165464A1 (en) * | 2001-01-03 | 2004-08-26 | Micron Technology, Inc. | Fast sensing scheme for floating-gate memory cells |
US20040105306A1 (en) * | 2001-01-03 | 2004-06-03 | Micron Technology, Inc. | Methods of sensing a programmed state of a floating-gate memory cell |
US6614692B2 (en) | 2001-01-18 | 2003-09-02 | Saifun Semiconductors Ltd. | EEPROM array and method for operation thereof |
EP1248260A1 (en) * | 2001-04-05 | 2002-10-09 | Saifun Semiconductors Ltd | Architecture and scheme for a non-strobed read sequence |
US20040130385A1 (en) * | 2001-04-05 | 2004-07-08 | Shor Joseph S. | Charge pump stage with body effect minimization |
US6584017B2 (en) | 2001-04-05 | 2003-06-24 | Saifun Semiconductors Ltd. | Method for programming a reference cell |
US20060268621A1 (en) * | 2001-04-05 | 2006-11-30 | Saifun Semiconductors, Ltd. | Method for programming a reference cell |
US6677805B2 (en) | 2001-04-05 | 2004-01-13 | Saifun Semiconductors Ltd. | Charge pump stage with body effect minimization |
US6535434B2 (en) | 2001-04-05 | 2003-03-18 | Saifun Semiconductors Ltd. | Architecture and scheme for a non-strobed read sequence |
US6636440B2 (en) | 2001-04-25 | 2003-10-21 | Saifun Semiconductors Ltd. | Method for operation of an EEPROM array, including refresh thereof |
US6522585B2 (en) | 2001-05-25 | 2003-02-18 | Sandisk Corporation | Dual-cell soft programming for virtual-ground memory arrays |
US6459620B1 (en) | 2001-06-21 | 2002-10-01 | Tower Semiconductor Ltd. | Sense amplifier offset cancellation in non-volatile memory circuits by dedicated programmed reference non-volatile memory cells |
US20040085840A1 (en) * | 2001-08-29 | 2004-05-06 | Micron Technology, Inc. | High voltage low power sensing device for flash memory |
US6671206B2 (en) | 2001-08-31 | 2003-12-30 | Micron Technology, Inc. | High voltage low power sensing device for flash memory |
US6914821B2 (en) | 2001-08-31 | 2005-07-05 | Micron Technology, Inc. | High voltage low power sensing device for flash memory |
US6643181B2 (en) | 2001-10-24 | 2003-11-04 | Saifun Semiconductors Ltd. | Method for erasing a memory cell |
US20030117861A1 (en) * | 2001-12-20 | 2003-06-26 | Eduardo Maayan | NROM NOR array |
US20030142544A1 (en) * | 2002-01-31 | 2003-07-31 | Eduardo Maayan | Mass storage array and methods for operation thereof |
US6975536B2 (en) | 2002-01-31 | 2005-12-13 | Saifun Semiconductors Ltd. | Mass storage array and methods for operation thereof |
US7738304B2 (en) | 2002-07-10 | 2010-06-15 | Saifun Semiconductors Ltd. | Multiple use memory chip |
US20080130359A1 (en) * | 2002-07-10 | 2008-06-05 | Eduardo Maayan | Multiple use memory chip |
US7573745B2 (en) | 2002-07-10 | 2009-08-11 | Saifun Semiconductors Ltd. | Multiple use memory chip |
US6826107B2 (en) | 2002-08-01 | 2004-11-30 | Saifun Semiconductors Ltd. | High voltage insertion in flash memory cards |
US7675782B2 (en) | 2002-10-29 | 2010-03-09 | Saifun Semiconductors Ltd. | Method, system and circuit for programming a non-volatile memory array |
US6963505B2 (en) | 2002-10-29 | 2005-11-08 | Aifun Semiconductors Ltd. | Method circuit and system for determining a reference voltage |
US6992932B2 (en) | 2002-10-29 | 2006-01-31 | Saifun Semiconductors Ltd | Method circuit and system for read error detection in a non-volatile memory array |
US6967896B2 (en) | 2003-01-30 | 2005-11-22 | Saifun Semiconductors Ltd | Address scramble |
US7743230B2 (en) | 2003-01-31 | 2010-06-22 | Saifun Semiconductors Ltd. | Memory array programming circuit and a method for using the circuit |
US7142464B2 (en) | 2003-04-29 | 2006-11-28 | Saifun Semiconductors Ltd. | Apparatus and methods for multi-level sensing in a memory array |
US20040218426A1 (en) * | 2003-04-29 | 2004-11-04 | Oleg Dadashev | Apparatus and methods for multi-level sensing in a memory array |
EP1473732A1 (en) * | 2003-04-29 | 2004-11-03 | Saifun Semiconductors Ltd | Apparatus and method of multi-level sensing in a memory array |
US6775186B1 (en) | 2003-07-03 | 2004-08-10 | Tower Semiconductor Ltd. | Low voltage sensing circuit for non-volatile memory device |
US7864612B2 (en) | 2003-09-16 | 2011-01-04 | Spansion Israel Ltd | Reading array cell with matched reference cell |
US20050057953A1 (en) * | 2003-09-16 | 2005-03-17 | Eli Lusky | Reading array cell with matched reference cell |
US6954393B2 (en) | 2003-09-16 | 2005-10-11 | Saifun Semiconductors Ltd. | Reading array cell with matched reference cell |
US6937523B2 (en) | 2003-10-27 | 2005-08-30 | Tower Semiconductor Ltd. | Neighbor effect cancellation in memory array architecture |
US20050088878A1 (en) * | 2003-10-27 | 2005-04-28 | Tower Semiconductor Ltd. | Neighbor effect cancellation in memory array architecture |
US7123510B2 (en) | 2004-02-16 | 2006-10-17 | Matsushita Electric Industrial Co., Ltd. | Non-volatile semiconductor memory device |
US20050180212A1 (en) * | 2004-02-16 | 2005-08-18 | Matsushita Electric Industrial Co., Ltd. | Non-volatile semiconductor memory device |
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US7964459B2 (en) | 2004-10-14 | 2011-06-21 | Spansion Israel Ltd. | Non-volatile memory structure and method of fabrication |
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US7450427B2 (en) | 2005-09-22 | 2008-11-11 | Nec Electronics Corporation | Non-volatile semiconductor memory device |
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US7593264B2 (en) * | 2006-01-09 | 2009-09-22 | Macronix International Co., Ltd. | Method and apparatus for programming nonvolatile memory |
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US8253452B2 (en) | 2006-02-21 | 2012-08-28 | Spansion Israel Ltd | Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same |
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US7616488B2 (en) | 2006-07-10 | 2009-11-10 | Panasonic Corporation | Current or voltage measurement circuit, sense circuit, semiconductor non-volatile memory, and differential amplifier |
US20090135651A1 (en) * | 2006-07-10 | 2009-05-28 | Matsushita Electric Industrial Co., Ltd. | Current or voltage measurement circuit, sense circuit, semiconductor non-volatile memory, and differential amplifier |
US7710780B2 (en) | 2007-11-15 | 2010-05-04 | Panasonic Corporation | Semiconductor non-volatile memory |
US20090129166A1 (en) * | 2007-11-15 | 2009-05-21 | Eduardo Maayan | Method, circuit and system for sensing a cell in a non-volatile memory array |
US20090129164A1 (en) * | 2007-11-15 | 2009-05-21 | Makoto Kojima | Semiconductor non-volatile memory |
US20160019972A1 (en) * | 2013-03-15 | 2016-01-21 | Silicon Storage Technology, Inc. | Self-Timer For Sense Amplifier In Memory Device |
US9620235B2 (en) * | 2013-03-15 | 2017-04-11 | Silicon Storage Technology, Inc. | Self-timer for sense amplifier in memory device |
US11423984B2 (en) | 2020-04-06 | 2022-08-23 | Crossbar, Inc. | Distinct chip identifier sequence utilizing unclonable characteristics of resistive memory on a chip |
US11430517B2 (en) | 2020-04-06 | 2022-08-30 | Crossbar, Inc. | Distinct chip identifier sequence utilizing unclonable characteristics of resistive memory on a chip |
US11430516B2 (en) | 2020-04-06 | 2022-08-30 | Crossbar, Inc. | Distinct chip identifier sequence utilizing unclonable characteristics of resistive memory on a chip |
US11437100B2 (en) * | 2020-04-06 | 2022-09-06 | Crossbar, Inc. | Distinct chip identifier sequence utilizing unclonable characteristics of resistive memory on a chip |
US11450384B2 (en) | 2020-04-06 | 2022-09-20 | Crossbar, Inc. | Distinct chip identifier sequence utilizing unclonable characteristics of resistive memory on a chip |
US11823739B2 (en) | 2020-04-06 | 2023-11-21 | Crossbar, Inc. | Physically unclonable function (PUF) generation involving high side programming of bits |
US11967376B2 (en) | 2020-04-06 | 2024-04-23 | Crossbar, Inc. | Distinct chip identifier sequence utilizing unclonable characteristics of resistive memory on a chip |
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