|Número de publicación||US6172554 B1|
|Tipo de publicación||Concesión|
|Número de solicitud||US 09/160,363|
|Fecha de publicación||9 Ene 2001|
|Fecha de presentación||24 Sep 1998|
|Fecha de prioridad||24 Sep 1998|
|Número de publicación||09160363, 160363, US 6172554 B1, US 6172554B1, US-B1-6172554, US6172554 B1, US6172554B1|
|Inventores||Pochung Young, Li-Chun Li|
|Cesionario original||Mosel Vitelic, Inc.|
|Exportar cita||BiBTeX, EndNote, RefMan|
|Citas de patentes (6), Citada por (6), Clasificaciones (5), Eventos legales (6)|
|Enlaces externos: USPTO, Cesión de USPTO, Espacenet|
1. Field of the Invention
The present invention relates to providing voltages.
2. Description of Related Art
Voltage generating circuits are widely used in electrical and electronic devices. For instance, substrate bias generator circuits, also referred to as back-bias generators, are used in semiconductor devices which require the substrate region to be biased to a predetermined voltage. For example, in dynamic random access memories (DRAM) the substrate region is negatively biased to prevent the DRAM cells from losing the stored information. The back-bias generator includes a voltage multiplier circuit, commonly referred to as charge pump, for providing the negative Back-Bias Voltage (VBB). The charge pump is usually accompanied by a VBB detector circuit. The detector circuit regulates the charge pump such that VBB is maintained as close to a target VBB value as possible.
The detector circuit constantly senses the VBB voltage level, and if VBB becomes more negative than the target VBB, the detector circuit turns off the charge pump thereby allowing VBB to drift back to the target VBB; and if VBB becomes less negative than the target VBB, the detector circuit turns on the charge pump to pump VBB back to the target VBB.
FIG. 1 shows a conventional VBB detector circuit 17. Serially connected resistors R1 and R2 are coupled between the power supply Vcc and VBB terminal 15. Vcc is provided by a power supply external to the device, and VBB is generated internally by a charge pump (not shown). Inverter 12 has its input terminal connected to node 11 which is the node between R1 and R2. The output terminal of inverter 12 also provides the output terminal Q10 of the detector circuit 17. Output terminal Q10 is connected to the charge pump.
Vcc, R1, R2, and VBB form a voltage divider which sets the voltage VA at node 11 in accordance with the following equation:
Resistors R1 and R2 are selected so that, for the nominal Vcc value and target VBB, the voltage VA equals the trip point of inverter 12. If the charge pump causes VBB to become more negative than the target value, VA drops below the trip point of inverter 12 causing Q10 to go high. The high level at Q10 turns off the charge pump, allowing VBB to increase back to the target value. Alternatively, if VBB becomes less negative than the target VBB, VA rises above the trip point of inverter 12 causing Q10 to go low. The low level of Q10 turns on the charge pump causing VBB to become more negative. Thus, VBB is maintained at the target value.
Circuit 17 however, suffers from a number of drawbacks, one of which is that VBB varies with changes in Vcc. In particular, as shown by equation (1), if Vcc increases, VBB has to become more negative to keep VA at the trip point of inverter 12 (this assumes that inverter 12 is designed so that its trip point is insensitive to Vcc). This increases junction leakage as explained in more detail below. The increased junction leakage adversely impacts the operation of the device. For example, in a DRAM the increased junction leakage can cause loss of information stored in the memory cells; and more generally, the high leakage current results in higher static power consumption, e.g., high stand-by current (ISB).
As both Vcc and |VBB| increase, leakage current increases across the junction between Vcc-biased n+ diffusion regions in the VBB-biased P-type substrate. This is more clearly illustrated in FIG. 2. FIG. 2 shows a P-type substrate 23 biased to VBB through the p+ diffusion region 22. The n+ diffusion region 21 represents one of many n+ diffusion regions biased to Vcc. The pn junction formed by the P-substrate 23 and the n+ diffusion 21 is reverse biased since a positive voltage Vcc is applied to the negatively charged n+ diffusion 21 and a negative voltage VBB is applied to the positively charged P-type substrate 23.
In accordance with the I-V characteristics of a pn junction, as the reverse voltage across the pn junction approaches the junction break down voltage (VBD), larger leakage current flows through the junction. Therefore, an increase in Vcc and the resulting more negative VBB, combine to cause a greater reverse voltage across the junction formed by the n+ region 21 and substrate 23.
The undesirable effects of the large leakage currents, such as high ISB and data loss in DRAM cells, are magnified as technology moves to smaller geometries and memory devices move to higher densities.
Another drawback of circuit 17 (FIG. 1) is that it does not prevent VBB from becoming positive. If VBB becomes positive by as little as 0.8V, junctions formed by Vss-biased n+ regions and the VBB-biased substrate become forward biased. This can lead to latch-up which may destroy the device.
FIG. 3A shows a prior art detector circuit 37 which prevents VBB from becoming positive. Circuit 37 is identical to circuit 17 of FIG. 1 except that NMOS transistor M30 is connected between node 11 and R2. With the gate of M30 connected to Vss, M30 turns off when its source (lead 33) reaches minus one threshold voltage (−VTN), VTN being that of M30. When M30 turns off, VA rises to Vcc. This causes the charge pump to turn on and pump VBB to a more negative voltage.
It is desirable to provide an improved VBB detector.
The inventors have observed that it is sometimes desirable to obtain VBB values closer to 0V than those provided by the VBB detector of FIG. 3A. The VBB range for circuit 37 (FIG. 3A) is illustrated in FIG. 3B. The horizontal axis represents Vcc and the vertical axis represents VBB. The threshold voltage VTN is that of M30 which is typically about 1V. Voltage VX represents the upper limit to which the charge pump may pump VBB (the upper limit typically equals the junction breakdown voltage VBD). The region bounded by −VTN and −VX (shown as the cross-hatched region) represents the VBB voltage range which circuit 37 tolerates. Given the technology trend towards smaller geometries and the above-mentioned problems caused by the increased junction leakage, lower VBB target values in the range of −1V to 0V (e.g. −0.5V) are highly desirable.
Accordingly, a VBB detector circuit is needed wherein VBB is made insensitive to Vcc variations, and also the range of possible VBB values is increased without compromising power consumption.
In some embodiments of the present invention, a voltage is provided which is substantially insensitive to power supply voltage variations. In some embodiments, the voltage is a bias voltage VBB. The substantial insensitivity to the power supply voltage variations is achieved in some embodiments by using a detector circuit which generates a signal substantially insensitive to power supply voltage variations. For example, in some detector circuit embodiments, the resistor R1 of FIG. 1 is replaced by a current source. The current provided by the current source is substantially insensitive to power supply voltage variations. As a result, the voltage on node 11 is substantially insensitive to power supply voltage variations. In some embodiments, the inverter 12 is also made substantially insensitive to power supply voltage variations. Therefore, VBB becomes substantially insensitive to power supply voltage variations.
Some embodiments of the present invention allow a voltage generated by a voltage generating circuit to get arbitrarily close to 0 volts while still not allowing the voltage to become positive. Thus, some VBB generators include a circuit that allows VBB to get arbitrarily close to 0 volts but does not allow VBB to become positive. In some embodiments, this is achieved by biasing the gate of transistor M30 of FIG. 3A to the threshold voltage VTN of transistor M30.
Other features and advantages of the invention are described below. The invention is defined by the appended claims.
FIG. 1 is a circuit diagram of a conventional VBB detector circuit.
FIG. 2 is a cross section of a portion of a prior art integrated circuit.
FIG. 3A is a circuit diagram of a prior art VBB detector circuit which prevents VBB from becoming positive.
FIG. 3B is a voltage diagram showing the VBB voltage range for circuit 37 of FIG. 3A.
FIG. 4A is a circuit diagram of a VBB detector circuit in accordance with the present invention.
FIG. 4B is a circuit diagram of one implementation of inverter 12 of FIG. 4A.
FIG. 5A is a circuit diagram of one embodiment of the detect or circuit 47 in FIG. 4A.
FIG. 5B is a voltage diagram showing the VBB voltage range for circuit 57 of FIG. 5A.
FIG. 4A shows a voltage detector circuit 47 in accordance with the present invention. The resistor R1 of FIG. 1 is replaced with a power-supply-voltage-insensitive current source 46. The current source 46 is connected between Vcc and node 11. Resistor R2 is connected between node 11 and VBB terminal 15 (note that R2 may be implemented using a MOS transistor, or a strip of polysilicon, or a strip of diffusion). Inverter 12 has its input terminal connected to node 11, and its output terminal represents the output terminal Q10 of the detector circuit 47. The output terminal Q10 is connected to an input terminal 13 of a charge pump 48. The charge pump 48 provides the voltage VBB on terminal 15.
The operation of circuit 47 is similar to that of circuit 17 in FIG. 1. However, by replacing R1 (FIG. 1) with the current source 46, the operation of the detector circuit 47 is made insensitive to Vcc variations. This is because the current source 46 provides a constant current despite Vcc variations.
The current equation written about node 11 yields the following:
IS represents the constant current provided by current source 46. Unlike equation (1), equation (2) does not include Vcc. Thus, regulation of the charge pump 48 by the detector circuit 47 is not affected by changes in Vcc.
Note that despite the absence of Vcc in equation (2), the trip point of inverter 12, to which VA is biased, may vary with Vcc. However, in some embodiments simple circuit techniques such as proper ratioing of the sizes of the pull up and pull down transistors of inverter 12 can be used to eliminate the dependence of inverter 12 trip point on Vcc. FIG. 4B shows a CMOS implementation of inverter 12 of FIG. 4A. By selecting a substantially larger transistor size for the pull down transistor M49 than the pull up transistor M48, the trip point of inverter 12 is made primarily dependent on the threshold voltage of the pull down transistor M49 and not Vcc.
FIG. 5A shows another VBB detector circuit 57. Transistors M51, M52, M53, and M54 collectively implement a constant current source 46 which is also used in some embodiments of FIG. 4A. M51 is a PMOS transistor with its source connected to Vcc, its drain connected to node 11, and its gate connected to node 53. M52 is a PMOS transistor with its source connected to Vcc, and its gate and drain connected to node 52. M53 is a PMOS transistor with its source connected to node 52, and its gate and drain connected to node 53. M54 is an NMOS transistor with its drain connected to node 53, its gate connected to Vcc, and its source connected to Vss.
Transistors M30, M55 and M56 prevent VBB from becoming positive, and also set the upper limit for VBB. M30 is a NMOS transistor with its drain connected to node 11, its gate connected to node 54, and its source connected to lead 33. M55 is a PMOS transistor with its source connected to Vcc, its gate connected to Vss, and its drain connected to node 54. M56 is a NMOS transistor with its drain and gate connected to node 54, and its source connected to Vss. Finally, resistor R2 is connected between lead 33 and VBB terminal 15.
The operation of circuit 57 will be described by first describing the operation of the section comprising M51, M52, M53, and M54, and then the operation of the section comprising M30, M55 and M56. As is well known, the current through a MOS transistor is a function of its gate to source voltage (VGS) and its drain to source voltage (VDS). Therefore, to eliminate the impact of Vcc on the current through transistor M51, we make its VGS and VDS independent from Vcc.
More particularly, M52 and M53 are diode connected so that the voltage at node 53 is at Vcc minus two threshold voltages (Vcc−2|VTP|), where VTP is threshold voltage of the PMOS transistors in FIG. 5A. M54 is a small NMOS leaker transistor which is kept on at all times by connecting its gate to Vcc. M54 maintains a small amount of current flowing through M52 and M53 so that M52 and M53 bias node 53 to Vcc minus 2|VTP|.
Hence, the gate to source voltage (VGS) of M51 is:
which does not depend on Vcc.
The impact of Vcc variations on VDS is eliminated by maintaining M51 in saturation at all times. A PMOS transistor is in saturation as long as the following equation is satisfied:
VTP represents the threshold voltage of M51. VGS is provided by equation (3), and VDS is determined as follows:
Plugging equations (3) and (5) into equation (4) yields:
Equation (6) is satisfied for VA values less than Vcc minus |VTP|. Assuming Vcc to be 5V and VTP to be −1V, equation (6) is satisfied for any VA values less than or equal to 4V. Since VA is biased to be equal to the trip point of inverter 12, inverter 12 can be designed so that its trip point is below 4V. In fact, as mentioned earlier, to ensure circuit 57 is Vcc insensitive, the inverter 12 trip point is set close to VTN (a NMOS threshold) or about 1V.
The invention is not limited to the above-described circuit implementation of the current source 46 (FIG. 4A). For example, in obtaining a desired voltage across the gate to source of M51, some embodiments may include only one of transistors M52, M53 (FIG. 5A), or more than two such transistor. Alternatively, the current through M51 may be multiplied by current mirrors if needed.
Transistors M30, M55 and M56 allow the VBB voltage range for circuit 57 to include the range between −VX and 0V, as indicated in FIG. 5B. This is made possible by biasing the gate of M30 (FIG. 5A) to VTN using M55 and M56. With its gate at VTN (1V), M30 turns off for source voltages (voltages at lead 33) greater than 0V.
The diode connected M56 causes node 54 to always remain at one VTN above Vss. M55 is a small PMOS leaker transistor which is kept on at all times by connecting its gate to Vss. M55 maintains a small amount of current flowing through M56 so that M56 biases node 54 to VTN.
Note that by selecting small transistor sizes for the leaker transistors M54 and M55, the static power consumption of circuit 57 is minimized.
Also note that the power supply voltage Vcc in FIGS. 4A, 4B and 5A may be provided on a power supply pin of a device (such as a DRAM) in which circuit 57 is housed, or alternatively, Vcc is generated internal to such device as a reference voltage.
Finally, note that the VBB voltage may be applied to a silicon substrate in which the memory cells of an integrated memory (such as a DRAM) reside. Alternatively, VBB may be applied to a well region in which the memory cells of such integrated memory reside, the well region being formed in a silicon substrate having a conductivity type opposite the well region.
Addendum A at the end of this description provides transistor sizes and other implementation details for some embodiments.
The above description of the present invention is intended to be illustrative and not limiting. The invention is further intended to include all variations and modifications falling within the scope of the appended claims.
The following table provides transistor width and length dimensions (in micrometers-μm) for some embodiments of FIG. 5A. Also, transistor sizes are provided for inverter 12 of FIG. 4B which is similar to inverter 12 of FIG. 5A.
In these embodiments, the resistor R2 (FIG. 5A) is 2 Mega Ω. A suitable charge pump 48 (FIG. 4A) is described in U.S. patent application Ser. No. 08/853,291 filed on May 9, 1997, incorporated herein by reference, now U.S. Pat. No. 5,907,257, issued May 25, 1999.
|Patente citada||Fecha de presentación||Fecha de publicación||Solicitante||Título|
|US4964082 *||27 Sep 1988||16 Oct 1990||Hitachi, Ltd.||Semiconductor memory device having a back-bias voltage generator|
|US5270584 *||26 Ago 1992||14 Dic 1993||Nec Corporation||Semiconductor integrated circuit|
|US5744997 *||26 Abr 1996||28 Abr 1998||Samsung Electronics, Co., Ltd.||Substrate bias voltage controlling circuit in semiconductor memory device|
|US5744998 *||3 Dic 1996||28 Abr 1998||Mitsubishi Denki Kabushiki Kaisha||Internal voltage detecting circuit having superior responsibility|
|US5872479 *||3 Ene 1996||16 Feb 1999||Lg Semicon Co., Ltd.||Apparatus for regulating substrate voltage in semiconductor device|
|US6005434 *||14 Feb 1996||21 Dic 1999||Mitsubishi Denki Kabushiki Kaisha||Substrate potential generation circuit that can suppress variation of output voltage with respect to change in external power supply voltage and environment temperature|
|Patente citante||Fecha de presentación||Fecha de publicación||Solicitante||Título|
|US6649425 *||4 Abr 2001||18 Nov 2003||Sun Microsystems, Inc.||Method to reduce leakage during a semi-conductor burn-in procedure|
|US6800908 *||25 Sep 2002||5 Oct 2004||Intel Corporation||Apparatus and circuit having reduced leakage current and method therefor|
|US6977529 *||3 Mar 2003||20 Dic 2005||Ics Technologies, Inc.||Differential clock signal detection circuit|
|US7109782||5 Oct 2004||19 Sep 2006||Freescale Semiconductor, Inc.||Well bias voltage generator|
|US7319611||25 Ene 2006||15 Ene 2008||Macronix International Co., Ltd.||Bitline transistor architecture for flash memory|
|US7733132 *||7 Abr 2008||8 Jun 2010||Hynix Semiconductor Inc.||Bulk bias voltage level detector in semiconductor memory device|
|Clasificación de EE.UU.||327/535, 327/537|
|24 Sep 1998||AS||Assignment|
Owner name: MOSEL VITELIC, INC., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:YOUNG, POCHUNG;LI, LI-CHUN;REEL/FRAME:009478/0967
Effective date: 19980922
|23 Jul 2002||CC||Certificate of correction|
|24 May 2004||AS||Assignment|
|25 Jun 2004||FPAY||Fee payment|
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