US6222414B1 - Bipolar-plus-DMOS mixed-typology power output stage - Google Patents

Bipolar-plus-DMOS mixed-typology power output stage Download PDF

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US6222414B1
US6222414B1 US08/351,578 US35157894A US6222414B1 US 6222414 B1 US6222414 B1 US 6222414B1 US 35157894 A US35157894 A US 35157894A US 6222414 B1 US6222414 B1 US 6222414B1
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transistor
stage
power
integrated
bipolar
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US08/351,578
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Carlo Cini
Fabrizio Stefani
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STMicroelectronics SRL
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SGS Thomson Microelectronics SRL
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Assigned to SGS-THOMSON MICROELECTRONICS, S.R.L. reassignment SGS-THOMSON MICROELECTRONICS, S.R.L. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CINI, CARLO, STEFANI, FABRIZIO
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/30—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor
    • H03F3/3001—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor with field-effect transistors
    • H03F3/3008—Bifet SEPP output stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/30—Indexing scheme relating to single-ended push-pull [SEPP]; Phase-splitters therefor
    • H03F2203/30012—Indexing scheme relating to single-ended push-pull [SEPP]; Phase-splitters therefor the two SEPP amplifying transistors are Darlington composite transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/30—Indexing scheme relating to single-ended push-pull [SEPP]; Phase-splitters therefor
    • H03F2203/30051—Indexing scheme relating to single-ended push-pull [SEPP]; Phase-splitters therefor the SEPP amplifying transistors are composed of multiple coupled transistors

Definitions

  • the present invention relates to an output stage for an integrated power amplifier particularly suited for audio amplifiers.
  • the output stages of power amplifiers are normally designed for maximizing the dynamic excursion of the output voltage (output voltage swing), by reducing as much as possible voltage drops due to the series resistance of the active components (transistors) that form the output stage.
  • a widely used technique in power output stages is that of realizing a “bootstrap” line, using for this purpose a relatively large capacitance, that may be externally connected to the IC pins, in order to obtain the maximum peak-to-peak variation of the output voltage.
  • this technique conflicts with a general IC design trend of eliminating or reducing the need of passive external components to a minimum.
  • the known configurations of a power output stage are amply reported in literature and substantially are those employing a pair of transistors operating in phase opposition, namely an NPN/NPN, PNP/NPN, pMOS/nMOS and nMOS/nMOS pair.
  • NPN/NPN NPN/NPN
  • PNP/NPN PNP/NPN
  • pMOS/nMOS pMOS/nMOS
  • nMOS/nMOS pair nMOS/nMOS pair.
  • the selection of one of the above configurations depends on the fabrication technology that is employed, which determines also the maximum reverse voltage that can be withstood by the devices (for example the maximum VCE of bipolar junction transistors or the maximum VDS of MOS transistors).
  • Bipolar NPN transistors notably suffer from the problem connected to the so-called “secondary breakdown” phenomenon. Also bipolar PNP transistors are affected by this phenomenon but in a lesser measure than NPN transistors.
  • the power MOS transistors that can be realized in a compatible manner with the other type of integrated structures, have internal resistance characteristics that typically show the following values:
  • the solution of using a complementary pair of DMOS output transistors would appear an ideal choice, by considering also the advantage represented by the fact that the two output transistors would not need a driving current, being intrinsically voltage-controlled devices.
  • a p-channel DMOS transistor requires an integration area that may be four times the integration area of an n-channel, complementary DMOS transistor, for the same Ron. Therefore the solution that employs a complementary pair of DMOS transistors is adopted only in a limited number of applications, where the relatively large silicon area requirement is not a problem.
  • a so configured output stage is perfectly complementary and therefore does not reduce the output dynamics by a VGS (or by a VBE) and may be driven by a relatively simple stage.
  • the output stage has an intrinsically high voltage swing characteristic and does not need externally connected boostrap components.
  • the use of power transistors of different technology (a bipolar transistor of the high side or pull-up part and a field effect transistor for the low side or push-down part), permits to reach an outstandingly good compromise between the extent of silicon area necessary for integrating the two power transistors, by exploiting the relatively small size of an n-channel DMOS structure and of a vertical, isolated collector, PNP structure and the driving power requisite, which is required only by the active pull-up element constituted by the bipolar PNP transistor.
  • the pull-up power element constituted by a bipolar PNP transistor
  • a stage composed of a field effect transistor for example a p-channel MOS transistor, of sufficient size to provide the driving power required by the bipolar output transistor.
  • the PNP transistor may be constituted by a complex structure that comprises the PNP and NPN transistors, the electrical behavior of which can be equated to that of an equivalent PNP transistor.
  • This solution permits to further reduce the integration area, being the power NPN structure of the PNP equivalent complex structure capable of operating at a higher current density than a PNP structure and therefore requiring a reduced area of integration.
  • the output voltage swing would be reduced by a VBE but this could be advantageously traded-off with a maximized saving of silicon area.
  • FIG. 1 is a circuit diagram of an output stage of the invention
  • FIG. 2 is a circuit diagram of an output stage of the invention, according to an alternative embodiment thereof;
  • FIG. 3 is a more detailed circuit diagram of the output stage of FIG. 2 .
  • the output stage of the invention is essentially constituted by a pull-up power element PW H , composed of a bipolar PNP transistor, and by a push-down power element PW L , composed of a DMOS transistor.
  • the collector of PW H and the drain of PW L are connected in common to an output node OUT of the amplifier, which in this example is used to drive a loudspeaker.
  • the complementary pair of transistors of the output stage is customarily driven by a suitable driving stage.
  • the driving of the MOS transistor PW L occurs essentially in a voltage mode, with a practically null driving power
  • the driving of the high side element of the push-pull output stage, that is of the bipolar PNP transistor PW H requires a certain driving current (base current).
  • FIG. 2 An alternative embodiment of the output stage of the invention is shown in FIG. 2, wherein a MOS transistor M 1 is employed for driving the bipolar PNP transistor PW H , so as to avoid loading the relative output node of the driver stage.
  • FIG. 3 A circuit diagram of the driver stage is depicted in FIG. 3 .
  • the driver stage may be realized with field effect transistors in a substantially symmetrical form.
  • the high side part of the push-pull output stage that is the power transistor PW H (driven through the MOS M 1 ) is driven by the amplifier composed of R 3 , M 2 , M 3 and the current generator I 1 .
  • the low side part of the push-pull output stage, composed of the n-channel DMOS transistor PW L is driven by the amplifier composed of R 4 , M 4 , M 5 and the current generator I 2 .
  • the two resistances R 1 and R 2 connected between the IN-node and ground and between the IN-node and the load, respectively, determine the voltage gain.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

An output power stage which includes a PNP pull-up transistor and an n-channel FET push-down transistor, driven in phase opposition. This fully complementary stage provides an outstandingly improved power handling capability per semiconductor area occupied, together with a large output voltage swing, but does not require the use of externally connected discrete boot-strap components. The bipolar pull-up transistor can optionally be driven through an FET auxiliary stage, to minimize the power requirements of the preceding signal amplification stage.

Description

FIELD OF THE INVENTION
The present invention relates to an output stage for an integrated power amplifier particularly suited for audio amplifiers.
BACKGROUND OF THE INVENTION
The output stages of power amplifiers are normally designed for maximizing the dynamic excursion of the output voltage (output voltage swing), by reducing as much as possible voltage drops due to the series resistance of the active components (transistors) that form the output stage. There is an ample specific bibliography out of which the volume “Power Integrated Circuit”, published by Mc.Graw Hill, in 1986, pages 9.28-9.35 may be cited.
A widely used technique in power output stages is that of realizing a “bootstrap” line, using for this purpose a relatively large capacitance, that may be externally connected to the IC pins, in order to obtain the maximum peak-to-peak variation of the output voltage. Unfortunately, this technique conflicts with a general IC design trend of eliminating or reducing the need of passive external components to a minimum.
The known configurations of a power output stage are amply reported in literature and substantially are those employing a pair of transistors operating in phase opposition, namely an NPN/NPN, PNP/NPN, pMOS/nMOS and nMOS/nMOS pair. Of course, the selection of one of the above configurations depends on the fabrication technology that is employed, which determines also the maximum reverse voltage that can be withstood by the devices (for example the maximum VCE of bipolar junction transistors or the maximum VDS of MOS transistors).
Bipolar NPN transistors notably suffer from the problem connected to the so-called “secondary breakdown” phenomenon. Also bipolar PNP transistors are affected by this phenomenon but in a lesser measure than NPN transistors.
On the contrary, DMOS transistors are notably exempt from this problem.
In a mixed technology fabrication process (BJT, CMOS and DMOS) or BCD process, the power MOS transistors that can be realized in a compatible manner with the other type of integrated structures, have internal resistance characteristics that typically show the following values:
(n-channel) DMOS: Ron=0.5 Ω×mm2
(p-channel) DMOS: Ron=2.2 Ω×mm2
In particular, the solution of using a complementary pair of DMOS output transistors would appear an ideal choice, by considering also the advantage represented by the fact that the two output transistors would not need a driving current, being intrinsically voltage-controlled devices. However, a p-channel DMOS transistor requires an integration area that may be four times the integration area of an n-channel, complementary DMOS transistor, for the same Ron. Therefore the solution that employs a complementary pair of DMOS transistors is adopted only in a limited number of applications, where the relatively large silicon area requirement is not a problem.
On the other hand, the use of a (more compact) pair of transistors of the same polarity (that is noncomplementary), for example a pair of n-channel DMOS transistors, besides losing a portion equivalent to a VGS voltage of the maximum voltage swing of the output signal or otherwise requiring a bootstrap line, requires also a somewhat more complex driving circuit than the circuit that would be necessary for driving, in phase opposition, a complementary pair of output transistors.
There is a long felt need or utility of a complementary output stage with good breakdown characteristics that would not need externally connected bootstrap components and require a relatively large area of integration.
SUMMARY OF THE INVENTION
It has been found that in a normal BCD fabrication process it is possible to realize a bipolar PNP power transistor, having an internal resistance Ron of about 0.3 Ω×mm2, which can be satisfactorily used as the high side part of a complementary output power stage that employs as its low side part, an n-channel field effect transistor.
A so configured output stage is perfectly complementary and therefore does not reduce the output dynamics by a VGS (or by a VBE) and may be driven by a relatively simple stage.
The output stage has an intrinsically high voltage swing characteristic and does not need externally connected boostrap components. The use of power transistors of different technology (a bipolar transistor of the high side or pull-up part and a field effect transistor for the low side or push-down part), permits to reach an outstandingly good compromise between the extent of silicon area necessary for integrating the two power transistors, by exploiting the relatively small size of an n-channel DMOS structure and of a vertical, isolated collector, PNP structure and the driving power requisite, which is required only by the active pull-up element constituted by the bipolar PNP transistor.
According to an alternative embodiment of the output stage of the invention, the pull-up power element, constituted by a bipolar PNP transistor, is driven by a stage composed of a field effect transistor, for example a p-channel MOS transistor, of sufficient size to provide the driving power required by the bipolar output transistor.
According to an embodiment of the invention, the PNP transistor may be constituted by a complex structure that comprises the PNP and NPN transistors, the electrical behavior of which can be equated to that of an equivalent PNP transistor. This solution permits to further reduce the integration area, being the power NPN structure of the PNP equivalent complex structure capable of operating at a higher current density than a PNP structure and therefore requiring a reduced area of integration. Of course, in this latter case, the output voltage swing would be reduced by a VBE but this could be advantageously traded-off with a maximized saving of silicon area.
BRIEF DESCRIPTION OF THE DRAWINGS
The different aspects and advantages of the output stage of the invention will become more evident through the following description of several embodiments and by referring to the annexed drawing, wherein:
FIG. 1 is a circuit diagram of an output stage of the invention;
FIG. 2 is a circuit diagram of an output stage of the invention, according to an alternative embodiment thereof;
FIG. 3 is a more detailed circuit diagram of the output stage of FIG. 2.
DESCRIPTION OF PREFERRED EMBODIMENTS
With reference to FIG. 1, the output stage of the invention is essentially constituted by a pull-up power element PWH, composed of a bipolar PNP transistor, and by a push-down power element PWL, composed of a DMOS transistor. The collector of PWH and the drain of PWL are connected in common to an output node OUT of the amplifier, which in this example is used to drive a loudspeaker. The complementary pair of transistors of the output stage is customarily driven by a suitable driving stage.
Of course, while the driving of the MOS transistor PWL occurs essentially in a voltage mode, with a practically null driving power, the driving of the high side element of the push-pull output stage, that is of the bipolar PNP transistor PWH, requires a certain driving current (base current).
An alternative embodiment of the output stage of the invention is shown in FIG. 2, wherein a MOS transistor M1 is employed for driving the bipolar PNP transistor PWH, so as to avoid loading the relative output node of the driver stage.
A circuit diagram of the driver stage is depicted in FIG. 3. As may be observed, the driver stage may be realized with field effect transistors in a substantially symmetrical form. The high side part of the push-pull output stage, that is the power transistor PWH (driven through the MOS M1) is driven by the amplifier composed of R3, M2, M3 and the current generator I1. The low side part of the push-pull output stage, composed of the n-channel DMOS transistor PWL is driven by the amplifier composed of R4, M4, M5 and the current generator I2. In order to ensure compatibility to ground potential, the two resistances R1 and R2, connected between the IN-node and ground and between the IN-node and the load, respectively, determine the voltage gain.

Claims (14)

What is claimed is:
1. An integrated power audio output stage comprising:
a pair of transistors connected, in series with an output node, between a positive and a negative supply rail;
a driver stage connected to drive said transistors in phase opposition;
wherein said pair of transistors comprises a PNP bipolar pull-up transistor and an n-channel power field effect push-down transistor;
wherein said output node is connected to a loudspeaker;
wherein said driver stage is an analog differential amplifier.
2. The integrated power output stage of claim 1, wherein said PNP transistor is driven by a stage comprising a p-channel field effect MOS transistor.
3. The integrated power output stage of claim 1, wherein said PNP Transistor is an integrated, isolated collector, vertical transistor.
4. The integrated power output stage of claim 1, wherein said n-channel field effect transistor is a DMOS transistor.
5. The integrated power output stage of claim 1, further comprising an NMOS transistor connected to drive said PNP transistor.
6. An integrated circuit power audio output stage, comprising:
a PNP integrated power bipolar transistor having a base terminal, a collector terminal operatively connected to an output node, and an emitter terminal operatively connected to a first supply rail;
an N-channel power DMOS transistor having a gate terminal, a drain terminal operatively connected to said output node, and a source terminal operatively connected to a second supply rail which is more negative than said first supply rail;
said base terminal and said gate terminal being interconnected so that said bipolar transistor and said DMOS transistor are driven in phase opposition;
wherein said output node drives a loudspeaker.
7. The integrated power output stage of claim 6, further comprising a driver stage, integrated with said bipolar and DMOS transistors, which is connected to drive said base terminal of said bipolar transistor in phase opposition to said gate terminal of said DMOS transistor.
8. The integrated power output stage of claim 6, wherein said second supply rail has a voltage below ground voltage.
9. An integrated circuit power output audio stage, comprising:
a PNP integrated power bipolar transistor having a base terminal, a collector terminal operatively connected to an output node, and an emitter terminal operatively connected to a first supply rail;
an N-channel power DMOS transistor having a gate terminal, a drain terminal operatively connected to said output node, and a source terminal operatively connected to a second supply rail which is more negative than said first supply rail;
an additional field-effect transistor, connected to drive said base terminal of said power bipolar transistor; and
a driver circuit connected to drive said bipolar transistor and said DMOS transistor in phase opposition; said bipolar transistor being driven through said additional transistor;
wherein said output node drives a loudspeaker.
10. The integrated circuit of claim 9, wherein said additional field-effect transistor is connected, in series with a resistor, between said supply rails.
11. The integrated circuit of claim 9, wherein said additional field-effect transistor is a p-channel transistor.
12. The integrated circuit of claim 9, wherein said additional field-effect transistor is a p-channel transistor, and has a drain thereof connected directly to said second power supply connection.
13. The integrated circuit of claim 9, wherein said driver circuit is an analog differential amplifier.
14. The integrated circuit of claim 9, wherein said second supply rail has a voltage below ground voltage.
US08/351,578 1993-12-07 1994-12-07 Bipolar-plus-DMOS mixed-typology power output stage Expired - Lifetime US6222414B1 (en)

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EP1424771A1 (en) * 2002-11-28 2004-06-02 STMicroelectronics S.r.l. Cascode power amplifier particularly for use in radiofrequency applications
US9871029B2 (en) * 2016-05-06 2018-01-16 Analog Devices Global Bus driver / line driver

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