US6316302B1 - Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant - Google Patents
Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant Download PDFInfo
- Publication number
- US6316302B1 US6316302B1 US09/604,051 US60405100A US6316302B1 US 6316302 B1 US6316302 B1 US 6316302B1 US 60405100 A US60405100 A US 60405100A US 6316302 B1 US6316302 B1 US 6316302B1
- Authority
- US
- United States
- Prior art keywords
- sidewall spacers
- pair
- dopant
- type
- gate conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 125000006850 spacer group Chemical group 0.000 title claims abstract description 165
- 238000005530 etching Methods 0.000 title claims abstract description 15
- 239000007943 implant Substances 0.000 title abstract description 45
- 239000004020 conductor Substances 0.000 claims abstract description 97
- 230000000873 masking effect Effects 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 239000004065 semiconductor Substances 0.000 claims abstract description 24
- 239000002019 doping agent Substances 0.000 claims description 52
- 239000000463 material Substances 0.000 claims description 11
- 238000002955 isolation Methods 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 abstract description 7
- 238000012876 topography Methods 0.000 description 13
- 150000004767 nitrides Chemical class 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000012545 processing Methods 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000002679 ablation Methods 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Definitions
- This invention relates to integrated circuit fabrication and, more particularly, to isotropically etching sidewall spacers formed upon the opposed sidewall surfaces of a pair of CMOS (one NMOS and one PMOS) gate conductors to reduce the lateral thickness of each spacer.
- the sidewall spacers are isotropically etched after performing a source/drain implant self-aligned to the pair of sidewall spacers arranged upon the NMOS gate conductor so that they may also be used to perform an LDD implant self-aligned to the pair of sidewall spacers arranged upon the PMOS gate conductor.
- MOSFETs are manufactured by placing an undoped polycrystalline (“polysilicon”) material over a relatively thin gate oxide. The polysilicon material is then patterned to form a gate conductor directly above a channel region of the substrate. A dopant species is implanted into the gate conductor and regions of the substrate exclusive of the channel region, thereby forming source and drain regions (i.e., junctions) adjacent to and on opposite sides of the channel region. If the dopant species used for forming the source and drain regions is n-type, then the resulting MOSFET is an NMOSFET (“n-channel”) transistor device.
- polysilicon undoped polycrystalline
- the resulting MOSFET is a PMOSFET (“p-channel”) transistor device.
- CMOS complementary metal-oxide-semiconductor
- SCE short-channel effects
- the distance between a source-side junction and a drain-side junction is often referred to as the physical channel length.
- Leff effective channel length
- SCE becomes a predominant problem whenever Leff drops below approximately 0.2 ⁇ m.
- SCE impacts device operation by, inter alia, reducing device threshold voltages and increasing sub-threshold currents.
- Leff becomes quite small, the depletion regions associated with the source and drain areas within the junctions may extend toward one another and substantially occupy the channel area. Henceforth, some of the channel will be partially depleted without any influence of gate voltage. As a result, less gate charge is required to invert the channel of a transistor having a short Leff.
- Somewhat related to threshold voltage lowering is the concept of sub-threshold current flow. Even at times when the gate voltage is below the threshold value, current between the source and drain nonetheless exists for transistors having a relatively short Leff.
- One method in which to control SCE is to increase the dopant concentration within the body of the device. Unfortunately, increasing dopant within the body deleteriously increases potential gradients in the device.
- HCE hot carrier effects
- LDD lightly doped drain
- the purpose of the LDD is to absorb some of the potential into the drain and thus reduce Em.
- a conventional LDD structure is one in which a light concentration of dopant is self-aligned to the gate conductor followed by a heavier concentration of dopant self-aligned to the gate conductor on which a pair of sidewall spacers has been formed.
- the purpose of the first implant dose is to produce lightly doped sections within an active area of the substrate near the channel.
- the second implant dose is spaced from the channel by a distance substantially equivalent to the thickness of each sidewall spacer.
- the second implant dose forms heavily doped source and drain regions within the active area laterally outside the LDD areas. In this manner, the lateral thickness of each sidewall spacer dictates the length of each LDD area.
- P-type dopant species e.g., boron
- the p-type dopant species easily diffuse through interstitial and vacancy positions within the substrate to other sections of the substrate in response to being heated during subsequent processing steps.
- the source and drain regions may eventually extend completely to the gate conductor while the LDD areas may extend partially underneath the gate conductor.
- the lateral migration of dopant species into the channel region reduces the Leff of the transistor, and thus may lead to detrimental SCE and HCE.
- FIGS. 1-4 illustrate a conventional sequence of processing steps which may be used to form a CMOS circuit in which the LDD areas of a PMOS transistor are laterally offset from the sidewalls surfaces of a corresponding gate conductor.
- FIG. 1 depicts a partial cross-sectional view of a single crystalline silicon substrate 10 which is slightly doped with n-type dopant species. Shallow trench isolation structures 14 laterally isolate active areas 6 and 8 of substrate 10 .
- a p-type well 12 resides within an upper portion of active area 6 between a pair of isolation structures 14 .
- a pair of gate conductors 22 are spaced above separate active areas of substrate 10 by a gate dielectric 20 .
- sidewall spacers 24 a , 24 b , and 24 c may be formed laterally adjacent the opposed sidewall surfaces of each gate conductor 22 .
- Sidewall spacers 24 a and 24 c are typically composed of a dielectric, i.e., silicon dioxide, which is dissimilar to the dielectric, i.e., silicon nitride, from which sidewall spacers 24 b are made.
- each of the sidewall spacers 24 a , 24 b , and 24 c may be selectively etched without removing the adjacent spacer.
- a masking layer 26 may be formed upon active area 6 and the sidewall spacers and the gate conductor 22 residing above active area 6 .
- a p + source/drain implant self-aligned to the exposed lateral edges of sidewall spacers 24 a is forwarded into the unmasked areas of substrate 10 to from source and drain regions 28 .
- sidewall spacers 24 c are removed from sidewall spacers 24 b using an etch technique which is highly selective to silicon dioxide (“oxide”) relative to silicon nitride (“nitride”).
- Another masking layer 30 is formed upon active area 8 and the structures overlying the active area, as shown in FIG. 2 .
- an n + source/drain implant self-aligned to the exposed lateral edges of sidewall spacers 24 b is performed to form source and drain regions 32 within well 12 . Absent sidewall spacers 24 c , source and drain regions 32 are placed such that they are closer to the adjacent gate conductor 22 than are source and drain regions 28 .
- masking layer 30 is removed from active area 8 , and sidewall spacers 24 b are removed from sidewall spacers 24 a using an etch technique which exhibits a high etch selectivity ratio of nitride to oxide.
- a p ⁇ LDD implant is performed. In this manner, LDD areas 36 are formed within active area 8 laterally aligned to the exposed lateral edges of sidewall spacers 24 a , immediately adjacent to source and drain regions 28 .
- sidewall spacers 24 a and masking layer 34 may then be removed, followed by the formation of a masking layer 38 upon active area 8 and the overlying gate conductor 22 .
- An n ⁇ LDD implant which is self-aligned to the opposed sidewall surfaces of the unmasked gate conductor 22 is forwarded into well 12 to form LDD areas 40 .
- An NMOS transistor 42 and a PMOS transistor 44 are thusly placed upon and within substrate 10 .
- source and drain regions 28 and LDD areas 36 of PMOS transistor 46 may include high-diffusing dopant species, initially placing them a spaced distance from gate conductor 22 reduces the possibility that they might migrate laterally underneath the gate conductor.
- first and second pairs of sidewall spacers are concurrently formed upon the opposed sidewall surfaces of respective first and second gate conductors.
- the first and second gate conductors are spaced laterally apart upon isolated first and second active areas of a semiconductor substrate, respectively.
- a single set of sidewall spacer pairs are used as masking structures during the formation of source and drain regions of an NMOS transistor and LDD areas of a PMOS transistor.
- the n + source/drain (“S/D”) implant is self-aligned to the outer lateral edge of the first pair of sidewall spacers prior to reducing the lateral thicknesses of the sidewall spacers.
- the p ⁇ LDD implant is self-aligned to the outer lateral edge of the second pair of sidewall spacers after the spacer thicknesses have been reduced. Therefore, multiple pairs of sidewall spacers need not be formed laterally adjacent the sidewall surfaces of the gate conductors to vary the spacing between the implant regions and the gate conductors of the ensuing integrated circuit.
- an n ⁇ LDD implant which is self-aligned to the opposed sidewall surfaces of the first gate conductor is forwarded into the first active area.
- the LDD areas of the PMOS transistor are displaced from the corresponding gate conductor while the LDD areas of the NMOS transistor are positioned immediately adjacent the corresponding gate conductor.
- third and fourth pairs of sidewall spacers are formed laterally extending from the first and second pairs of sidewall spacers, respectively.
- a p + S/D implant is then self-aligned to the exposed lateral edges of the fourth pair of sidewall spacers, thereby forming source and drain regions within the second active area.
- the combined lateral thickness of adjacent first and third spacers is substantially greater than the original lateral thickness of each individual third spacer. Accordingly, the source and drain regions of the PMOS transistor are laterally spaced from the second gate conductor by a distance that is substantially greater than the distance by which the source and drain regions of the NMOS transistor are spaced from the first gate conductor.
- CMOS transistor in which the PMOS junctions are displaced from their corresponding gate conductor by a greater distance than the NMOS junctions are displaced from their corresponding gate conductor.
- only two pairs of sidewall spacers are formed upon the sidewall surfaces of each gate conductor.
- the deposition time and anisotropic etch time required to form a third spacer is eliminated.
- a semiconductor substrate which includes a first active area laterally isolated from a second active area by an isolation structure.
- a first gate conductor and a second gate conductor have been patterned laterally spaced apart upon respective first and second active areas.
- the first and second gate conductors are spaced above the substrate by a gate dielectric and are laterally bounded by respective first and second opposed sidewall surfaces.
- a first masking layer is formed upon the second active area and the second gate conductor, followed by forwarding an n ⁇ LDD implant self-aligned to the first opposed sidewall surfaces into the first active area.
- the first masking layer is removed, and the first and second pairs of sidewall spacers are then formed laterally extending from the respective first and second opposed sidewall surfaces.
- the sidewall spacers comprise a dielectric, e.g., oxide or nitride.
- a second masking layer is then patterned upon the second active area, the second pair of sidewall spacers, and the second gate conductor.
- an n + S/D implant of n-type dopants e.g., arsenic
- the n + S/D implant is performed at a higher dose and energy than the n ⁇ LDD implant so that the resulting first source and drain regions contain a higher dopant concentration than the resulting first LDD areas.
- An NMOS transistor is thus formed upon and within the first active area.
- the first and second pairs of sidewall spacers are isotropically etched using, e.g., a plasma etch chemistry which readily removes the spacer material. In this manner, the lateral thickness of each sidewall spacer is reduced. Thereafter, a third masking layer is formed upon the first active area, the first pair of sidewall spacers, and the first gate conductor. A p ⁇ implant is then performed to incorporate p-type dopants, e.g., boron, into regions of the second active area spaced from the second gate conductor by the second pair of sidewall spacers having the reduced thicknesses.
- p-type dopants e.g., boron
- the third masking layer is removed so that third and fourth pairs of sidewall spacers may be formed upon the first and second pairs of sidewall spacers, respectively.
- the third pair of sidewall spacers extend laterally from first outer edges that laterally bound the first pair of sidewall spacers to third outer edges that laterally bound the third pair of sidewall spacers.
- the fourth pair of sidewall spacers extend laterally from second outer edges that laterally bound the second pair of sidewall spacers to fourth outer edges that laterally bound the fourth pair of sidewall spacers.
- a p + implant performed at a higher dose and energy than the p ⁇ implant is forwarded into second source and drain regions of the second active area.
- the second source and drain regions are laterally spaced from the second gate conductor by the second and fourth pairs of sidewall spacers.
- the second LDD areas of the resulting PMOS transistor are arranged within the second active area, approximately aligned between the second and fourth outer edges of the second and fourth pairs of sidewall spacers, respectively.
- the second source and drain regions are positioned within the second active area immediately adjacent to the second LDD areas.
- the first LDD areas of the NMOS transistor reside within the first active area, approximately aligned to the first opposed sidewall surfaces of the first gate conductor.
- the outer lateral edges of the first LDD areas are interposed between, and laterally displaced from, the first and third outer edges of the first and third pairs of sidewall spacers, respectively.
- the first source and drain regions are arranged within the first active area beside the first LDD areas.
- FIGS. 1-4 depict a cross-sectional view of a sequence of conventional processing steps used to form a CMOS integrated circuit, wherein three pairs of sidewall spacers are employed to form graded junctions of transistor devices;
- FIG. 5 depicts a partial cross-sectional view of a semiconductor topography in which first and second gate conductors are arranged upon respective first and second active areas of a semiconductor substrate, wherein a first masking layer is formed upon the second active area and the second gate conductor;
- FIG. 6 depicts a partial cross-sectional view of the semiconductor topography, wherein an n ⁇ LDD implant forwarded into the first active area is self-aligned to the first opposed sidewall surfaces of the first gate conductor, subsequent to the step in FIG. 5;
- FIG. 7 depicts a partial cross-sectional view of the semiconductor topography, wherein first and second pairs of sidewall spacers are formed upon respective first and second opposed sidewall surfaces which bound the first and second gate conductors, respectively, subsequent to the step in FIG. 6;
- FIG. 8 depicts a partial cross-sectional view of the semiconductor topography, wherein a second masking layer is formed upon the second active area, and an n + implant forwarded into the first active area is self-aligned to the exposed lateral edges of the first pair of spacers, subsequent to the step in FIG. 7;
- FIG. 9 depicts a partial cross-sectional view of the semiconductor topography, wherein the first and second pairs of sidewall spacers are isotropically etched to reduce the lateral thickness of each spacer after removing the second masking layer from the second active area, subsequent to the step in FIG. 8;
- FIG. 10 depicts a partial cross-sectional view of the semiconductor topography, wherein a third masking layer is formed upon the first active area, and wherein a p ⁇ LDD implant forwarded into the second active area is self-aligned to the exposed lateral edges of the second pair of sidewall spacers, subsequent to the step in FIG. 9;
- FIG. 11 depicts a partial cross-sectional view of the semiconductor topography, wherein third and fourth pairs of sidewall spacers are formed laterally extending from respective first and second sidewall spacers, subsequent to the step in FIG. 10;
- FIG. 12 depicts a partial cross-sectional view of a semiconductor topography, wherein a fourth masking layer is formed upon the first active area, and wherein a p + LDD implant forwarded into the second active area is self-aligned to the exposed lateral edges of the fourth pair of sidewall spacers, subsequent to the step in FIG. 11; and
- FIG. 13 depicts a partial cross-sectional view of a semiconductor topography, wherein the fourth masking layer is removed from the first active area to complete the formation of NMOS and PMOS transistors, subsequent to the step in FIG. 12 .
- Substrate 50 preferably comprises single crystalline silicon which has been slightly doped with n-type impurities.
- Substrate 50 includes first and second active areas 46 and 48 which are isolated from each other and from other active areas within substrate 50 by well-known shallow trench isolation structures 54 .
- trench isolation structures 50 may be replaced with well-known LOCOS structures.
- a p-type well 52 has been formed within an upper portion of first active area 46 using ion implantation of p-type species therein.
- bulk substrate 50 may be slightly doped with p-type impurities, and an n-type well may be arranged within active area 48 .
- a pair of gate conductors 58 a and 58 b have been patterned a lateral spaced distance apart upon first and second active areas 46 and 48 , respectively.
- Gate conductors 58 a and 58 b may comprise, e.g., polysilicon which has been chemically-vapor deposited from a silane source.
- a gate dielectric 56 comprising, e.g., oxide, is interposed between substrate 50 and each gate conductor.
- a masking layer 60 is patterned across active area 48 and gate conductor 58 b which leaves well 52 and gate conductor 58 a uncovered.
- Masking layer 60 may comprise, e.g., photoresist which is patterned using optical lithography.
- an n ⁇ LDD implant is forwarded into areas 62 of p-type well 52 which are not masked by gate conductor 58 a .
- Appropriate n-type dopant species for the LDD implant include arsenic and phosphorus.
- FIG. 7 illustrates the formation of first and second pairs of sidewall spacers 66 a and 66 b laterally extending from the opposed sidewall surfaces of respective first and second gate conductors 58 a and 58 b .
- Masking layer 60 is stripped from active area 48 prior to spacer formation.
- Sidewall spacers 66 a and 66 b may be formed by first depositing a spacer material, e.g., oxide or nitride, across the semiconductor topography, as indicated by dotted line 64 . Thereafter, the spacer material is anisotropically etched such that ion ablation of horizontally oriented surfaces occurs at a faster rate than ion ablation of vertically oriented surfaces. The etch preferably terminates before substantial portions of substrate 50 and gate conductor 58 can be removed. Using the anisotropic etch allows the spacer material to be retained upon the sidewall surfaces of gate conductors 58 a and 58 b in the form of sidewall spacers 66 a and 66 b.
- a spacer material e.g., oxide or nitride
- a masking layer 68 comprising, e.g., photoresist, is then patterned upon active area 48 of substrate 50 , sidewall spacers 66 b , and gate conductor 58 b . Thereafter, an n + S/D implant of n-type dopant species are forwarded into source and drain regions 70 of well 52 which are displaced from gate conductor 58 a by a distance substantially equivalent to the lateral thickness of each sidewall spacer 66 a . The n + S/D implant is performed at a higher dose and energy than is the n ⁇ LDD implant.
- Source and drain regions 70 dominate a substantial portion of the previously implanted areas 62 such that LDD areas 62 become primarily positioned beneath sidewall spacers 66 a .
- masking layer 68 is removed, and sidewall spacers 66 a and 66 b are concurrently isotropically etched to reduce their lateral thicknesses.
- a plasma etch technique which exhibits a high selectivity to the spacer material relative to silicon may, for example, be used.
- a masking layer 72 comprising, e.g., photoresist, is then patterned upon active area 46 , gate conductor 58 a , and sidewall spacers 66 a .
- a p ⁇ LDD implant is forwarded into areas 74 of active area which are laterally spaced from gate conductor 58 b by a distance substantially equivalent to the reduced lateral thickness of each sidewall spacers 66 b .
- Appropriate p-type dopant species from the implant include boron and boron difluoride.
- third and fourth pairs of sidewall spacers 78 a and 78 b are formed laterally extending from respective first and second pairs of sidewall spacers 66 a and 66 b .
- Formation of sidewall spacers 78 a and 78 b involves depositing a spacer material, e.g., oxide or nitride, across the topography, as represented by dotted line 76 , followed by anisotropically etching the spacer material. Thereafter, as shown in FIG.
- a spacer material e.g., oxide or nitride
- a masking layer 79 comprising, e.g., photoresist is patterned upon active area 46 , gate conductor 58 a , and sidewall spacers 66 a and 66 b .
- a p + S/D implant is then performed to incorporate a relatively high concentration of p-type dopant species into source and drain regions 80 of active area 48 which are displaced from gate conductor 58 b by a distance substantially equivalent to the combined lateral thicknesses of spacers 66 b and 78 b .
- the p + S/D implant is performed at a higher dose and energy than the p ⁇ LDD implant
- FIG. 13 depicts the semiconductor topography after masking layer 79 has been removed from active area 46 .
- An NMOS transistor 82 and a PMOS transistor 84 result from the sequence of steps shown in FIGS. 5-13.
- An ensuing CMOS integrated circuit employing NMOS transistor 82 and PMOS transistor 84 may be formed using well-known semiconductor fabrication
- this invention is believed to provide a method for isotropically etching pairs of sidewall spacers to reduce the lateral thickness of each sidewall spacer.
- the pre-etch thickness of the sidewall spacers may be used as masking structures for a S/D implant of an NMOS transistor while the post-etch thickness of the spacers may be used as masking structures for an LDD implant of a PMOS transistor.
Abstract
A method is provided for isotropically etching pairs of sidewall spacers to reduce the lateral thickness of each sidewall spacer. In an embodiment, first and second pairs of sidewall spacers are concurrently formed upon the opposed sidewall surfaces of respective first and second gate conductors. The first and second gate conductors are spaced laterally apart upon isolated first and second active areas of a semiconductor substrate, respectively. Advantageously, a single set of sidewall spacer pairs are used as masking structures during the formation of source and drain regions of an NMOS transistor and LDD areas of a PMOS transistor. That is, the n+ source/drain (“S/D”) implant is self-aligned to the outer lateral edge of the first pair of sidewall spacers prior to reducing the lateral thicknesses of the sidewall spacers. However, the p− LDD implant is self-aligned to the outer lateral edge of the second pair of sidewall spacers after the spacer thicknesses have been reduced. Therefore, multiple pairs of sidewall spacers need not be formed laterally adjacent the sidewall surfaces of the gate conductors to vary the spacing between the implant regions and the gate conductors of the ensuing integrated circuit.
Description
This application is a divisional of U.S. Ser. No. 09/105,872 filed Jun. 26, 1998 now U.S. Pat. No. 6,124,610.
1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to isotropically etching sidewall spacers formed upon the opposed sidewall surfaces of a pair of CMOS (one NMOS and one PMOS) gate conductors to reduce the lateral thickness of each spacer. The sidewall spacers are isotropically etched after performing a source/drain implant self-aligned to the pair of sidewall spacers arranged upon the NMOS gate conductor so that they may also be used to perform an LDD implant self-aligned to the pair of sidewall spacers arranged upon the PMOS gate conductor.
2. Description of the Related Art
Fabrication of a MOSFET device is well known. Generally speaking, MOSFETs are manufactured by placing an undoped polycrystalline (“polysilicon”) material over a relatively thin gate oxide. The polysilicon material is then patterned to form a gate conductor directly above a channel region of the substrate. A dopant species is implanted into the gate conductor and regions of the substrate exclusive of the channel region, thereby forming source and drain regions (i.e., junctions) adjacent to and on opposite sides of the channel region. If the dopant species used for forming the source and drain regions is n-type, then the resulting MOSFET is an NMOSFET (“n-channel”) transistor device. Conversely, if the dopant species is p-type, then the resulting MOSFET is a PMOSFET (“p-channel”) transistor device. Integrated circuits utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both (CMOS) on a single substrate. While both types of devices can be formed, the devices are distinguishable based on the dopant species used.
As device dimensions continue to shrink, transistor devices become more sensitive to so-called short-channel effects (“SCE”). The distance between a source-side junction and a drain-side junction is often referred to as the physical channel length. However, after implantation and subsequent diffusion of the junctions, the actual distance between junctions becomes less than the physical channel length and is often referred to as the effective channel length (“Leff”). In VLSI designs, as the physical channel becomes small, so too must the Leff. SCE becomes a predominant problem whenever Leff drops below approximately 0.2 μm.
Generally speaking, SCE impacts device operation by, inter alia, reducing device threshold voltages and increasing sub-threshold currents. As Leff becomes quite small, the depletion regions associated with the source and drain areas within the junctions may extend toward one another and substantially occupy the channel area. Henceforth, some of the channel will be partially depleted without any influence of gate voltage. As a result, less gate charge is required to invert the channel of a transistor having a short Leff. Somewhat related to threshold voltage lowering is the concept of sub-threshold current flow. Even at times when the gate voltage is below the threshold value, current between the source and drain nonetheless exists for transistors having a relatively short Leff. One method in which to control SCE is to increase the dopant concentration within the body of the device. Unfortunately, increasing dopant within the body deleteriously increases potential gradients in the device.
In addition to promoting SCE, reducing device dimensions may cause the lateral electric field in MOS devices to increase, giving rise to so-called hot carrier effects (“HCE”). HCE is a phenomena in which the kinetic energy of charged carriers (holes or electrons) within the channel region of a device is increased as the carriers are accelerated through large potential gradients. As a result of this increase in kinetic energy, the charged carriers are injected into the gate oxide wherein they may become trapped. The greatest potential gradient, often referred to as the maximum electric field (“Em”) occurs near the drain during saturated operation. As a result of electron entrapment within the gate oxide, a net negative charge density forms in the gate oxide. The trapped charge can accumulate with time, resulting in a positive threshold shift in an NMOS transistor, or a negative threshold shift in a PMOS transistor.
To overcome the problems related to SCE and HCE, an alternative drain structure known as the lightly doped drain (“LDD”) is commonly used. The purpose of the LDD is to absorb some of the potential into the drain and thus reduce Em. A conventional LDD structure is one in which a light concentration of dopant is self-aligned to the gate conductor followed by a heavier concentration of dopant self-aligned to the gate conductor on which a pair of sidewall spacers has been formed. The purpose of the first implant dose is to produce lightly doped sections within an active area of the substrate near the channel. The second implant dose is spaced from the channel by a distance substantially equivalent to the thickness of each sidewall spacer. The second implant dose forms heavily doped source and drain regions within the active area laterally outside the LDD areas. In this manner, the lateral thickness of each sidewall spacer dictates the length of each LDD area.
Unfortunately, lateral migration of dopant species within both the source and drain regions and the LDD areas of a PMOS transistor can offset the benefits of having those LDD areas. P-type dopant species, e.g., boron, are typically relatively small in size. As such, the p-type dopant species easily diffuse through interstitial and vacancy positions within the substrate to other sections of the substrate in response to being heated during subsequent processing steps. As a result of dopant diffusion, the source and drain regions may eventually extend completely to the gate conductor while the LDD areas may extend partially underneath the gate conductor. The lateral migration of dopant species into the channel region reduces the Leff of the transistor, and thus may lead to detrimental SCE and HCE. Thus, it may be of benefit to unconventionally displace the PMOS LDD areas away from the gate conductor to provide protection against SCE and HCE.
FIGS. 1-4 illustrate a conventional sequence of processing steps which may be used to form a CMOS circuit in which the LDD areas of a PMOS transistor are laterally offset from the sidewalls surfaces of a corresponding gate conductor. FIG. 1 depicts a partial cross-sectional view of a single crystalline silicon substrate 10 which is slightly doped with n-type dopant species. Shallow trench isolation structures 14 laterally isolate active areas 6 and 8 of substrate 10. A p-type well 12 resides within an upper portion of active area 6 between a pair of isolation structures 14. A pair of gate conductors 22 are spaced above separate active areas of substrate 10 by a gate dielectric 20. For example, three pairs of sidewall spacers 24 a, 24 b, and 24 c may be formed laterally adjacent the opposed sidewall surfaces of each gate conductor 22. Sidewall spacers 24 a and 24 c are typically composed of a dielectric, i.e., silicon dioxide, which is dissimilar to the dielectric, i.e., silicon nitride, from which sidewall spacers 24 b are made. As such, each of the sidewall spacers 24 a, 24 b, and 24 c may be selectively etched without removing the adjacent spacer. As shown in FIG. 1, a masking layer 26 may be formed upon active area 6 and the sidewall spacers and the gate conductor 22 residing above active area 6. Subsequent to forming masking layer 26, a p+ source/drain implant self-aligned to the exposed lateral edges of sidewall spacers 24 a is forwarded into the unmasked areas of substrate 10 to from source and drain regions 28.
After removing masking layer 26, sidewall spacers 24 c are removed from sidewall spacers 24 b using an etch technique which is highly selective to silicon dioxide (“oxide”) relative to silicon nitride (“nitride”). Another masking layer 30 is formed upon active area 8 and the structures overlying the active area, as shown in FIG. 2. Thereafter, an n+ source/drain implant self-aligned to the exposed lateral edges of sidewall spacers 24 b is performed to form source and drain regions 32 within well 12. Absent sidewall spacers 24 c, source and drain regions 32 are placed such that they are closer to the adjacent gate conductor 22 than are source and drain regions 28. Subsequently, masking layer 30 is removed from active area 8, and sidewall spacers 24 b are removed from sidewall spacers 24 a using an etch technique which exhibits a high etch selectivity ratio of nitride to oxide. After forming a masking layer 34 upon active area 6 and the structures overlying active area 6, a p− LDD implant is performed. In this manner, LDD areas 36 are formed within active area 8 laterally aligned to the exposed lateral edges of sidewall spacers 24 a, immediately adjacent to source and drain regions 28.
As shown in FIG. 4, sidewall spacers 24 a and masking layer 34 may then be removed, followed by the formation of a masking layer 38 upon active area 8 and the overlying gate conductor 22. An n− LDD implant which is self-aligned to the opposed sidewall surfaces of the unmasked gate conductor 22 is forwarded into well 12 to form LDD areas 40. An NMOS transistor 42 and a PMOS transistor 44 are thusly placed upon and within substrate 10. Although source and drain regions 28 and LDD areas 36 of PMOS transistor 46 may include high-diffusing dopant species, initially placing them a spaced distance from gate conductor 22 reduces the possibility that they might migrate laterally underneath the gate conductor.
The process of forming three pairs of sidewall spacers laterally adjacent each gate conductor, sequentially removing each pair of spacers, and masking certain active areas while implanting dopants into other active areas is unfortunately very time consuming. First of all, since sidewall spacers 24 a and 24 c are composed of oxide while sidewall spacer 24 b is composed of nitride, a separate deposition and anisotropic etch step is required for each spacer. Further, each time an implantation step is performed, one mask is removed from certain active areas while another mask is formed across other active areas. Also, since a different pair of spacers is selectively etched before each implantation step, time must be allotted for the preparation of each etch process and each implantation process. It would therefore be desirable to reduce the number of processing steps, and hence the amount of time required to form a CMOS circuit in which the junctions of the PMOS transistors are laterally spaced from adjacent gate conductors while those of the NMOS transistors are positioned immediately adjacent the gate conductors.
The problems outlined above are in large part solved by the technique hereof for isotropically etching pairs of sidewall spacers to reduce the lateral thickness of each sidewall spacer. In an embodiment, first and second pairs of sidewall spacers are concurrently formed upon the opposed sidewall surfaces of respective first and second gate conductors. The first and second gate conductors are spaced laterally apart upon isolated first and second active areas of a semiconductor substrate, respectively. Advantageously, a single set of sidewall spacer pairs are used as masking structures during the formation of source and drain regions of an NMOS transistor and LDD areas of a PMOS transistor. That is, the n+ source/drain (“S/D”) implant is self-aligned to the outer lateral edge of the first pair of sidewall spacers prior to reducing the lateral thicknesses of the sidewall spacers. However, the p− LDD implant is self-aligned to the outer lateral edge of the second pair of sidewall spacers after the spacer thicknesses have been reduced. Therefore, multiple pairs of sidewall spacers need not be formed laterally adjacent the sidewall surfaces of the gate conductors to vary the spacing between the implant regions and the gate conductors of the ensuing integrated circuit.
Prior to fabricating the sidewall spacers, an n− LDD implant which is self-aligned to the opposed sidewall surfaces of the first gate conductor is forwarded into the first active area. As such, the LDD areas of the PMOS transistor are displaced from the corresponding gate conductor while the LDD areas of the NMOS transistor are positioned immediately adjacent the corresponding gate conductor. Subsequent to performing the p− LDD implant, third and fourth pairs of sidewall spacers are formed laterally extending from the first and second pairs of sidewall spacers, respectively. A p+ S/D implant is then self-aligned to the exposed lateral edges of the fourth pair of sidewall spacers, thereby forming source and drain regions within the second active area. The combined lateral thickness of adjacent first and third spacers is substantially greater than the original lateral thickness of each individual third spacer. Accordingly, the source and drain regions of the PMOS transistor are laterally spaced from the second gate conductor by a distance that is substantially greater than the distance by which the source and drain regions of the NMOS transistor are spaced from the first gate conductor.
Removing the graded junctions (i.e., source and drain regions and LDD areas) of the PMOS transistor away from the second gate conductor gives the dopant species some leeway between the junctions and the channel region of the substrate beneath the gate conductor. Absent the additional spacing between the PMOS junctions and the second gate conductor, the relatively fast-diffusing p-type dopant species, e.g., boron, could inadvertently migrate into the channel region, and thus reduce the Leff of the PMOS transistor. As such, displacing the PMOS junctions from the second gate conductor lowers the risk of SCE and HCE. Advantageously, fewer steps are required to form the CMOS transistor in which the PMOS junctions are displaced from their corresponding gate conductor by a greater distance than the NMOS junctions are displaced from their corresponding gate conductor. In particular, only two pairs of sidewall spacers are formed upon the sidewall surfaces of each gate conductor. As such, the deposition time and anisotropic etch time required to form a third spacer is eliminated. Also, it is not necessary to remove one spacer from another spacer to achieve the desired junction configuration. Accordingly, less time is required to fabricate the transistor devices which are substantially resistant to HCE and SCE. Therefore, the overall throughput of the integrated circuit manufacturer is increased by reducing the lateral thicknesses of a single set of sidewall spacer pairs so that they may be used for both an n+ S/D implant and a p− LDD implant.
According to an embodiment, a semiconductor substrate is provided which includes a first active area laterally isolated from a second active area by an isolation structure. A first gate conductor and a second gate conductor have been patterned laterally spaced apart upon respective first and second active areas. The first and second gate conductors are spaced above the substrate by a gate dielectric and are laterally bounded by respective first and second opposed sidewall surfaces. A first masking layer is formed upon the second active area and the second gate conductor, followed by forwarding an n− LDD implant self-aligned to the first opposed sidewall surfaces into the first active area. The first masking layer is removed, and the first and second pairs of sidewall spacers are then formed laterally extending from the respective first and second opposed sidewall surfaces. Preferably the sidewall spacers comprise a dielectric, e.g., oxide or nitride. A second masking layer is then patterned upon the second active area, the second pair of sidewall spacers, and the second gate conductor. Subsequently, an n+ S/D implant of n-type dopants, e.g., arsenic, is forwarded into first source and drain regions of the first active area which are spaced from the first gate conductor by the first pair of sidewall spacers. The n+ S/D implant is performed at a higher dose and energy than the n− LDD implant so that the resulting first source and drain regions contain a higher dopant concentration than the resulting first LDD areas. An NMOS transistor is thus formed upon and within the first active area.
After removing the second masking layer from the semiconductor topography, the first and second pairs of sidewall spacers are isotropically etched using, e.g., a plasma etch chemistry which readily removes the spacer material. In this manner, the lateral thickness of each sidewall spacer is reduced. Thereafter, a third masking layer is formed upon the first active area, the first pair of sidewall spacers, and the first gate conductor. A p− implant is then performed to incorporate p-type dopants, e.g., boron, into regions of the second active area spaced from the second gate conductor by the second pair of sidewall spacers having the reduced thicknesses. The third masking layer is removed so that third and fourth pairs of sidewall spacers may be formed upon the first and second pairs of sidewall spacers, respectively. As such, the third pair of sidewall spacers extend laterally from first outer edges that laterally bound the first pair of sidewall spacers to third outer edges that laterally bound the third pair of sidewall spacers. Also, the fourth pair of sidewall spacers extend laterally from second outer edges that laterally bound the second pair of sidewall spacers to fourth outer edges that laterally bound the fourth pair of sidewall spacers.
After patterning a masking layer upon the first active area, the first and third pairs of sidewall spacers, and the first gate conductor, a p+ implant performed at a higher dose and energy than the p− implant is forwarded into second source and drain regions of the second active area. The second source and drain regions are laterally spaced from the second gate conductor by the second and fourth pairs of sidewall spacers. The second LDD areas of the resulting PMOS transistor are arranged within the second active area, approximately aligned between the second and fourth outer edges of the second and fourth pairs of sidewall spacers, respectively. The second source and drain regions are positioned within the second active area immediately adjacent to the second LDD areas. On the other hand, the first LDD areas of the NMOS transistor reside within the first active area, approximately aligned to the first opposed sidewall surfaces of the first gate conductor. The outer lateral edges of the first LDD areas are interposed between, and laterally displaced from, the first and third outer edges of the first and third pairs of sidewall spacers, respectively. The first source and drain regions are arranged within the first active area beside the first LDD areas.
Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which:
FIGS. 1-4 depict a cross-sectional view of a sequence of conventional processing steps used to form a CMOS integrated circuit, wherein three pairs of sidewall spacers are employed to form graded junctions of transistor devices;
FIG. 5 depicts a partial cross-sectional view of a semiconductor topography in which first and second gate conductors are arranged upon respective first and second active areas of a semiconductor substrate, wherein a first masking layer is formed upon the second active area and the second gate conductor;
FIG. 6 depicts a partial cross-sectional view of the semiconductor topography, wherein an n− LDD implant forwarded into the first active area is self-aligned to the first opposed sidewall surfaces of the first gate conductor, subsequent to the step in FIG. 5;
FIG. 7 depicts a partial cross-sectional view of the semiconductor topography, wherein first and second pairs of sidewall spacers are formed upon respective first and second opposed sidewall surfaces which bound the first and second gate conductors, respectively, subsequent to the step in FIG. 6;
FIG. 8 depicts a partial cross-sectional view of the semiconductor topography, wherein a second masking layer is formed upon the second active area, and an n+ implant forwarded into the first active area is self-aligned to the exposed lateral edges of the first pair of spacers, subsequent to the step in FIG. 7;
FIG. 9 depicts a partial cross-sectional view of the semiconductor topography, wherein the first and second pairs of sidewall spacers are isotropically etched to reduce the lateral thickness of each spacer after removing the second masking layer from the second active area, subsequent to the step in FIG. 8;
FIG. 10 depicts a partial cross-sectional view of the semiconductor topography, wherein a third masking layer is formed upon the first active area, and wherein a p− LDD implant forwarded into the second active area is self-aligned to the exposed lateral edges of the second pair of sidewall spacers, subsequent to the step in FIG. 9;
FIG. 11 depicts a partial cross-sectional view of the semiconductor topography, wherein third and fourth pairs of sidewall spacers are formed laterally extending from respective first and second sidewall spacers, subsequent to the step in FIG. 10;
FIG. 12 depicts a partial cross-sectional view of a semiconductor topography, wherein a fourth masking layer is formed upon the first active area, and wherein a p+ LDD implant forwarded into the second active area is self-aligned to the exposed lateral edges of the fourth pair of sidewall spacers, subsequent to the step in FIG. 11; and
FIG. 13 depicts a partial cross-sectional view of a semiconductor topography, wherein the fourth masking layer is removed from the first active area to complete the formation of NMOS and PMOS transistors, subsequent to the step in FIG. 12.
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.
Turning now to FIG. 5, a partial cross-sectional view of a semiconductor substrate 50 is depicted. Substrate 50 preferably comprises single crystalline silicon which has been slightly doped with n-type impurities. Substrate 50 includes first and second active areas 46 and 48 which are isolated from each other and from other active areas within substrate 50 by well-known shallow trench isolation structures 54. Alternatively, trench isolation structures 50 may be replaced with well-known LOCOS structures. A p-type well 52 has been formed within an upper portion of first active area 46 using ion implantation of p-type species therein. In an alternate embodiment, bulk substrate 50 may be slightly doped with p-type impurities, and an n-type well may be arranged within active area 48. A pair of gate conductors 58 a and 58 b have been patterned a lateral spaced distance apart upon first and second active areas 46 and 48, respectively. Gate conductors 58 a and 58 b may comprise, e.g., polysilicon which has been chemically-vapor deposited from a silane source. A gate dielectric 56 comprising, e.g., oxide, is interposed between substrate 50 and each gate conductor. As shown in FIG. 5, a masking layer 60 is patterned across active area 48 and gate conductor 58 b which leaves well 52 and gate conductor 58 a uncovered. Masking layer 60 may comprise, e.g., photoresist which is patterned using optical lithography.
Subsequent to forming masking layer 60, an n− LDD implant is forwarded into areas 62 of p-type well 52 which are not masked by gate conductor 58 a. Appropriate n-type dopant species for the LDD implant include arsenic and phosphorus. FIG. 7 illustrates the formation of first and second pairs of sidewall spacers 66 a and 66 b laterally extending from the opposed sidewall surfaces of respective first and second gate conductors 58 a and 58 b. Masking layer 60 is stripped from active area 48 prior to spacer formation. Sidewall spacers 66 a and 66 b may be formed by first depositing a spacer material, e.g., oxide or nitride, across the semiconductor topography, as indicated by dotted line 64. Thereafter, the spacer material is anisotropically etched such that ion ablation of horizontally oriented surfaces occurs at a faster rate than ion ablation of vertically oriented surfaces. The etch preferably terminates before substantial portions of substrate 50 and gate conductor 58 can be removed. Using the anisotropic etch allows the spacer material to be retained upon the sidewall surfaces of gate conductors 58 a and 58 b in the form of sidewall spacers 66 a and 66 b.
Turning to FIG. 8, a masking layer 68 comprising, e.g., photoresist, is then patterned upon active area 48 of substrate 50, sidewall spacers 66 b, and gate conductor 58 b. Thereafter, an n+ S/D implant of n-type dopant species are forwarded into source and drain regions 70 of well 52 which are displaced from gate conductor 58 a by a distance substantially equivalent to the lateral thickness of each sidewall spacer 66 a. The n+ S/D implant is performed at a higher dose and energy than is the n− LDD implant. Source and drain regions 70 dominate a substantial portion of the previously implanted areas 62 such that LDD areas 62 become primarily positioned beneath sidewall spacers 66 a. Subsequently, as depicted in FIG. 9, masking layer 68 is removed, and sidewall spacers 66 a and 66 b are concurrently isotropically etched to reduce their lateral thicknesses. A plasma etch technique which exhibits a high selectivity to the spacer material relative to silicon may, for example, be used. As shown in FIG. 10, a masking layer 72 comprising, e.g., photoresist, is then patterned upon active area 46, gate conductor 58 a, and sidewall spacers 66 a. A p− LDD implant is forwarded into areas 74 of active area which are laterally spaced from gate conductor 58 b by a distance substantially equivalent to the reduced lateral thickness of each sidewall spacers 66 b. Appropriate p-type dopant species from the implant include boron and boron difluoride.
Turning to FIG. 11, masking layer 72 is removed and third and fourth pairs of sidewall spacers 78 a and 78 b are formed laterally extending from respective first and second pairs of sidewall spacers 66 a and 66 b. Formation of sidewall spacers 78 a and 78 b involves depositing a spacer material, e.g., oxide or nitride, across the topography, as represented by dotted line 76, followed by anisotropically etching the spacer material. Thereafter, as shown in FIG. 12, a masking layer 79 comprising, e.g., photoresist is patterned upon active area 46, gate conductor 58 a, and sidewall spacers 66 a and 66 b. A p+ S/D implant is then performed to incorporate a relatively high concentration of p-type dopant species into source and drain regions 80 of active area 48 which are displaced from gate conductor 58 b by a distance substantially equivalent to the combined lateral thicknesses of spacers 66 b and 78 b. The p+ S/D implant is performed at a higher dose and energy than the p− LDD implant FIG. 13 depicts the semiconductor topography after masking layer 79 has been removed from active area 46. An NMOS transistor 82 and a PMOS transistor 84 result from the sequence of steps shown in FIGS. 5-13. An ensuing CMOS integrated circuit employing NMOS transistor 82 and PMOS transistor 84 may be formed using well-known semiconductor fabrication techniques.
It will be appreciated to those skilled in the art having the benefit of this disclosure that this invention is believed to provide a method for isotropically etching pairs of sidewall spacers to reduce the lateral thickness of each sidewall spacer. Accordingly, the pre-etch thickness of the sidewall spacers may be used as masking structures for a S/D implant of an NMOS transistor while the post-etch thickness of the spacers may be used as masking structures for an LDD implant of a PMOS transistor. Further modifications and alternative embodiments of various aspects of the invention will be apparent to those skilled in the art in view of this description. It is intended that the following claims be interpreted to embrace all such modifications and changes and, accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.
Claims (21)
1. A method for forming an integrated circuit, comprising:
providing first and second gate conductors laterally spaced apart and dielectrically spaced above respective first and second active areas of a semiconductor substrate;
implanting a first concentration of a first type of dopant into regions of the first active area aligned with opposed sidewalls of the first gate conductor;
subsequent to said implanting a first concentration of a first type of dopant into regions of the first active area aligned with opposed sidewalls of the first gate conductor, forming first and second pairs of sidewall spacers extending laterally from respective first and second opposed sidewall surfaces of the first and second gate conductors;
implanting the first type of dopant into source and drain regions of the first active area spaced from the first gate conductor by the first pair of sidewall spacers;
isotropically etching the first and second pairs of sidewall spacers to reduce a lateral thickness of the first and second pairs of sidewall spacers; and
implanting a second type of dopant into regions of the second active area spaced from the second gate conductor by the second pair of sidewall spacers having the reduced lateral thickness.
2. The method of claim 1, wherein the first active area is laterally spaced from the second active area by an isolation structure.
3. The method of claim 1, further comprising, prior to said implanting a first concentration of a first type of dopant into regions of the first active area aligned with opposed sidewalls of the first gate conductor, forming a first masking layer across the second gate conductor and the second active area.
4. The method of claim 3, wherein the first type of dopant is implanted into the first source and drain regions at a second concentration greater than the first concentration.
5. The method of claim 4, further comprising removing the first masking layer from the second gate conductor and the second active area prior to said forming first and second pairs of sidewall spacers.
6. The method of claim 5, further comprising forming a second masking layer across the second gate conductor, the second pair of sidewall spacers, and the second active area prior to said implanting the first type of dopant into the first source and drain regions.
7. The method of claim 6, wherein the first type of dopant comprises an n-type dopant species.
8. The method of claim 6, further comprising removing the second masking layer prior to said isotropically etching the first and second pairs of sidewall spacers.
9. The method of claim 8, further comprising forming a third masking layer across the first gate conductor, the first pair of sidewall spacers, and the first source and drain regions prior to said implanting a second type of dopant into regions of the second active area.
10. The method of claim 9, wherein the second type of dopant comprises a p-type dopant species.
11. The method of claim 9, further comprising removing the third masking layer, and forming third and fourth pairs of sidewall spacers laterally extending from the first and second pairs of sidewall spacers, respectively, subsequent to said implanting a second type of dopant into regions of the second active area.
12. The method of claim 11, further comprising forming a fourth masking layer across the first gate conductor, the first and third pairs of sidewall spacers, and the first active area.
13. The method of claim 12, further comprising implanting the second type of dopant into second source and drain regions of the second active area at a higher concentration than said implanting a second type of dopant into regions of the second active area, wherein the second source and drain regions are spaced from the second gate conductor by the second and fourth pairs of sidewall spacers.
14. A method for forming an integrated circuit, comprising:
forming a first pair of sidewall spacers on opposed sidewall surfaces of a first gate conductor and a second pair of sidewall spacers on opposed sidewall surfaces of a second gate conductor;
implanting a first type of dopant into first regions of a semiconductor substrate self-aligned to outer lateral edges of said first pair of sidewall spacers;
etching the first and second pairs of sidewall spacers to reduce a lateral thickness of the first and second pairs of sidewall spacers;
implanting a second type of dopant into second regions of the semiconductor substrate self-aligned to outer lateral edges of the second pair of sidewall spacers having the reduced lateral thickness;
subsequent to said etching, forming a third pair of sidewall spacers laterally extending from said first pair of sidewall spacers and a fourth pair of sidewall spacers laterally extending from said second pair of sidewall spacers; and
implanting the second type of dopant into third regions of the semiconductor substrate self-aligned to outer lateral edges of the fourth pair of sidewall spacers.
15. The method as recited in claim 14, further comprising, prior to said forming a first pair of sidewall spacers, implanting the first type of dopant into fourth regions of the semiconductor substrate self-aligned to outer lateral edges of said first gate conductor.
16. The method as recited in claim 14, wherein the combined lateral thickness on each side of said second gate conductor of said second pair of sidewall spacers after said etching and said fourth pair of sidewall spacers is greater than said second pair of sidewall spacers before said etching.
17. The method as recited in claim 14, wherein said first and second sidewall spacers are formed from a single type of spacer material.
18. A method for forming an integrated circuit, comprising:
providing first and second gate conductors laterally spaced apart and dielectrically spaced above respective first and second active areas of a semiconductor substrate;
forming first and second pairs of sidewall spacers extending laterally from respective first and second opposed sidewall surfaces of the first and second gate conductors, wherein said first and second sidewall spacers are formed from a single type of spacer material;
implanting a first type of dopant into source and drain regions of the first active area spaced from the first gate conductor by the first pair of sidewall spacers;
isotropically etching the first and second pairs of sidewall spacers to reduce a lateral thickness of the first and second pairs of sidewall spacers; and
implanting a second type of dopant into regions of the second active area spaced from the second gate conductor by the second pair of sidewall spacers having the reduced lateral thickness.
19. The method as recited in claim 18, further comprising prior to said forming first and second pairs of sidewall spacers, implanting the first type of dopant into regions of the first active area self-aligned to first gate conductor.
20. The method as recited in claim 18, further comprising, subsequent to said implanting a second type of dopant:
forming third and fourth pairs of sidewall spacers laterally extending from said first and second pairs of sidewall spacers respectively; and
implanting the second type of dopant into source and drain regions of the second active area spaced from the second gate conductor by the combined lateral thickness of the second pair of sidewall spacers having the reduced lateral thickness and the fourth pair of sidewall spacers.
21. A method for forming an integrated circuit, comprising:
forming a first pair of sidewall spacers on opposed sidewall surfaces of a first gate conductor and a second pair of sidewall spacers on opposed sidewall surfaces of a second gate conductor;
forming first dopant regions self-aligned said first pair of sidewall spacers;
etching the second pair of sidewall spacers to reduce a lateral thickness of the second pair of sidewall spacers;
forming second dopant regions self-aligned to the second pair of sidewall spacers having the reduced lateral thickness;
subsequent to said etching, forming an additional pair of sidewall spacers laterally extending from said second pair of sidewall spacers; and
forming third dopant regions self-aligned to the additional pair of sidewall spacers.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/604,051 US6316302B1 (en) | 1998-06-26 | 2000-06-26 | Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/105,872 US6124610A (en) | 1998-06-26 | 1998-06-26 | Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant |
US09/604,051 US6316302B1 (en) | 1998-06-26 | 2000-06-26 | Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/105,872 Division US6124610A (en) | 1998-06-26 | 1998-06-26 | Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant |
Publications (1)
Publication Number | Publication Date |
---|---|
US6316302B1 true US6316302B1 (en) | 2001-11-13 |
Family
ID=22308245
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/105,872 Expired - Lifetime US6124610A (en) | 1998-06-26 | 1998-06-26 | Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant |
US09/604,051 Expired - Lifetime US6316302B1 (en) | 1998-06-26 | 2000-06-26 | Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/105,872 Expired - Lifetime US6124610A (en) | 1998-06-26 | 1998-06-26 | Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant |
Country Status (2)
Country | Link |
---|---|
US (2) | US6124610A (en) |
WO (1) | WO2000001011A1 (en) |
Cited By (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6521487B1 (en) * | 2001-12-05 | 2003-02-18 | United Microelectronics Corp. | Method for making a thyristor |
US6551870B1 (en) * | 1998-10-13 | 2003-04-22 | Advanced Micro Devices, Inc. | Method of fabricating ultra shallow junction CMOS transistors with nitride disposable spacer |
US6551882B2 (en) * | 1998-12-21 | 2003-04-22 | Kabushiki Kaisha Toshiba | Semiconductor device manufacturing method permitting suppression of leak current through the PN junction |
WO2003052799A2 (en) * | 2001-12-14 | 2003-06-26 | Advanced Micro Devices, Inc. | A method of forming differential spacers for individual optimization of n-channel and p-channel transistors |
US20030124864A1 (en) * | 2001-12-28 | 2003-07-03 | Hirofumi Komori | Semiconductor device and its manufacturing method |
US6593623B1 (en) * | 1998-03-30 | 2003-07-15 | Advanced Micro Devices, Inc. | Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion |
US6706605B1 (en) * | 2003-03-31 | 2004-03-16 | Texas Instruments Incorporated | Transistor formed from stacked disposable sidewall spacer |
US20040092074A1 (en) * | 2002-11-07 | 2004-05-13 | Nanya Technology Corporation | Method of forming source/drain regions in semiconductor devices |
US20040132241A1 (en) * | 2000-08-24 | 2004-07-08 | Hitachi, Ltd. | Insulated gate field effect transistor and method of fabricating the same |
US20040164320A1 (en) * | 2003-02-10 | 2004-08-26 | Chartered Semiconductor Manufacturing Ltd. | Method of activating polysilicon gate structure dopants after offset spacer deposition |
US6825529B2 (en) * | 2002-12-12 | 2004-11-30 | International Business Machines Corporation | Stress inducing spacers |
US20050145942A1 (en) * | 2004-01-07 | 2005-07-07 | International Business Machines Corporation | Method of making field effect transistors having self-aligned source and drain regions using independently controlled spacer widths |
US20050190421A1 (en) * | 2004-03-01 | 2005-09-01 | Jian Chen | Integrated circuit with multiple spacer insulating region widths |
US20050242376A1 (en) * | 2004-04-29 | 2005-11-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of making the same |
US20050266643A1 (en) * | 2004-05-28 | 2005-12-01 | Burnett James D | Memory with recessed devices |
US20050275045A1 (en) * | 2004-06-11 | 2005-12-15 | International Business Machines Corporation | Low capacitance fet for operation at subthreshold voltages |
US20050275034A1 (en) * | 2004-04-08 | 2005-12-15 | International Business Machines Corporation | A manufacturable method and structure for double spacer cmos with optimized nfet/pfet performance |
US20060008973A1 (en) * | 2004-07-07 | 2006-01-12 | Phua Timothy W H | Selective oxide trimming to improve metal T-gate transistor |
US20060281271A1 (en) * | 2005-06-13 | 2006-12-14 | Advanced Micro Devices, Inc. | Method of forming a semiconductor device having an epitaxial layer and device thereof |
US20070173453A1 (en) * | 2002-02-21 | 2007-07-26 | Quark Biotech, Inc. | Methods of preventing or treating brain ischemia or brain injury |
US20070181951A1 (en) * | 2006-02-08 | 2007-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Selective CESL structure for CMOS application |
US20080085585A1 (en) * | 2006-10-05 | 2008-04-10 | International Business Machines Corporation | Structure and method for creation of a transistor |
CN100383935C (en) * | 2002-11-22 | 2008-04-23 | 南亚科技股份有限公司 | Method for making source/drain element |
US7402485B1 (en) | 2004-10-20 | 2008-07-22 | Advanced Micro Devices, Inc. | Method of forming a semiconductor device |
US7402207B1 (en) | 2004-05-05 | 2008-07-22 | Advanced Micro Devices, Inc. | Method and apparatus for controlling the thickness of a selective epitaxial growth layer |
US7456062B1 (en) | 2004-10-20 | 2008-11-25 | Advanced Micro Devices, Inc. | Method of forming a semiconductor device |
US20090017588A1 (en) * | 2005-02-02 | 2009-01-15 | Texas Instruments Incorporated | Systems and methods that selectively modify liner induced stress |
JP2009049427A (en) * | 2008-10-22 | 2009-03-05 | Renesas Technology Corp | Mis type semiconductor device and method of manufacturing the same |
US7553732B1 (en) | 2005-06-13 | 2009-06-30 | Advanced Micro Devices, Inc. | Integration scheme for constrained SEG growth on poly during raised S/D processing |
US7572705B1 (en) | 2005-09-21 | 2009-08-11 | Advanced Micro Devices, Inc. | Semiconductor device and method of manufacturing a semiconductor device |
US20110284966A1 (en) * | 2010-05-19 | 2011-11-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and Method for Alignment Marks |
US20120161245A1 (en) * | 2009-12-21 | 2012-06-28 | Panasonic Corporation | Semiconductor device and method for fabricating the same |
US8642415B2 (en) | 2012-05-03 | 2014-02-04 | International Business Machines Corporation | Semiconductor substrate with transistors having different threshold voltages |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6306702B1 (en) * | 1999-08-24 | 2001-10-23 | Advanced Micro Devices, Inc. | Dual spacer method of forming CMOS transistors with substantially the same sub 0.25 micron gate length |
JP2001168323A (en) * | 1999-12-06 | 2001-06-22 | Mitsubishi Electric Corp | Method of manufacturing semiconductor device |
JP2001196549A (en) * | 2000-01-11 | 2001-07-19 | Mitsubishi Electric Corp | Semiconductor device and manufacturing method therefor |
US6492275B2 (en) * | 2000-01-21 | 2002-12-10 | Advanced Micro Devices, Inc. | Control of transistor performance through adjustment of spacer oxide profile with a wet etch |
US6444531B1 (en) * | 2000-08-24 | 2002-09-03 | Infineon Technologies Ag | Disposable spacer technology for device tailoring |
JP4897146B2 (en) * | 2001-03-02 | 2012-03-14 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method and semiconductor device |
US6767770B1 (en) | 2002-10-01 | 2004-07-27 | T-Ram, Inc. | Method of forming self-aligned thin capacitively-coupled thyristor structure |
US6828202B1 (en) | 2002-10-01 | 2004-12-07 | T-Ram, Inc. | Semiconductor region self-aligned with ion implant shadowing |
US7125753B1 (en) | 2002-10-01 | 2006-10-24 | T-Ram Semiconductor, Inc. | Self-aligned thin capacitively-coupled thyristor structure |
KR100965213B1 (en) * | 2002-12-30 | 2010-06-22 | 동부일렉트로닉스 주식회사 | Method for forming transistor in semiconductor device |
US7056782B2 (en) * | 2004-02-25 | 2006-06-06 | International Business Machines Corporation | CMOS silicide metal gate integration |
JP4361880B2 (en) * | 2005-01-11 | 2009-11-11 | 富士通マイクロエレクトロニクス株式会社 | Manufacturing method of semiconductor integrated circuit device |
US7858458B2 (en) | 2005-06-14 | 2010-12-28 | Micron Technology, Inc. | CMOS fabrication |
KR100720474B1 (en) * | 2005-06-17 | 2007-05-22 | 동부일렉트로닉스 주식회사 | CMOS Image sensor and Method for fabricating of the same |
US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
US8114750B2 (en) * | 2008-04-17 | 2012-02-14 | International Business Machines Corporation | Lateral diffusion field effect transistor with drain region self-aligned to gate electrode |
US20090283843A1 (en) * | 2008-05-13 | 2009-11-19 | Micrel, Inc. | NMOS Transistor Including Extended NLDD-Drain For Improved Ruggedness |
US20100032753A1 (en) * | 2008-05-13 | 2010-02-11 | Micrel, Inc. | MOS Transistor Including Extended NLDD Source-Drain Regions For Improved Ruggedness |
CN102412205A (en) * | 2011-05-13 | 2012-04-11 | 上海华力微电子有限公司 | Process for adjusting characteristic size of gate sidewall layer in light-doped drain ion implantation |
Citations (112)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4172260A (en) | 1976-12-01 | 1979-10-23 | Hitachi, Ltd. | Insulated gate field effect transistor with source field shield extending over multiple region channel |
US4222062A (en) | 1976-05-04 | 1980-09-09 | American Microsystems, Inc. | VMOS Floating gate memory device |
US4356623A (en) | 1980-09-15 | 1982-11-02 | Texas Instruments Incorporated | Fabrication of submicron semiconductor devices |
JPS58137255A (en) | 1982-02-10 | 1983-08-15 | Hitachi Ltd | Insulated gate type field-effect transistor |
US4463491A (en) | 1982-04-23 | 1984-08-07 | Gte Laboratories Incorporated | Method of fabricating a monolithic integrated circuit structure |
US4638347A (en) | 1982-12-07 | 1987-01-20 | International Business Machines Corporation | Gate electrode sidewall isolation spacer for field effect transistors |
US4652897A (en) | 1984-07-13 | 1987-03-24 | Hitachi, Ltd. | Semiconductor memory device |
US4672419A (en) | 1984-06-25 | 1987-06-09 | Texas Instruments Incorporated | Metal gate, interconnect and contact system for VLSI devices |
JPS62200757A (en) | 1986-02-28 | 1987-09-04 | Toshiba Corp | Mos-type semiconductor device |
US4737828A (en) | 1986-03-17 | 1988-04-12 | General Electric Company | Method for gate electrode fabrication and symmetrical and non-symmetrical self-aligned inlay transistors made therefrom |
JPS63161660A (en) | 1986-12-25 | 1988-07-05 | Toshiba Corp | Semiconductor device |
US4788663A (en) | 1987-04-24 | 1988-11-29 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device with a lightly-doped drain structure |
US4818715A (en) | 1987-07-09 | 1989-04-04 | Industrial Technology Research Institute | Method of fabricating a LDDFET with self-aligned silicide |
US4818714A (en) | 1987-12-02 | 1989-04-04 | Advanced Micro Devices, Inc. | Method of making a high performance MOS device having LDD regions with graded junctions |
US4835112A (en) | 1988-03-08 | 1989-05-30 | Motorola, Inc. | CMOS salicide process using germanium implantation |
US4843023A (en) | 1985-09-25 | 1989-06-27 | Hewlett-Packard Company | Process for forming lightly-doped-drain (LDD) without extra masking steps |
US4868617A (en) | 1988-04-25 | 1989-09-19 | Elite Semiconductor & Sytems International, Inc. | Gate controllable lightly doped drain mosfet devices |
US4949136A (en) | 1988-06-09 | 1990-08-14 | University Of Connecticut | Submicron lightly doped field effect transistors |
US4951100A (en) | 1989-07-03 | 1990-08-21 | Motorola, Inc. | Hot electron collector for a LDD transistor |
US4952825A (en) | 1988-03-14 | 1990-08-28 | Nec Corporation | Semiconductor integrated circuit having signal level conversion circuit |
US4968639A (en) | 1987-12-21 | 1990-11-06 | Sgs-Thomson Microelectronics S.R.L. | Process for manufacturing CMOS integrated devices with reduced gate lengths |
US4971922A (en) | 1984-08-22 | 1990-11-20 | Mitsubishi Denki Kabushiki Kaisha | Method of fabricating semiconductor device |
US4994869A (en) | 1989-06-30 | 1991-02-19 | Texas Instruments Incorporated | NMOS transistor having inversion layer source/drain contacts |
US4994404A (en) | 1989-08-28 | 1991-02-19 | Motorola, Inc. | Method for forming a lightly-doped drain (LDD) structure in a semiconductor device |
JPH0341773A (en) | 1989-07-10 | 1991-02-22 | Sony Corp | Semiconductor device and manufacture thereof |
US5015598A (en) | 1989-11-03 | 1991-05-14 | U.S. Philips Corporation | Method of manufacturing a device comprising MIS transistors having a gate electrode in the form of an inverted "T" |
US5091763A (en) | 1990-12-19 | 1992-02-25 | Intel Corporation | Self-aligned overlap MOSFET and method of fabrication |
JPH0485968A (en) | 1990-07-30 | 1992-03-18 | Nec Corp | Mos semiconductor device and manufacture thereof |
US5119152A (en) | 1990-03-19 | 1992-06-02 | Kabushiki Kaisha Toshiba | MOS semiconductor device having LDD structure |
JPH04171730A (en) | 1990-11-02 | 1992-06-18 | Mitsubishi Electric Corp | Semiconductor device |
JPH04208571A (en) | 1990-11-30 | 1992-07-30 | Matsushita Electron Corp | Insulated-gate fet |
US5153145A (en) | 1989-10-17 | 1992-10-06 | At&T Bell Laboratories | Fet with gate spacer |
US5168072A (en) | 1990-10-12 | 1992-12-01 | Texas Instruments Incorporated | Method of fabricating an high-performance insulated-gate field-effect transistor |
JPH0575115A (en) | 1991-09-12 | 1993-03-26 | Toshiba Corp | Semiconductor device and manufacture thereof |
US5216268A (en) | 1991-09-23 | 1993-06-01 | Integrated Silicon Solution, Inc. | Full-featured EEPROM |
US5221632A (en) | 1990-10-31 | 1993-06-22 | Matsushita Electric Industrial Co., Ltd. | Method of proudcing a MIS transistor |
US5241203A (en) | 1991-07-10 | 1993-08-31 | International Business Machines Corporation | Inverse T-gate FET transistor with lightly doped source and drain region |
US5254866A (en) | 1990-04-03 | 1993-10-19 | Mitsubishi Denki Kabushiki Kaisha | LDD CMOS with wider oxide sidewall on PMOS than NMOS |
US5258319A (en) | 1988-02-19 | 1993-11-02 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a MOS type field effect transistor using an oblique ion implantation step |
US5274261A (en) | 1990-07-31 | 1993-12-28 | Texas Instruments Incorporated | Integrated circuit degradation resistant structure |
US5278441A (en) | 1991-02-27 | 1994-01-11 | Samsung Electronics Co. Ltd. | Method for fabricating a semiconductor transistor and structure thereof |
US5286664A (en) | 1991-10-01 | 1994-02-15 | Nec Corporation | Method for fabricating the LDD-MOSFET |
US5296401A (en) | 1990-01-11 | 1994-03-22 | Mitsubishi Denki Kabushiki Kaisha | MIS device having p channel MOS device and n channel MOS device with LDD structure and manufacturing method thereof |
US5324974A (en) | 1990-09-04 | 1994-06-28 | Industrial Technology Research Institute | Nitride capped MOSFET for integrated circuits |
US5332914A (en) | 1988-02-05 | 1994-07-26 | Emanuel Hazani | EEPROM cell structure and architecture with increased capacitance and with programming and erase terminals shared between several cells |
US5334870A (en) | 1992-04-17 | 1994-08-02 | Nippondenso Co. Ltd. | Complementary MIS transistor and a fabrication process thereof |
US5341003A (en) | 1991-06-10 | 1994-08-23 | Fuji Electric Co., Ltd. | MOS semiconductor device having a main unit element and a sense unit element for monitoring the current in the main unit element |
US5369297A (en) | 1991-09-05 | 1994-11-29 | Mitsubishi Denki Kabushiki Kaisha | Field effect transistor including silicon oxide film and nitrided oxide film as gate insulator film and manufacturing method thereof |
US5371394A (en) | 1993-11-15 | 1994-12-06 | Motorola, Inc. | Double implanted laterally diffused MOS device and method thereof |
US5386133A (en) | 1991-02-05 | 1995-01-31 | Matsushita Electric Industrial Co., Ltd. | LDD FET with polysilicon sidewalls |
US5405791A (en) | 1994-10-04 | 1995-04-11 | Micron Semiconductor, Inc. | Process for fabricating ULSI CMOS circuits using a single polysilicon gate layer and disposable spacers |
US5422506A (en) | 1991-04-01 | 1995-06-06 | Sgs-Thomson Microelectronics, Inc. | Field effect transistor structure heavily doped source/drain regions and lightly doped source/drain regions |
US5424234A (en) | 1991-06-13 | 1995-06-13 | Goldstar Electron Co., Ltd. | Method of making oxide semiconductor field effect transistor |
US5432106A (en) | 1993-08-02 | 1995-07-11 | United Microelectronics Corporation | Manufacture of an asymmetric non-volatile memory cell |
US5444282A (en) | 1990-10-09 | 1995-08-22 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and a method of manufacturing thereof |
US5460993A (en) | 1995-04-03 | 1995-10-24 | Taiwan Semiconductor Manufacturing Company Ltd. | Method of making NMOS and PMOS LDD transistors utilizing thinned sidewall spacers |
US5470773A (en) | 1994-04-25 | 1995-11-28 | Advanced Micro Devices, Inc. | Method protecting a stacked gate edge in a semiconductor device from self aligned source (SAS) etch |
US5473184A (en) | 1993-03-05 | 1995-12-05 | Nippon Steel Corporation | Semiconductor device and method for fabricating same |
US5477070A (en) | 1993-04-13 | 1995-12-19 | Samsung Electronics Co., Ltd. | Drive transistor for CCD-type image sensor |
US5480814A (en) | 1994-12-27 | 1996-01-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Process of making a polysilicon barrier layer in a self-aligned contact module |
US5482880A (en) | 1991-08-30 | 1996-01-09 | Texas Instruments Incorporated | Non-volatile memory cell and fabrication method |
US5493130A (en) | 1993-06-10 | 1996-02-20 | Micron Technology, Inc. | Integrated circuitry having an electrically conductive sidewall link positioned over and electrically interconnecting respective outer sidewalls of two conductive layers |
US5498555A (en) | 1994-11-07 | 1996-03-12 | United Microelectronics Corporation | Method of making LDD with polysilicon and dielectric spacers |
US5501997A (en) | 1994-05-03 | 1996-03-26 | United Microelectronics Corp. | Process of fabricating semiconductor devices having lightly-doped drain |
US5510284A (en) | 1993-08-27 | 1996-04-23 | Sharp Kabushiki Kaisha | Method for manufacturing an asymetric non-volatile memory |
US5510279A (en) | 1995-01-06 | 1996-04-23 | United Microelectronics Corp. | Method of fabricating an asymmetric lightly doped drain transistor device |
US5512771A (en) | 1992-11-04 | 1996-04-30 | Matsushita Electric Industrial Co., Ltd. | MOS type semiconductor device having a low concentration impurity diffusion region |
US5516707A (en) | 1995-06-12 | 1996-05-14 | Vlsi Technology, Inc. | Large-tilted-angle nitrogen implant into dielectric regions overlaying source/drain regions of a transistor |
US5545578A (en) | 1994-06-08 | 1996-08-13 | Samsung Electronics Co., Ltd. | Method of maufacturing a semiconductor device having a low resistance gate electrode |
US5565369A (en) | 1993-09-03 | 1996-10-15 | United Microelectronics Corporation | Method of making retarded DDD (double diffused drain) device structure |
US5576556A (en) | 1993-08-20 | 1996-11-19 | Semiconductor Energy Laboratory Co., Ltd. | Thin film semiconductor device with gate metal oxide and sidewall spacer |
US5580804A (en) | 1994-12-15 | 1996-12-03 | Advanced Micro Devices, Inc. | Method for fabricating true LDD devices in a MOS technology |
US5583067A (en) | 1993-01-22 | 1996-12-10 | Intel Corporation | Inverse T-gate semiconductor device with self-aligned punchthrough stops and method of fabrication |
US5602045A (en) | 1995-01-30 | 1997-02-11 | Sony Corporation | Method for making a semiconductor device |
US5607869A (en) | 1993-12-30 | 1997-03-04 | Nec Corporation | Method for manufacturing asymmetrical LDD type MIS device |
US5608240A (en) | 1993-12-01 | 1997-03-04 | Nec Corporation | Semiconductor integrated circuit having at least one asymmetrical CMOS transistor |
US5629220A (en) | 1993-07-27 | 1997-05-13 | United Microelectronics Corporation | Method of manufacture of pull down transistor with drain off-set for low leakage SRAM's |
US5654215A (en) | 1996-09-13 | 1997-08-05 | Advanced Micro Devices, Inc. | Method for fabrication of a non-symmetrical transistor |
US5656518A (en) | 1996-09-13 | 1997-08-12 | Advanced Micro Devices, Inc. | Method for fabrication of a non-symmetrical transistor |
US5677224A (en) | 1996-09-03 | 1997-10-14 | Advanced Micro Devices, Inc. | Method of making asymmetrical N-channel and P-channel devices |
US5696019A (en) | 1996-06-24 | 1997-12-09 | Macronix International Co., Ltd. | Self-aligned trench isolation for memory array using sidewall spacers |
US5702972A (en) * | 1997-01-27 | 1997-12-30 | Taiwan Semiconductor Manufacturing Company Ltd. | Method of fabricating MOSFET devices |
US5705439A (en) | 1996-04-22 | 1998-01-06 | Taiwan Semiconductor Manufacturing Company Ltd. | Method to make an asymmetrical LDD structure for deep sub-micron MOSFETS |
US5710450A (en) | 1994-12-23 | 1998-01-20 | Intel Corporation | Transistor with ultra shallow tip and method of fabrication |
US5719425A (en) | 1996-01-31 | 1998-02-17 | Micron Technology, Inc. | Multiple implant lightly doped drain (MILDD) field effect transistor |
US5723352A (en) * | 1995-08-03 | 1998-03-03 | Taiwan Semiconductor Manufacturing Company | Process to optimize performance and reliability of MOSFET devices |
US5739573A (en) | 1994-07-22 | 1998-04-14 | Nec Corporation | Semiconductor device with improved salicide structure and a method of manufacturing the same |
US5741736A (en) | 1995-05-04 | 1998-04-21 | Motorola Inc. | Process for forming a transistor with a nonuniformly doped channel |
US5747373A (en) * | 1996-09-24 | 1998-05-05 | Taiwan Semiconductor Manufacturing Company Ltd. | Nitride-oxide sidewall spacer for salicide formation |
US5757045A (en) | 1996-07-17 | 1998-05-26 | Taiwan Semiconductor Manufacturing Company Ltd. | CMOS device structure with reduced risk of salicide bridging and reduced resistance via use of a ultra shallow, junction extension, ion implantation |
US5759901A (en) * | 1995-04-06 | 1998-06-02 | Vlsi Technology, Inc. | Fabrication method for sub-half micron CMOS transistor |
US5766969A (en) | 1996-12-06 | 1998-06-16 | Advanced Micro Devices, Inc. | Multiple spacer formation/removal technique for forming a graded junction |
US5789780A (en) | 1996-12-03 | 1998-08-04 | Advanced Micro Devices, Inc. | Transistor with source and drain regions within the semiconductor substrate detached or laterally displaced from the transistor gate |
US5793089A (en) | 1997-01-10 | 1998-08-11 | Advanced Micro Devices, Inc. | Graded MOS transistor junction formed by aligning a sequence of implants to a selectively removable polysilicon sidewall space and oxide thermally grown thereon |
US5801077A (en) * | 1996-04-22 | 1998-09-01 | Chartered Semiconductor Manufacturing Ltd. | Method of making sidewall polymer on polycide gate for LDD structure |
US5827747A (en) * | 1996-03-28 | 1998-10-27 | Mosel Vitelic, Inc. | Method for forming LDD CMOS using double spacers and large-tilt-angle ion implantation |
US5837572A (en) | 1997-01-10 | 1998-11-17 | Advanced Micro Devices, Inc. | CMOS integrated circuit formed by using removable spacers to produce asymmetrical NMOS junctions before asymmetrical PMOS junctions for optimizing thermal diffusivity of dopants implanted therein |
US5847428A (en) | 1996-12-06 | 1998-12-08 | Advanced Micro Devices, Inc. | Integrated circuit gate conductor which uses layered spacers to produce a graded junction |
US5846857A (en) * | 1997-09-05 | 1998-12-08 | Advanced Micro Devices, Inc. | CMOS processing employing removable sidewall spacers for independently optimized N- and P-channel transistor performance |
US5851866A (en) * | 1996-11-27 | 1998-12-22 | Lg Semicon Co., Ltd. | Fabrication method for CMOS with sidewalls |
US5869866A (en) | 1996-12-06 | 1999-02-09 | Advanced Micro Devices, Inc. | Integrated circuit having sacrificial spacers for producing graded NMOS source/drain junctions possibly dissimilar from PMOS source/drain junctions |
US5869879A (en) | 1996-12-06 | 1999-02-09 | Advanced Micro Devices, Inc. | CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions |
US5882973A (en) | 1997-01-27 | 1999-03-16 | Advanced Micro Devices, Inc. | Method for forming an integrated circuit having transistors of dissimilarly graded junction profiles |
US5895955A (en) | 1997-01-10 | 1999-04-20 | Advanced Micro Devices, Inc. | MOS transistor employing a removable, dual layer etch stop to protect implant regions from sidewall spacer overetch |
US5898202A (en) | 1996-12-03 | 1999-04-27 | Advanced Micro Devices, Inc. | Selective spacer formation for optimized silicon area reduction |
US5900666A (en) | 1996-12-03 | 1999-05-04 | Advanced Micro Devices, Inc. | Ultra-short transistor fabrication scheme for enhanced reliability |
US5899722A (en) * | 1998-05-22 | 1999-05-04 | Taiwan Semiconductor Manufacturing Company Ltd. | Method of forming dual spacer for self aligned contact integration |
US6090692A (en) * | 1995-07-26 | 2000-07-18 | Lg Semicon Co., Ltd. | Fabrication method for semiconductor memory device |
US6107149A (en) * | 1997-09-05 | 2000-08-22 | Advanced Micro Devices, Inc. | CMOS semiconductor device comprising graded junctions with reduced junction capacitance |
US6130135A (en) * | 1998-05-18 | 2000-10-10 | Powerchip Semiconductor Corp. | Method of fabricating lightly-doped drain transistor having inverse-T gate structure |
US6153455A (en) * | 1998-10-13 | 2000-11-28 | Advanced Micro Devices | Method of fabricating ultra shallow junction CMOS transistors with nitride disposable spacer |
US6191044B1 (en) * | 1998-10-08 | 2001-02-20 | Advanced Micro Devices, Inc. | Method for forming graded LDD transistor using controlled polysilicon gate profile |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2781918B2 (en) * | 1989-04-20 | 1998-07-30 | 三菱電機株式会社 | Method for manufacturing MOS type semiconductor device |
JPH06216151A (en) * | 1993-01-14 | 1994-08-05 | Sony Corp | Semiconductor device and manufacture thereof |
-
1998
- 1998-06-26 US US09/105,872 patent/US6124610A/en not_active Expired - Lifetime
-
1999
- 1999-02-12 WO PCT/US1999/003135 patent/WO2000001011A1/en active Application Filing
-
2000
- 2000-06-26 US US09/604,051 patent/US6316302B1/en not_active Expired - Lifetime
Patent Citations (116)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4222062A (en) | 1976-05-04 | 1980-09-09 | American Microsystems, Inc. | VMOS Floating gate memory device |
US4172260A (en) | 1976-12-01 | 1979-10-23 | Hitachi, Ltd. | Insulated gate field effect transistor with source field shield extending over multiple region channel |
US4356623A (en) | 1980-09-15 | 1982-11-02 | Texas Instruments Incorporated | Fabrication of submicron semiconductor devices |
US4356623B1 (en) | 1980-09-15 | 1989-07-25 | ||
JPS58137255A (en) | 1982-02-10 | 1983-08-15 | Hitachi Ltd | Insulated gate type field-effect transistor |
US4463491A (en) | 1982-04-23 | 1984-08-07 | Gte Laboratories Incorporated | Method of fabricating a monolithic integrated circuit structure |
US4638347A (en) | 1982-12-07 | 1987-01-20 | International Business Machines Corporation | Gate electrode sidewall isolation spacer for field effect transistors |
US4672419A (en) | 1984-06-25 | 1987-06-09 | Texas Instruments Incorporated | Metal gate, interconnect and contact system for VLSI devices |
US4652897A (en) | 1984-07-13 | 1987-03-24 | Hitachi, Ltd. | Semiconductor memory device |
US4971922A (en) | 1984-08-22 | 1990-11-20 | Mitsubishi Denki Kabushiki Kaisha | Method of fabricating semiconductor device |
US4843023A (en) | 1985-09-25 | 1989-06-27 | Hewlett-Packard Company | Process for forming lightly-doped-drain (LDD) without extra masking steps |
JPS62200757A (en) | 1986-02-28 | 1987-09-04 | Toshiba Corp | Mos-type semiconductor device |
US4737828A (en) | 1986-03-17 | 1988-04-12 | General Electric Company | Method for gate electrode fabrication and symmetrical and non-symmetrical self-aligned inlay transistors made therefrom |
JPS63161660A (en) | 1986-12-25 | 1988-07-05 | Toshiba Corp | Semiconductor device |
US4788663A (en) | 1987-04-24 | 1988-11-29 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device with a lightly-doped drain structure |
US4818715A (en) | 1987-07-09 | 1989-04-04 | Industrial Technology Research Institute | Method of fabricating a LDDFET with self-aligned silicide |
US4818714A (en) | 1987-12-02 | 1989-04-04 | Advanced Micro Devices, Inc. | Method of making a high performance MOS device having LDD regions with graded junctions |
US4968639A (en) | 1987-12-21 | 1990-11-06 | Sgs-Thomson Microelectronics S.R.L. | Process for manufacturing CMOS integrated devices with reduced gate lengths |
US5332914A (en) | 1988-02-05 | 1994-07-26 | Emanuel Hazani | EEPROM cell structure and architecture with increased capacitance and with programming and erase terminals shared between several cells |
US5258319A (en) | 1988-02-19 | 1993-11-02 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a MOS type field effect transistor using an oblique ion implantation step |
US4835112A (en) | 1988-03-08 | 1989-05-30 | Motorola, Inc. | CMOS salicide process using germanium implantation |
US4952825A (en) | 1988-03-14 | 1990-08-28 | Nec Corporation | Semiconductor integrated circuit having signal level conversion circuit |
US4868617A (en) | 1988-04-25 | 1989-09-19 | Elite Semiconductor & Sytems International, Inc. | Gate controllable lightly doped drain mosfet devices |
US4949136A (en) | 1988-06-09 | 1990-08-14 | University Of Connecticut | Submicron lightly doped field effect transistors |
US4994869A (en) | 1989-06-30 | 1991-02-19 | Texas Instruments Incorporated | NMOS transistor having inversion layer source/drain contacts |
US4951100A (en) | 1989-07-03 | 1990-08-21 | Motorola, Inc. | Hot electron collector for a LDD transistor |
JPH0341773A (en) | 1989-07-10 | 1991-02-22 | Sony Corp | Semiconductor device and manufacture thereof |
US4994404A (en) | 1989-08-28 | 1991-02-19 | Motorola, Inc. | Method for forming a lightly-doped drain (LDD) structure in a semiconductor device |
US5153145A (en) | 1989-10-17 | 1992-10-06 | At&T Bell Laboratories | Fet with gate spacer |
US5015598A (en) | 1989-11-03 | 1991-05-14 | U.S. Philips Corporation | Method of manufacturing a device comprising MIS transistors having a gate electrode in the form of an inverted "T" |
US5296401A (en) | 1990-01-11 | 1994-03-22 | Mitsubishi Denki Kabushiki Kaisha | MIS device having p channel MOS device and n channel MOS device with LDD structure and manufacturing method thereof |
US5119152A (en) | 1990-03-19 | 1992-06-02 | Kabushiki Kaisha Toshiba | MOS semiconductor device having LDD structure |
US5254866A (en) | 1990-04-03 | 1993-10-19 | Mitsubishi Denki Kabushiki Kaisha | LDD CMOS with wider oxide sidewall on PMOS than NMOS |
US5547885A (en) | 1990-04-03 | 1996-08-20 | Mitsubishi Denki Kabushiki Kaisha | Method of making asymmetric LDD transistor |
JPH0485968A (en) | 1990-07-30 | 1992-03-18 | Nec Corp | Mos semiconductor device and manufacture thereof |
US5274261A (en) | 1990-07-31 | 1993-12-28 | Texas Instruments Incorporated | Integrated circuit degradation resistant structure |
US5324974A (en) | 1990-09-04 | 1994-06-28 | Industrial Technology Research Institute | Nitride capped MOSFET for integrated circuits |
US5444282A (en) | 1990-10-09 | 1995-08-22 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and a method of manufacturing thereof |
US5168072A (en) | 1990-10-12 | 1992-12-01 | Texas Instruments Incorporated | Method of fabricating an high-performance insulated-gate field-effect transistor |
US5221632A (en) | 1990-10-31 | 1993-06-22 | Matsushita Electric Industrial Co., Ltd. | Method of proudcing a MIS transistor |
JPH04171730A (en) | 1990-11-02 | 1992-06-18 | Mitsubishi Electric Corp | Semiconductor device |
JPH04208571A (en) | 1990-11-30 | 1992-07-30 | Matsushita Electron Corp | Insulated-gate fet |
US5091763A (en) | 1990-12-19 | 1992-02-25 | Intel Corporation | Self-aligned overlap MOSFET and method of fabrication |
US5386133A (en) | 1991-02-05 | 1995-01-31 | Matsushita Electric Industrial Co., Ltd. | LDD FET with polysilicon sidewalls |
US5278441A (en) | 1991-02-27 | 1994-01-11 | Samsung Electronics Co. Ltd. | Method for fabricating a semiconductor transistor and structure thereof |
US5422506A (en) | 1991-04-01 | 1995-06-06 | Sgs-Thomson Microelectronics, Inc. | Field effect transistor structure heavily doped source/drain regions and lightly doped source/drain regions |
US5341003A (en) | 1991-06-10 | 1994-08-23 | Fuji Electric Co., Ltd. | MOS semiconductor device having a main unit element and a sense unit element for monitoring the current in the main unit element |
US5424234A (en) | 1991-06-13 | 1995-06-13 | Goldstar Electron Co., Ltd. | Method of making oxide semiconductor field effect transistor |
US5241203A (en) | 1991-07-10 | 1993-08-31 | International Business Machines Corporation | Inverse T-gate FET transistor with lightly doped source and drain region |
US5482880A (en) | 1991-08-30 | 1996-01-09 | Texas Instruments Incorporated | Non-volatile memory cell and fabrication method |
US5369297A (en) | 1991-09-05 | 1994-11-29 | Mitsubishi Denki Kabushiki Kaisha | Field effect transistor including silicon oxide film and nitrided oxide film as gate insulator film and manufacturing method thereof |
JPH0575115A (en) | 1991-09-12 | 1993-03-26 | Toshiba Corp | Semiconductor device and manufacture thereof |
US5216268A (en) | 1991-09-23 | 1993-06-01 | Integrated Silicon Solution, Inc. | Full-featured EEPROM |
US5286664A (en) | 1991-10-01 | 1994-02-15 | Nec Corporation | Method for fabricating the LDD-MOSFET |
US5334870A (en) | 1992-04-17 | 1994-08-02 | Nippondenso Co. Ltd. | Complementary MIS transistor and a fabrication process thereof |
US5512771A (en) | 1992-11-04 | 1996-04-30 | Matsushita Electric Industrial Co., Ltd. | MOS type semiconductor device having a low concentration impurity diffusion region |
US5583067A (en) | 1993-01-22 | 1996-12-10 | Intel Corporation | Inverse T-gate semiconductor device with self-aligned punchthrough stops and method of fabrication |
US5473184A (en) | 1993-03-05 | 1995-12-05 | Nippon Steel Corporation | Semiconductor device and method for fabricating same |
US5477070A (en) | 1993-04-13 | 1995-12-19 | Samsung Electronics Co., Ltd. | Drive transistor for CCD-type image sensor |
US5493130A (en) | 1993-06-10 | 1996-02-20 | Micron Technology, Inc. | Integrated circuitry having an electrically conductive sidewall link positioned over and electrically interconnecting respective outer sidewalls of two conductive layers |
US5629220A (en) | 1993-07-27 | 1997-05-13 | United Microelectronics Corporation | Method of manufacture of pull down transistor with drain off-set for low leakage SRAM's |
US5432106A (en) | 1993-08-02 | 1995-07-11 | United Microelectronics Corporation | Manufacture of an asymmetric non-volatile memory cell |
US5576556A (en) | 1993-08-20 | 1996-11-19 | Semiconductor Energy Laboratory Co., Ltd. | Thin film semiconductor device with gate metal oxide and sidewall spacer |
US5510284A (en) | 1993-08-27 | 1996-04-23 | Sharp Kabushiki Kaisha | Method for manufacturing an asymetric non-volatile memory |
US5565369A (en) | 1993-09-03 | 1996-10-15 | United Microelectronics Corporation | Method of making retarded DDD (double diffused drain) device structure |
US5371394A (en) | 1993-11-15 | 1994-12-06 | Motorola, Inc. | Double implanted laterally diffused MOS device and method thereof |
US5608240A (en) | 1993-12-01 | 1997-03-04 | Nec Corporation | Semiconductor integrated circuit having at least one asymmetrical CMOS transistor |
US5607869A (en) | 1993-12-30 | 1997-03-04 | Nec Corporation | Method for manufacturing asymmetrical LDD type MIS device |
US5470773A (en) | 1994-04-25 | 1995-11-28 | Advanced Micro Devices, Inc. | Method protecting a stacked gate edge in a semiconductor device from self aligned source (SAS) etch |
US5501997A (en) | 1994-05-03 | 1996-03-26 | United Microelectronics Corp. | Process of fabricating semiconductor devices having lightly-doped drain |
US5545578A (en) | 1994-06-08 | 1996-08-13 | Samsung Electronics Co., Ltd. | Method of maufacturing a semiconductor device having a low resistance gate electrode |
US5739573A (en) | 1994-07-22 | 1998-04-14 | Nec Corporation | Semiconductor device with improved salicide structure and a method of manufacturing the same |
US5405791A (en) | 1994-10-04 | 1995-04-11 | Micron Semiconductor, Inc. | Process for fabricating ULSI CMOS circuits using a single polysilicon gate layer and disposable spacers |
US5663586A (en) | 1994-11-07 | 1997-09-02 | United Microelectronics Corporation | Fet device with double spacer |
US5641698A (en) * | 1994-11-07 | 1997-06-24 | United Microelectronics Corporation | Method of fabricating FET device with double spacer |
US5498555A (en) | 1994-11-07 | 1996-03-12 | United Microelectronics Corporation | Method of making LDD with polysilicon and dielectric spacers |
US5580804A (en) | 1994-12-15 | 1996-12-03 | Advanced Micro Devices, Inc. | Method for fabricating true LDD devices in a MOS technology |
US5710450A (en) | 1994-12-23 | 1998-01-20 | Intel Corporation | Transistor with ultra shallow tip and method of fabrication |
US5480814A (en) | 1994-12-27 | 1996-01-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Process of making a polysilicon barrier layer in a self-aligned contact module |
US5510279A (en) | 1995-01-06 | 1996-04-23 | United Microelectronics Corp. | Method of fabricating an asymmetric lightly doped drain transistor device |
US5602045A (en) | 1995-01-30 | 1997-02-11 | Sony Corporation | Method for making a semiconductor device |
US5460993A (en) | 1995-04-03 | 1995-10-24 | Taiwan Semiconductor Manufacturing Company Ltd. | Method of making NMOS and PMOS LDD transistors utilizing thinned sidewall spacers |
US5759901A (en) * | 1995-04-06 | 1998-06-02 | Vlsi Technology, Inc. | Fabrication method for sub-half micron CMOS transistor |
US5741736A (en) | 1995-05-04 | 1998-04-21 | Motorola Inc. | Process for forming a transistor with a nonuniformly doped channel |
US5516707A (en) | 1995-06-12 | 1996-05-14 | Vlsi Technology, Inc. | Large-tilted-angle nitrogen implant into dielectric regions overlaying source/drain regions of a transistor |
US6090692A (en) * | 1995-07-26 | 2000-07-18 | Lg Semicon Co., Ltd. | Fabrication method for semiconductor memory device |
US5723352A (en) * | 1995-08-03 | 1998-03-03 | Taiwan Semiconductor Manufacturing Company | Process to optimize performance and reliability of MOSFET devices |
US5719425A (en) | 1996-01-31 | 1998-02-17 | Micron Technology, Inc. | Multiple implant lightly doped drain (MILDD) field effect transistor |
US5827747A (en) * | 1996-03-28 | 1998-10-27 | Mosel Vitelic, Inc. | Method for forming LDD CMOS using double spacers and large-tilt-angle ion implantation |
US5705439A (en) | 1996-04-22 | 1998-01-06 | Taiwan Semiconductor Manufacturing Company Ltd. | Method to make an asymmetrical LDD structure for deep sub-micron MOSFETS |
US5801077A (en) * | 1996-04-22 | 1998-09-01 | Chartered Semiconductor Manufacturing Ltd. | Method of making sidewall polymer on polycide gate for LDD structure |
US5696019A (en) | 1996-06-24 | 1997-12-09 | Macronix International Co., Ltd. | Self-aligned trench isolation for memory array using sidewall spacers |
US5757045A (en) | 1996-07-17 | 1998-05-26 | Taiwan Semiconductor Manufacturing Company Ltd. | CMOS device structure with reduced risk of salicide bridging and reduced resistance via use of a ultra shallow, junction extension, ion implantation |
US5677224A (en) | 1996-09-03 | 1997-10-14 | Advanced Micro Devices, Inc. | Method of making asymmetrical N-channel and P-channel devices |
US5656518A (en) | 1996-09-13 | 1997-08-12 | Advanced Micro Devices, Inc. | Method for fabrication of a non-symmetrical transistor |
US5654215A (en) | 1996-09-13 | 1997-08-05 | Advanced Micro Devices, Inc. | Method for fabrication of a non-symmetrical transistor |
US5747373A (en) * | 1996-09-24 | 1998-05-05 | Taiwan Semiconductor Manufacturing Company Ltd. | Nitride-oxide sidewall spacer for salicide formation |
US5851866A (en) * | 1996-11-27 | 1998-12-22 | Lg Semicon Co., Ltd. | Fabrication method for CMOS with sidewalls |
US5789780A (en) | 1996-12-03 | 1998-08-04 | Advanced Micro Devices, Inc. | Transistor with source and drain regions within the semiconductor substrate detached or laterally displaced from the transistor gate |
US5900666A (en) | 1996-12-03 | 1999-05-04 | Advanced Micro Devices, Inc. | Ultra-short transistor fabrication scheme for enhanced reliability |
US5898202A (en) | 1996-12-03 | 1999-04-27 | Advanced Micro Devices, Inc. | Selective spacer formation for optimized silicon area reduction |
US5766969A (en) | 1996-12-06 | 1998-06-16 | Advanced Micro Devices, Inc. | Multiple spacer formation/removal technique for forming a graded junction |
US5869879A (en) | 1996-12-06 | 1999-02-09 | Advanced Micro Devices, Inc. | CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions |
US5847428A (en) | 1996-12-06 | 1998-12-08 | Advanced Micro Devices, Inc. | Integrated circuit gate conductor which uses layered spacers to produce a graded junction |
US5869866A (en) | 1996-12-06 | 1999-02-09 | Advanced Micro Devices, Inc. | Integrated circuit having sacrificial spacers for producing graded NMOS source/drain junctions possibly dissimilar from PMOS source/drain junctions |
US5837572A (en) | 1997-01-10 | 1998-11-17 | Advanced Micro Devices, Inc. | CMOS integrated circuit formed by using removable spacers to produce asymmetrical NMOS junctions before asymmetrical PMOS junctions for optimizing thermal diffusivity of dopants implanted therein |
US5895955A (en) | 1997-01-10 | 1999-04-20 | Advanced Micro Devices, Inc. | MOS transistor employing a removable, dual layer etch stop to protect implant regions from sidewall spacer overetch |
US5793089A (en) | 1997-01-10 | 1998-08-11 | Advanced Micro Devices, Inc. | Graded MOS transistor junction formed by aligning a sequence of implants to a selectively removable polysilicon sidewall space and oxide thermally grown thereon |
US5882973A (en) | 1997-01-27 | 1999-03-16 | Advanced Micro Devices, Inc. | Method for forming an integrated circuit having transistors of dissimilarly graded junction profiles |
US5702972A (en) * | 1997-01-27 | 1997-12-30 | Taiwan Semiconductor Manufacturing Company Ltd. | Method of fabricating MOSFET devices |
US5846857A (en) * | 1997-09-05 | 1998-12-08 | Advanced Micro Devices, Inc. | CMOS processing employing removable sidewall spacers for independently optimized N- and P-channel transistor performance |
US6107149A (en) * | 1997-09-05 | 2000-08-22 | Advanced Micro Devices, Inc. | CMOS semiconductor device comprising graded junctions with reduced junction capacitance |
US6130135A (en) * | 1998-05-18 | 2000-10-10 | Powerchip Semiconductor Corp. | Method of fabricating lightly-doped drain transistor having inverse-T gate structure |
US5899722A (en) * | 1998-05-22 | 1999-05-04 | Taiwan Semiconductor Manufacturing Company Ltd. | Method of forming dual spacer for self aligned contact integration |
US6191044B1 (en) * | 1998-10-08 | 2001-02-20 | Advanced Micro Devices, Inc. | Method for forming graded LDD transistor using controlled polysilicon gate profile |
US6153455A (en) * | 1998-10-13 | 2000-11-28 | Advanced Micro Devices | Method of fabricating ultra shallow junction CMOS transistors with nitride disposable spacer |
Non-Patent Citations (6)
Title |
---|
Ghandi, Sorab "VLSI Fabrication Principles and Gallium Arsenide," Second Edition, John Wiley and Sons, Inc. pp. 510, 514-517, 535-537 and 576-577. |
International Search Report for Application No. PCT/US99/03135 mailed Jun. 15, 1999. |
Patent Abstracts of Japan, Publication No. 06216151, publisher Aug. 5, 1994. |
Streetman, Solid State Electronic Devices, Prentice-Hall, Inc., 1995, pp. 319-321. |
Wolf, et al., Silicon Processing for the VLSI Era, vol. 1: Process Technology, Lattice Press 1986, p. 183. |
Wolf, Stanley, "Silicon Processing for the VLSI era, vol. 1,: Process Technology," Lattice Press, pp. 280-300. |
Cited By (58)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6593623B1 (en) * | 1998-03-30 | 2003-07-15 | Advanced Micro Devices, Inc. | Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion |
US6551870B1 (en) * | 1998-10-13 | 2003-04-22 | Advanced Micro Devices, Inc. | Method of fabricating ultra shallow junction CMOS transistors with nitride disposable spacer |
US6551882B2 (en) * | 1998-12-21 | 2003-04-22 | Kabushiki Kaisha Toshiba | Semiconductor device manufacturing method permitting suppression of leak current through the PN junction |
US20040132241A1 (en) * | 2000-08-24 | 2004-07-08 | Hitachi, Ltd. | Insulated gate field effect transistor and method of fabricating the same |
US6521487B1 (en) * | 2001-12-05 | 2003-02-18 | United Microelectronics Corp. | Method for making a thyristor |
WO2003052799A2 (en) * | 2001-12-14 | 2003-06-26 | Advanced Micro Devices, Inc. | A method of forming differential spacers for individual optimization of n-channel and p-channel transistors |
WO2003052799A3 (en) * | 2001-12-14 | 2003-08-14 | Advanced Micro Devices Inc | A method of forming differential spacers for individual optimization of n-channel and p-channel transistors |
CN1307689C (en) * | 2001-12-14 | 2007-03-28 | 先进微装置公司 | A method of forming differential spacers for individual optimization of N-channel and P-channel transistors |
US20030124864A1 (en) * | 2001-12-28 | 2003-07-03 | Hirofumi Komori | Semiconductor device and its manufacturing method |
US6847080B2 (en) * | 2001-12-28 | 2005-01-25 | Texas Instruments Incorporated | Semiconductor device with high and low breakdown voltage and its manufacturing method |
US20070173453A1 (en) * | 2002-02-21 | 2007-07-26 | Quark Biotech, Inc. | Methods of preventing or treating brain ischemia or brain injury |
US20040092074A1 (en) * | 2002-11-07 | 2004-05-13 | Nanya Technology Corporation | Method of forming source/drain regions in semiconductor devices |
US6790735B2 (en) * | 2002-11-07 | 2004-09-14 | Nanya Technology Corporation | Method of forming source/drain regions in semiconductor devices |
CN100383935C (en) * | 2002-11-22 | 2008-04-23 | 南亚科技股份有限公司 | Method for making source/drain element |
US6825529B2 (en) * | 2002-12-12 | 2004-11-30 | International Business Machines Corporation | Stress inducing spacers |
US20040164320A1 (en) * | 2003-02-10 | 2004-08-26 | Chartered Semiconductor Manufacturing Ltd. | Method of activating polysilicon gate structure dopants after offset spacer deposition |
US6969646B2 (en) * | 2003-02-10 | 2005-11-29 | Chartered Semiconductor Manufacturing Ltd. | Method of activating polysilicon gate structure dopants after offset spacer deposition |
US6706605B1 (en) * | 2003-03-31 | 2004-03-16 | Texas Instruments Incorporated | Transistor formed from stacked disposable sidewall spacer |
US20050145942A1 (en) * | 2004-01-07 | 2005-07-07 | International Business Machines Corporation | Method of making field effect transistors having self-aligned source and drain regions using independently controlled spacer widths |
US7067366B2 (en) * | 2004-01-07 | 2006-06-27 | International Business Machines Corporation | Method of making field effect transistors having self-aligned source and drain regions using independently controlled spacer widths |
US7064396B2 (en) * | 2004-03-01 | 2006-06-20 | Freescale Semiconductor, Inc. | Integrated circuit with multiple spacer insulating region widths |
CN1926693B (en) * | 2004-03-01 | 2010-10-20 | 飞思卡尔半导体公司 | Integrated circuit with multiple spacer insulating region widths |
US20060011988A1 (en) * | 2004-03-01 | 2006-01-19 | Jian Chen | Integrated circuit with multiple spacer insulating region widths |
WO2005091758A3 (en) * | 2004-03-01 | 2006-01-26 | Freescale Semiconductor Inc | Integrated circuit with multiple spacer insulating region widths |
US20050190421A1 (en) * | 2004-03-01 | 2005-09-01 | Jian Chen | Integrated circuit with multiple spacer insulating region widths |
US20050275034A1 (en) * | 2004-04-08 | 2005-12-15 | International Business Machines Corporation | A manufacturable method and structure for double spacer cmos with optimized nfet/pfet performance |
US20050242376A1 (en) * | 2004-04-29 | 2005-11-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of making the same |
US7259050B2 (en) * | 2004-04-29 | 2007-08-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of making the same |
US7402207B1 (en) | 2004-05-05 | 2008-07-22 | Advanced Micro Devices, Inc. | Method and apparatus for controlling the thickness of a selective epitaxial growth layer |
WO2005119761A2 (en) * | 2004-05-28 | 2005-12-15 | Freescale Semiconductor, Inc. | Memory with recessed devices |
US20050266643A1 (en) * | 2004-05-28 | 2005-12-01 | Burnett James D | Memory with recessed devices |
TWI402942B (en) * | 2004-05-28 | 2013-07-21 | Freescale Semiconductor Inc | Memory with recessed devices |
US7078297B2 (en) * | 2004-05-28 | 2006-07-18 | Freescale Semiconductor, Inc. | Memory with recessed devices |
WO2005119761A3 (en) * | 2004-05-28 | 2006-02-02 | Freescale Semiconductor Inc | Memory with recessed devices |
US20050275045A1 (en) * | 2004-06-11 | 2005-12-15 | International Business Machines Corporation | Low capacitance fet for operation at subthreshold voltages |
US7009265B2 (en) * | 2004-06-11 | 2006-03-07 | International Business Machines Corporation | Low capacitance FET for operation at subthreshold voltages |
US7084025B2 (en) | 2004-07-07 | 2006-08-01 | Chartered Semiconductor Manufacturing Ltd | Selective oxide trimming to improve metal T-gate transistor |
US20060008973A1 (en) * | 2004-07-07 | 2006-01-12 | Phua Timothy W H | Selective oxide trimming to improve metal T-gate transistor |
US7402485B1 (en) | 2004-10-20 | 2008-07-22 | Advanced Micro Devices, Inc. | Method of forming a semiconductor device |
US7456062B1 (en) | 2004-10-20 | 2008-11-25 | Advanced Micro Devices, Inc. | Method of forming a semiconductor device |
US7939400B2 (en) * | 2005-02-02 | 2011-05-10 | Texas Instruments Incorporated | Systems and methods that selectively modify liner induced stress |
US20090017588A1 (en) * | 2005-02-02 | 2009-01-15 | Texas Instruments Incorporated | Systems and methods that selectively modify liner induced stress |
US7553732B1 (en) | 2005-06-13 | 2009-06-30 | Advanced Micro Devices, Inc. | Integration scheme for constrained SEG growth on poly during raised S/D processing |
US20090236664A1 (en) * | 2005-06-13 | 2009-09-24 | Advanced Micro Devices, Inc. | Integration scheme for constrained seg growth on poly during raised s/d processing |
US20060281271A1 (en) * | 2005-06-13 | 2006-12-14 | Advanced Micro Devices, Inc. | Method of forming a semiconductor device having an epitaxial layer and device thereof |
US7910996B2 (en) | 2005-09-21 | 2011-03-22 | Globalfoundries Inc. | Semiconductor device and method of manufacturing a semiconductor device |
US7572705B1 (en) | 2005-09-21 | 2009-08-11 | Advanced Micro Devices, Inc. | Semiconductor device and method of manufacturing a semiconductor device |
US20070181951A1 (en) * | 2006-02-08 | 2007-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Selective CESL structure for CMOS application |
US7696578B2 (en) | 2006-02-08 | 2010-04-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Selective CESL structure for CMOS application |
US20080085585A1 (en) * | 2006-10-05 | 2008-04-10 | International Business Machines Corporation | Structure and method for creation of a transistor |
US7550351B2 (en) * | 2006-10-05 | 2009-06-23 | International Business Machines Corporation | Structure and method for creation of a transistor |
JP2009049427A (en) * | 2008-10-22 | 2009-03-05 | Renesas Technology Corp | Mis type semiconductor device and method of manufacturing the same |
US20120161245A1 (en) * | 2009-12-21 | 2012-06-28 | Panasonic Corporation | Semiconductor device and method for fabricating the same |
US20110284966A1 (en) * | 2010-05-19 | 2011-11-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and Method for Alignment Marks |
US9000525B2 (en) * | 2010-05-19 | 2015-04-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for alignment marks |
US10665585B2 (en) | 2010-05-19 | 2020-05-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for alignment marks |
US11121128B2 (en) | 2010-05-19 | 2021-09-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for alignment marks |
US8642415B2 (en) | 2012-05-03 | 2014-02-04 | International Business Machines Corporation | Semiconductor substrate with transistors having different threshold voltages |
Also Published As
Publication number | Publication date |
---|---|
US6124610A (en) | 2000-09-26 |
WO2000001011A1 (en) | 2000-01-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6316302B1 (en) | Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant | |
US6191446B1 (en) | Formation and control of a vertically oriented transistor channel length | |
US5930642A (en) | Transistor with buried insulative layer beneath the channel region | |
US5082794A (en) | Method of fabricating mos transistors using selective polysilicon deposition | |
US5677224A (en) | Method of making asymmetrical N-channel and P-channel devices | |
US5548143A (en) | Metal oxide semiconductor transistor and a method for manufacturing the same | |
US5759897A (en) | Method of making an asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region | |
US5102816A (en) | Staircase sidewall spacer for improved source/drain architecture | |
US6255152B1 (en) | Method of fabricating CMOS using Si-B layer to form source/drain extension junction | |
EP0164449B1 (en) | Process for producing a semiconductor integrated circuit device including a misfet | |
JP4260905B2 (en) | Method for manufacturing an integrated circuit | |
JPH08330587A (en) | Method for manufacturing integrated circuit, and method for replenishing both diffusion and segregation of boron from channel and field regions to source and drain regions adjacent thereto | |
WO1998048457A1 (en) | Method of making nmos and pmos devices with reduced masking steps | |
US5858848A (en) | Semiconductor fabrication employing self-aligned sidewall spacers laterally adjacent to a transistor gate | |
US6096616A (en) | Fabrication of a non-ldd graded p-channel mosfet | |
US6274443B1 (en) | Simplified graded LDD transistor using controlled polysilicon gate profile | |
US5923982A (en) | Method of making asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region using two source/drain implant steps | |
US6040220A (en) | Asymmetrical transistor formed from a gate conductor of unequal thickness | |
US6391728B1 (en) | Method of forming a highly localized halo profile to prevent punch-through | |
US7122862B2 (en) | Reduction of channel hot carrier effects in transistor devices | |
US5882974A (en) | High-performance PMOS transistor using a barrier implant in the source-side of the transistor channel | |
US6121631A (en) | Test structure to determine the effect of LDD length upon transistor performance | |
US5920103A (en) | Asymmetrical transistor having a gate dielectric which is substantially resistant to hot carrier injection | |
US6008100A (en) | Metal-oxide semiconductor field effect transistor device fabrication process | |
US6380021B1 (en) | Ultra-shallow junction formation by novel process sequence for PMOSFET |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
FPAY | Fee payment |
Year of fee payment: 12 |