US6366516B1 - Memory subsystem employing pool of refresh candidates - Google Patents
Memory subsystem employing pool of refresh candidates Download PDFInfo
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- US6366516B1 US6366516B1 US09/753,005 US75300500A US6366516B1 US 6366516 B1 US6366516 B1 US 6366516B1 US 75300500 A US75300500 A US 75300500A US 6366516 B1 US6366516 B1 US 6366516B1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
Definitions
- the present invention relates generally to the field of semiconductor memories; more particularly, to dynamic random-access memories (DRAMS) and memory architectures that provide for DRAM refresh operations.
- DRAMS dynamic random-access memories
- CPU central processor unit
- the main or system memory is typically implemented with DRAM devices.
- data is stored in a memory cell in the form of a capacitive charge that decays over time.
- periodic refreshing of the cell must occur in order to restore the charge level to its original, full capacity.
- the data is read and then rewritten back into the memory.
- explicit refresh cycles occur to specified memory address at the direction of the subsystem memory controller. Reading or writing data to an addressed location in memory is another way that memory cells can be refreshed.
- an explicit refresh cycle is called a primary refresh cycle. Refreshes that result from a read or write operation to a memory location are referred to as secondary refreshes.
- a single timer or a small set of timers controls primary refresh operations.
- the timer is set to an appropriate interval so as to insure that a refresh operation occurs before a known time it takes a DRAM cell to become completely discharged.
- a primary refresh cycle is posted for execution.
- a sequential timer or counter is used to generate the address for the primary refresh cycle.
- the primary refresh cycle with its address, is sent on to logic that either executes the cycle or posts it for later execution.
- An example of this latter approach is found in U.S. Pat. No. 5,907,857, which teaches refreshing dynamic memory in a burst that shifts memory refresh activity into periods of time in which the memory bus is relatively idle.
- U.S. Pat. No. 5,822,265 teaches a DRAM controller that performs a background refresh during times when the memory request input of the DRAM is idle after a measured time interval substantially less than the maximum refresh interval.
- U.S. Pat. No. 5,828,382 describes a method of interleaving refresh cycles to improve DRAM speed by reducing the time needed for a precharge sequence during a refresh cycle. The method involves grouping two or more consecutive refresh cycles, thereby effectively reducing precharge time per refresh operation.
- FIG. 1 is a conceptual diagram a system for generating and maintaining a pool of refresh candidates in accordance with the present invention.
- FIG. 2 is a circuit block diagram of a memory subsystem in accordance with one embodiment of the present invention.
- FIG. 3 is a detailed schematic diagram of a timer/detector circuit utilized in one embodiment of the present invention.
- the present invention is a method and apparatus that improves the utilization of the memory subsystem of a computer.
- numerous details are set forth, such as specific circuit configurations, circuit configurations, device types, etc., in order to provide a thorough understanding of the invention. It will be clear, however, to one skilled in the art, that these specific details may not be needed to practice the present invention.
- main memory is organized into an array of dynamic RAM memory cells that can be individually accessed by row and column addresses.
- Refreshes to DRAM can occur with either explicit refresh cycles (i.e., primary refreshes) or with reads and writes (i.e., secondary refreshes) to the same addresses.
- An important characteristic of a DRAM memory array is that when a row address is accessed or refreshed, all of the memory cells contained in that row have their stored charges restored to their original, full charge levels.
- the present invention it takes advantage of this characteristic by eliminating many primary refresh cycles, and only performing primary refresh cycles to only those rows in the memory that actually require to be refreshed.
- Primary refresh queue is a register stack structure that holds the collected row addresses candidates for refresh until they are sent to logic that handles the actual refresh cycle. This logic typically resides in the RAM controller of the memory subsystem.
- a key concept of the present invention is that primary refresh cycles are only performed to those locations that actually need to be refreshed. No primary refreshes are performed to locations that are read (or written) during the normal activity of the DRAM.
- primary refresh cycles are largely unnecessary since the information in the DRAM is constantly being restored (secondary refreshes) through read cycles used to display the stored image.
- the present invention takes advantage of this operational characteristic by scheduling for primary refresh only those memory location candidates that have actually suffered a loss of charge that exceeds a predetermined level.
- the memory subsystem of the present invention optimizes memory bandwidth performance by taking advantage of normally occurring read and write cycles that perform a secondary refresh function.
- the present invention is generic to any memory subsystem that relies upon dynamic memory devices.
- the present invention is equally applicable to computer systems utilizing external RAM, CPUs having internal RAM structures, main memory, graphics systems, video processing devices, etc.
- the invention shown in FIG. 1 may be implemented using an array of timers or counters for primary refresh cycles.
- a single timer would be associated with a single row of DRAM.
- Each timer would be set according to the known characteristic refresh time of the corresponding row within the dynamic RAM.
- the interval for each row is counted remotely by each timer, and the timer is reset every time a read, write or primary refresh is performed to the associated row address.
- the addresses for the primary refresh cycles are generated my candidate collector 12 .
- candidate collector 12 may perform this function periodically by searching the candidate pool and then scheduling the primary refresh cycle addresses by placing them into the primary refresh queue 13 . After the primary refresh cycle addresses are placed into the primary refresh queue 13 , they are removed (by resetting their timers) from the candidate pool.
- the primary refresh cycle timers may be implemented using ordinary logic devices.
- the timers may comprise a single bit storage device, several bit counters, or standard analog circuits having known decay times.
- the primary refresh cycle timers may also be implemented in a static RAM (SRAM) array, with the bits are read out, aged, and then written back into the SRAM. Since the granularity of the timer affects the algorithm for collecting and scheduling refreshes, the implementation choice for the timer function may be dependent on the particular memory system application.
- SRAM static RAM
- Node 32 is also connected to one input of comparator 34 .
- the other input of comparator 34 is set to a voltage determined by the resistor divider network comprising resistors R 1 and R 2 , coupled in series between V cc and ground. Together, the resistor divider network and comparator 34 comprise threshold detector 33 .
- the charge threshold level is simply set by the values of R 1 and R 2 .
- Threshold detected 33 simply monitors the charge present on the storage cell. When the charge at node 32 drops below the predetermined threshold level, comparator 34 outputs a refresh request signal causing a primary refresh cycle request to be placed in the refresh pool.
- the additional storage cells 21 are manufactured identical to the RAM cells in each row 20 of the array, their physical characteristics are the same. This means that when the charge level of the additional storage cell 21 has decayed below the threshold level, all of the cells in the associated row 20 need to be refreshed.
- Refresh pool collector 24 may be implemented using a variety of well known structures.
- a collector 24 may be implemented as a standard first-in-first-out (FIFO) stack register.
- refresh pool collector 24 may include logic that prioritizes the collected refresh requests. Such a priority-ordering scheme would assign a higher priority to requests exceeding a Critical charge decay level, and a lower priority to rows that have exceeded a Request charge decay level (above the Critical level). Critical level requests are delivered first, followed by any Request level requests. Distinguishing between a Request threshold level and a Critical threshold level may be accomplished using additional detector structures or additional ordinary logic. Priority row ordering would have the salutary benefit of insuring that no cells are ever completely discharged, as might occur without such a scheme in cases where the subsystem is backed up with numerous refresh cycles.
- Refresh request generator 25 receives as an input the addresses of the rows 20 of the DRAM that need a refresh cycle. Basically, generator 25 comprises a FIFO structure that sends the refresh cycle requests to the RAM controller 26 , which handles the actual refresh cycle. In the diagram of FIG. 2, read, write, and refresh requests are transmitted by RAM controller 26 to DRAM via lines 27 . These three types of request transmissions are basically used to enable charge switch 31 in the circuit of FIG. 3 .
- FIG. 4 is a timing waveform diagram illustrating the operation of one embodiment of the present invention.
- the “sawtooth” right triangles of the waveform represent the charge levels of various rows within the DRAM of the memory subsystem. As can be seen, charge levels decay over time (moving from left to right). The rate of charge loss of a particular row is denoted by the hypotenuse of a given triangle. For instance, the triangle shown between time t 0 and time t 1 illustrates the steady leakage of charge for a particular DRAM row. This row is recharged to the fully charged level at time t 1 as a result of a secondary refresh cycle, i.e., a read or write cycle. Note that the vertical side of each triangle denotes the refreshing of charge to the designated row. This charge restoration may result from a read, write or refresh cycle. The charge level of a particular row is restored to the Fully Charged Level at each of times t 1 -t 12 shown in FIG. 4 .
- the two triangles shown between times t 3 and t 5 represent rows that are refreshed through explicit refresh cycles. This is evident from the fact that the charge level of both of these rows decays past the Request Level threshold, which event may be detected by the threshold detector block 23 . Note that if the charge level of these particular rows dropped below the Critical Level, they would receive priority status for refreshing, as described above.
- FIG. 4 illustrates how the present invention achieves a substantial improvement in memory bandwidth performance over the prior art. During the entire time interval shown, only two primary refresh cycles needed to be performed. Again, this improvement in memory bandwidth performance is realized by taking advantage of normal read/write activity to the dynamic RAM in accordance with the present invention.
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US09/753,005 US6366516B1 (en) | 2000-12-29 | 2000-12-29 | Memory subsystem employing pool of refresh candidates |
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US09/753,005 US6366516B1 (en) | 2000-12-29 | 2000-12-29 | Memory subsystem employing pool of refresh candidates |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040196702A1 (en) * | 2003-04-04 | 2004-10-07 | Infineon Technologies North America Corp. | Use of redundant memory cells to manufacture cost efficient drams with reduced self refresh current capability |
JP2014524098A (en) * | 2011-06-30 | 2014-09-18 | シリコン イメージ,インコーポレイテッド | Mechanism for facilitating fine-grained self-refresh control of dynamic memory devices |
Citations (10)
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US4982369A (en) * | 1986-11-07 | 1991-01-01 | Fujitsu Limited | Self-refresh semiconductor memory device responsive to a refresh request signal |
US5768193A (en) * | 1996-06-17 | 1998-06-16 | Aplus Integrated Circuits, Inc. | Bit-refreshable method and circuit for refreshing a nonvolatile flash memory |
US5774404A (en) | 1994-10-21 | 1998-06-30 | Fujitsu Limited | Semiconductor memory having self-refresh function |
US5796992A (en) | 1995-12-20 | 1998-08-18 | Compaq Computer Corporation | Circuit for switching between synchronous and asynchronous memory refresh cycles in low power mode |
US5822266A (en) | 1996-05-21 | 1998-10-13 | Elonex Plc | Apparatus and method for minimizing DRAM recharge time |
US5822265A (en) | 1997-07-29 | 1998-10-13 | Rockwell Semiconductor Systems, Inc. | DRAM controller with background refresh |
US5907857A (en) | 1997-04-07 | 1999-05-25 | Opti, Inc. | Refresh-ahead and burst refresh preemption technique for managing DRAM in computer system |
US5956281A (en) * | 1997-09-12 | 1999-09-21 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device capable of setting substrate voltage shallow in disturb test mode and self refresh mode |
US5999474A (en) | 1998-10-01 | 1999-12-07 | Monolithic System Tech Inc | Method and apparatus for complete hiding of the refresh of a semiconductor memory |
US6118719A (en) | 1998-05-20 | 2000-09-12 | International Business Machines Corporation | Self-initiated self-refresh mode for memory modules |
-
2000
- 2000-12-29 US US09/753,005 patent/US6366516B1/en not_active Expired - Lifetime
Patent Citations (10)
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US4982369A (en) * | 1986-11-07 | 1991-01-01 | Fujitsu Limited | Self-refresh semiconductor memory device responsive to a refresh request signal |
US5774404A (en) | 1994-10-21 | 1998-06-30 | Fujitsu Limited | Semiconductor memory having self-refresh function |
US5796992A (en) | 1995-12-20 | 1998-08-18 | Compaq Computer Corporation | Circuit for switching between synchronous and asynchronous memory refresh cycles in low power mode |
US5822266A (en) | 1996-05-21 | 1998-10-13 | Elonex Plc | Apparatus and method for minimizing DRAM recharge time |
US5768193A (en) * | 1996-06-17 | 1998-06-16 | Aplus Integrated Circuits, Inc. | Bit-refreshable method and circuit for refreshing a nonvolatile flash memory |
US5907857A (en) | 1997-04-07 | 1999-05-25 | Opti, Inc. | Refresh-ahead and burst refresh preemption technique for managing DRAM in computer system |
US5822265A (en) | 1997-07-29 | 1998-10-13 | Rockwell Semiconductor Systems, Inc. | DRAM controller with background refresh |
US5956281A (en) * | 1997-09-12 | 1999-09-21 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device capable of setting substrate voltage shallow in disturb test mode and self refresh mode |
US6118719A (en) | 1998-05-20 | 2000-09-12 | International Business Machines Corporation | Self-initiated self-refresh mode for memory modules |
US5999474A (en) | 1998-10-01 | 1999-12-07 | Monolithic System Tech Inc | Method and apparatus for complete hiding of the refresh of a semiconductor memory |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040196702A1 (en) * | 2003-04-04 | 2004-10-07 | Infineon Technologies North America Corp. | Use of redundant memory cells to manufacture cost efficient drams with reduced self refresh current capability |
US6847571B2 (en) * | 2003-04-04 | 2005-01-25 | Infineon Technologies Ag | Use of redundant memory cells to manufacture cost efficient drams with reduced self refresh current capability |
DE102004016702B4 (en) * | 2003-04-04 | 2010-01-28 | Qimonda Ag | Dynamic Random Access Reduced Self-Refreshment Memory and Method for Refreshing Dynamic Random Access Memory |
JP2014524098A (en) * | 2011-06-30 | 2014-09-18 | シリコン イメージ,インコーポレイテッド | Mechanism for facilitating fine-grained self-refresh control of dynamic memory devices |
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