US6366524B1 - Address decoding in multiple-bank memory architectures - Google Patents
Address decoding in multiple-bank memory architectures Download PDFInfo
- Publication number
- US6366524B1 US6366524B1 US09/628,197 US62819700A US6366524B1 US 6366524 B1 US6366524 B1 US 6366524B1 US 62819700 A US62819700 A US 62819700A US 6366524 B1 US6366524 B1 US 6366524B1
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- Prior art keywords
- address
- coupled
- decoder
- input
- bank
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/06—Address interface arrangements, e.g. address buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
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Abstract
Description
Claims (40)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/628,197 US6366524B1 (en) | 2000-07-28 | 2000-07-28 | Address decoding in multiple-bank memory architectures |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/628,197 US6366524B1 (en) | 2000-07-28 | 2000-07-28 | Address decoding in multiple-bank memory architectures |
Publications (1)
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US6366524B1 true US6366524B1 (en) | 2002-04-02 |
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Family Applications (1)
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US09/628,197 Expired - Lifetime US6366524B1 (en) | 2000-07-28 | 2000-07-28 | Address decoding in multiple-bank memory architectures |
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US (1) | US6366524B1 (en) |
Cited By (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6449674B1 (en) * | 1998-12-24 | 2002-09-10 | Hyundai Electronics Industries Co., Ltd. | Internal command signal generator and method therefor |
US20030233511A1 (en) * | 2002-03-20 | 2003-12-18 | Seiko Epson Corporation | Data transfer device and method for multidimensional memory |
US6721227B2 (en) * | 2002-02-11 | 2004-04-13 | Micron Technology, Inc. | User selectable banks for DRAM |
US6747898B2 (en) | 2002-07-08 | 2004-06-08 | Micron Technology, Inc. | Column decode circuit for high density/high performance memories |
US20040119520A1 (en) * | 2002-12-21 | 2004-06-24 | Bae Seung Cheol | Setup/hold time control device |
US6888777B2 (en) * | 2002-08-27 | 2005-05-03 | Intel Corporation | Address decode |
US20060050591A1 (en) * | 2004-09-09 | 2006-03-09 | Samsung Electronics Co., Ltd. | Address coding method and address decoder for reducing sensing noise during refresh operation of memory device |
US20100238748A1 (en) * | 2007-09-03 | 2010-09-23 | Dong-Keun Kim | Semiconductor memory device |
US20120188839A1 (en) * | 2011-01-26 | 2012-07-26 | Jeong-Tae Hwang | Bank selection circuit and memory device having the same |
CN104025196A (en) * | 2011-08-12 | 2014-09-03 | Gsi技术有限公司 | Systems and methods involving multi-bank, dual- or multi-pipe srams |
US20150332743A1 (en) * | 2014-05-14 | 2015-11-19 | SK Hynix Inc. | Semiconductor memory device |
US9935750B2 (en) | 2010-08-26 | 2018-04-03 | Qualcomm Incorporated | Single stream phase tracking during channel estimation in a very high throughput wireless MIMO communication system |
US10521229B2 (en) | 2016-12-06 | 2019-12-31 | Gsi Technology, Inc. | Computational memory cell and processing array device using memory cells |
CN110875067A (en) * | 2018-08-29 | 2020-03-10 | 三星电子株式会社 | Method and system for performing decoding in finfet-based memory |
US10770133B1 (en) | 2016-12-06 | 2020-09-08 | Gsi Technology, Inc. | Read and write data processing circuits and methods associated with computational memory cells that provides write inhibits and read bit line pre-charge inhibits |
US10777262B1 (en) | 2016-12-06 | 2020-09-15 | Gsi Technology, Inc. | Read data processing circuits and methods associated memory cells |
US10847212B1 (en) | 2016-12-06 | 2020-11-24 | Gsi Technology, Inc. | Read and write data processing circuits and methods associated with computational memory cells using two read multiplexers |
US10847213B1 (en) | 2016-12-06 | 2020-11-24 | Gsi Technology, Inc. | Write data processing circuits and methods associated with computational memory cells |
US10854284B1 (en) | 2016-12-06 | 2020-12-01 | Gsi Technology, Inc. | Computational memory cell and processing array device with ratioless write port |
US10860320B1 (en) | 2016-12-06 | 2020-12-08 | Gsi Technology, Inc. | Orthogonal data transposition system and method during data transfers to/from a processing array |
US10877731B1 (en) | 2019-06-18 | 2020-12-29 | Gsi Technology, Inc. | Processing array device that performs one cycle full adder operation and bit line read/write logic features |
US10891076B1 (en) | 2016-12-06 | 2021-01-12 | Gsi Technology, Inc. | Results processing circuits and methods associated with computational memory cells |
US10930341B1 (en) | 2019-06-18 | 2021-02-23 | Gsi Technology, Inc. | Processing array device that performs one cycle full adder operation and bit line read/write logic features |
US10943648B1 (en) | 2016-12-06 | 2021-03-09 | Gsi Technology, Inc. | Ultra low VDD memory cell with ratioless write port |
US10958272B2 (en) | 2019-06-18 | 2021-03-23 | Gsi Technology, Inc. | Computational memory cell and processing array device using complementary exclusive or memory cells |
US10998040B2 (en) | 2016-12-06 | 2021-05-04 | Gsi Technology, Inc. | Computational memory cell and processing array device using the memory cells for XOR and XNOR computations |
US11227653B1 (en) | 2016-12-06 | 2022-01-18 | Gsi Technology, Inc. | Storage array circuits and methods for computational memory cells |
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US5041886A (en) | 1989-08-17 | 1991-08-20 | Samsung Electronics Co., Ltd. | Nonvolatile semiconductor memory device and manufacturing method thereof |
US5202823A (en) * | 1990-03-29 | 1993-04-13 | Nec Corporation | Semiconductor memory device having signal receiving facility fabricated from bi-cmos circuits |
US5295115A (en) * | 1991-09-17 | 1994-03-15 | Nec Corporation | Addressing system free from multi-selection of word lines |
US5537354A (en) | 1993-12-15 | 1996-07-16 | Fujitsu Limited | Semiconductor memory device and method of forming the same |
US5600605A (en) | 1995-06-07 | 1997-02-04 | Micron Technology, Inc. | Auto-activate on synchronous dynamic random access memory |
US5666321A (en) | 1995-09-01 | 1997-09-09 | Micron Technology, Inc. | Synchronous DRAM memory with asynchronous column decode |
US5748557A (en) * | 1995-12-27 | 1998-05-05 | Samsung Electronics Co., Ltd. | Address buffer for high-speed address inputting |
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US5950219A (en) * | 1996-05-02 | 1999-09-07 | Cirrus Logic, Inc. | Memory banks with pipelined addressing and priority acknowledging and systems and methods using the same |
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2000
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US5041886A (en) | 1989-08-17 | 1991-08-20 | Samsung Electronics Co., Ltd. | Nonvolatile semiconductor memory device and manufacturing method thereof |
US5202823A (en) * | 1990-03-29 | 1993-04-13 | Nec Corporation | Semiconductor memory device having signal receiving facility fabricated from bi-cmos circuits |
US5295115A (en) * | 1991-09-17 | 1994-03-15 | Nec Corporation | Addressing system free from multi-selection of word lines |
US5537354A (en) | 1993-12-15 | 1996-07-16 | Fujitsu Limited | Semiconductor memory device and method of forming the same |
US6026465A (en) | 1994-06-03 | 2000-02-15 | Intel Corporation | Flash memory including a mode register for indicating synchronous or asynchronous mode of operation |
US5751039A (en) | 1995-05-19 | 1998-05-12 | Micron Technology, Inc. | Programmable non-volatile memory cell and method of forming a non-volatile memory cell |
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US5600605A (en) | 1995-06-07 | 1997-02-04 | Micron Technology, Inc. | Auto-activate on synchronous dynamic random access memory |
US5666321A (en) | 1995-09-01 | 1997-09-09 | Micron Technology, Inc. | Synchronous DRAM memory with asynchronous column decode |
US5748557A (en) * | 1995-12-27 | 1998-05-05 | Samsung Electronics Co., Ltd. | Address buffer for high-speed address inputting |
US5950219A (en) * | 1996-05-02 | 1999-09-07 | Cirrus Logic, Inc. | Memory banks with pipelined addressing and priority acknowledging and systems and methods using the same |
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US5936903A (en) | 1997-02-26 | 1999-08-10 | Powerchip Semiconductor Corp. | Synchronous semiconductor memory device |
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Cited By (54)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6449674B1 (en) * | 1998-12-24 | 2002-09-10 | Hyundai Electronics Industries Co., Ltd. | Internal command signal generator and method therefor |
US6721227B2 (en) * | 2002-02-11 | 2004-04-13 | Micron Technology, Inc. | User selectable banks for DRAM |
US20100097878A1 (en) * | 2002-02-11 | 2010-04-22 | Micron Technology, Inc. | User selectable banks for dram |
US7636271B2 (en) | 2002-02-11 | 2009-12-22 | Micron Technology, Inc. | User selectable banks for DRAM |
US20040165468A1 (en) * | 2002-02-11 | 2004-08-26 | Micron Technology, Inc. | User selectable banks for dram |
US20070242551A1 (en) * | 2002-02-11 | 2007-10-18 | Micron Technology, Inc. | User selectable banks for DRAM |
US7203122B2 (en) | 2002-02-11 | 2007-04-10 | Micron Technology, Inc. | User selectable banks for DRAM |
US7995420B2 (en) | 2002-02-11 | 2011-08-09 | Round Rock Research, Llc | User selectable banks for DRAM |
US20030233511A1 (en) * | 2002-03-20 | 2003-12-18 | Seiko Epson Corporation | Data transfer device and method for multidimensional memory |
US7096312B2 (en) * | 2002-03-20 | 2006-08-22 | Seiko Epson Corporation | Data transfer device and method for multidimensional memory |
US6747898B2 (en) | 2002-07-08 | 2004-06-08 | Micron Technology, Inc. | Column decode circuit for high density/high performance memories |
US6888777B2 (en) * | 2002-08-27 | 2005-05-03 | Intel Corporation | Address decode |
US6924685B2 (en) | 2002-12-21 | 2005-08-02 | Hynix Semiconductor, Inc. | Device for controlling a setup/hold time of an input signal |
US20040119520A1 (en) * | 2002-12-21 | 2004-06-24 | Bae Seung Cheol | Setup/hold time control device |
US7180816B2 (en) * | 2004-09-09 | 2007-02-20 | Samsung Electronics Co., Ltd. | Address coding method and address decoder for reducing sensing noise during refresh operation of memory device |
US20060050591A1 (en) * | 2004-09-09 | 2006-03-09 | Samsung Electronics Co., Ltd. | Address coding method and address decoder for reducing sensing noise during refresh operation of memory device |
US20100238748A1 (en) * | 2007-09-03 | 2010-09-23 | Dong-Keun Kim | Semiconductor memory device |
US7894295B2 (en) * | 2007-09-03 | 2011-02-22 | Hynix Semiconductor Inc. | Semiconductor memory device |
US9935750B2 (en) | 2010-08-26 | 2018-04-03 | Qualcomm Incorporated | Single stream phase tracking during channel estimation in a very high throughput wireless MIMO communication system |
US20120188839A1 (en) * | 2011-01-26 | 2012-07-26 | Jeong-Tae Hwang | Bank selection circuit and memory device having the same |
US8958262B2 (en) * | 2011-01-26 | 2015-02-17 | Hynix Semiconductor Inc. | Bank selection circuit and memory device having the same |
CN104025196B (en) * | 2011-08-12 | 2017-05-03 | Gsi技术有限公司 | Systems And Methods Involving Multi-Bank, Dual- Or Multi-Pipe SRAMs |
US9196324B2 (en) | 2011-08-12 | 2015-11-24 | Gsi Technology, Inc. | Systems and methods involving multi-bank, dual- or multi-pipe SRAMs |
US8982649B2 (en) | 2011-08-12 | 2015-03-17 | Gsi Technology, Inc. | Systems and methods involving multi-bank, dual- or multi-pipe SRAMs |
US9679631B2 (en) | 2011-08-12 | 2017-06-13 | Gsi Technology, Inc. | Systems and methods involving multi-bank, dual- or multi-pipe SRAMs |
CN104025196A (en) * | 2011-08-12 | 2014-09-03 | Gsi技术有限公司 | Systems and methods involving multi-bank, dual- or multi-pipe srams |
US20150332743A1 (en) * | 2014-05-14 | 2015-11-19 | SK Hynix Inc. | Semiconductor memory device |
US9589641B2 (en) * | 2014-05-14 | 2017-03-07 | SK Hynix Inc. | Semiconductor memory device |
US11150903B2 (en) | 2016-12-06 | 2021-10-19 | Gsi Technology, Inc. | Computational memory cell and processing array device using memory cells |
US11194519B2 (en) | 2016-12-06 | 2021-12-07 | Gsi Technology, Inc. | Results processing circuits and methods associated with computational memory cells |
US11763881B2 (en) | 2016-12-06 | 2023-09-19 | Gsi Technology, Inc. | Computational memory cell and processing array device using the memory cells for XOR and XNOR computations |
US10725777B2 (en) | 2016-12-06 | 2020-07-28 | Gsi Technology, Inc. | Computational memory cell and processing array device using memory cells |
US10770133B1 (en) | 2016-12-06 | 2020-09-08 | Gsi Technology, Inc. | Read and write data processing circuits and methods associated with computational memory cells that provides write inhibits and read bit line pre-charge inhibits |
US10777262B1 (en) | 2016-12-06 | 2020-09-15 | Gsi Technology, Inc. | Read data processing circuits and methods associated memory cells |
US10847212B1 (en) | 2016-12-06 | 2020-11-24 | Gsi Technology, Inc. | Read and write data processing circuits and methods associated with computational memory cells using two read multiplexers |
US10847213B1 (en) | 2016-12-06 | 2020-11-24 | Gsi Technology, Inc. | Write data processing circuits and methods associated with computational memory cells |
US10854284B1 (en) | 2016-12-06 | 2020-12-01 | Gsi Technology, Inc. | Computational memory cell and processing array device with ratioless write port |
US10860320B1 (en) | 2016-12-06 | 2020-12-08 | Gsi Technology, Inc. | Orthogonal data transposition system and method during data transfers to/from a processing array |
US10860318B2 (en) | 2016-12-06 | 2020-12-08 | Gsi Technology, Inc. | Computational memory cell and processing array device using memory cells |
US11409528B2 (en) | 2016-12-06 | 2022-08-09 | Gsi Technology, Inc. | Orthogonal data transposition system and method during data transfers to/from a processing array |
US10891076B1 (en) | 2016-12-06 | 2021-01-12 | Gsi Technology, Inc. | Results processing circuits and methods associated with computational memory cells |
US11257540B2 (en) | 2016-12-06 | 2022-02-22 | Gsi Technology, Inc. | Write data processing methods associated with computational memory cells |
US10943648B1 (en) | 2016-12-06 | 2021-03-09 | Gsi Technology, Inc. | Ultra low VDD memory cell with ratioless write port |
US11227653B1 (en) | 2016-12-06 | 2022-01-18 | Gsi Technology, Inc. | Storage array circuits and methods for computational memory cells |
US10998040B2 (en) | 2016-12-06 | 2021-05-04 | Gsi Technology, Inc. | Computational memory cell and processing array device using the memory cells for XOR and XNOR computations |
US11094374B1 (en) | 2016-12-06 | 2021-08-17 | Gsi Technology, Inc. | Write data processing circuits and methods associated with computational memory cells |
US10521229B2 (en) | 2016-12-06 | 2019-12-31 | Gsi Technology, Inc. | Computational memory cell and processing array device using memory cells |
US11205476B1 (en) | 2016-12-06 | 2021-12-21 | Gsi Technology, Inc. | Read data processing circuits and methods associated with computational memory cells |
CN110875067A (en) * | 2018-08-29 | 2020-03-10 | 三星电子株式会社 | Method and system for performing decoding in finfet-based memory |
US10672443B2 (en) * | 2018-08-29 | 2020-06-02 | Samsung Electronics Co., Ltd. | Methods and systems for performing decoding in finFET based memories |
US11194548B2 (en) | 2019-06-18 | 2021-12-07 | Gsi Technology, Inc. | Processing array device that performs one cycle full adder operation and bit line read/write logic features |
US10958272B2 (en) | 2019-06-18 | 2021-03-23 | Gsi Technology, Inc. | Computational memory cell and processing array device using complementary exclusive or memory cells |
US10930341B1 (en) | 2019-06-18 | 2021-02-23 | Gsi Technology, Inc. | Processing array device that performs one cycle full adder operation and bit line read/write logic features |
US10877731B1 (en) | 2019-06-18 | 2020-12-29 | Gsi Technology, Inc. | Processing array device that performs one cycle full adder operation and bit line read/write logic features |
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