US6385091B1 - Read reference scheme for non-volatile memory - Google Patents
Read reference scheme for non-volatile memory Download PDFInfo
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- US6385091B1 US6385091B1 US09/846,936 US84693601A US6385091B1 US 6385091 B1 US6385091 B1 US 6385091B1 US 84693601 A US84693601 A US 84693601A US 6385091 B1 US6385091 B1 US 6385091B1
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- word line
- voltage
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- read
- memory cell
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
Definitions
- the present invention relates generally to non-volatile memories and in particular the present invention relates to a read reference scheme using current load matching on the reference word line path.
- a flash memory is a non-volatile memory. That is, a flash memory is a type of memory that retains data when its power source is removed.
- a typical flash memory comprises a memory array divided up into individually erasable sections or blocks of memory cells. The memory cells are arranged in a row and column fashion. Each memory cell includes a floating gate field-effect transistor capable of holding a charge. Moreover, each memory cell can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by an erase operation. Thus, the data in a cell is determined by the presence or absence of the charge in the floating gate.
- a high positive voltage such as 12 volts is applied to the control gate of the cell.
- a moderate positive voltage such as 6 to 9 volts is applied to the drain while the source voltage and the substrate voltage are at ground level.
- a block or section of memory cells is erased by putting a negative voltage on the word lines of an entire block and coupling the source connection of the entire block to Vcc (power supply), or higher. This creates a field that removes electrons from the floating gates of the memory elements.
- the memory cells can be activated using a lower control gate voltage.
- An erased non-volatile memory cell is said to be at a logic level of “1”.
- Verification of a non-volatile memory cell is accomplished by applying a potential to the control gate of the memory cell to be verified and then using a current sensing circuit or sense amplifier circuit to compare a current generated by the memory cell with a known current from a reference memory cell.
- the reference memory cell is generally a non-volatile memory cell or bit that has a predefined charge that is set or trimmed by the manufacture of the memory to produce a specific reference current.
- the reference cell is typically programmed to an intermediate state such that it conducts about half the current conducted by a fully programmed memory cell when an equivalent voltage level is applied to the control gates of the respective memory being read and reference memory cell.
- the reference memory cell is coupled to the sense amplifier circuit by a reference bit line line.
- the memory cell that is being read is coupled to the sense amplifier circuit by a memory cell bit line.
- a supply voltage is applied to a word line that is coupled to the control gate of the memory cell.
- the same supply voltage is applied to a reference word line that is coupled to a control gate of the reference cell.
- the sense amplifier circuit determines whether the memory cell to be read or verified draws more or less current than the reference current. By doing this, the sense amplifier circuit determines if the memory cell is in a programmed state or an erased state.
- a problem can occur in the prior art when differing current levels are drawn in a path between a voltage pump and word line verses a path between the voltage pump and the reference word line during a read or verify operation. A larger voltage drop from the supply voltage will occur in the path with the highest current load. This may cause a differential voltage to exist between the respective paths. Moreover, the differential may result in a reduction in the margin of current difference between the memory cell and the reference memory cell, which could reduce the accuracy of the sense amplifier circuit.
- a flash memory device comprising, a word line, a reference word line and a reference load circuit.
- the word line is coupled to a control gate of a memory cell.
- the reference word line is coupled to a control gate of a reference memory cell.
- the reference load circuit is coupled to the reference word line to approximately match a current load on the word line so the voltage level of the reference word line will be approximately equally to the voltage level on the word line during a read operation.
- a flash memory device comprises, a voltage pump, a non-volatile memory cell having a control gate, a x-decoder circuit, a word line, a non-volatile reference memory cell having a control gate, a reference word line and a reference load.
- the voltage pump is used to supply a read voltage.
- the word line is coupled to the control gate of the memory cell.
- the x-decoder circuit is used to selectively couple the voltage pump to the word line during a read operation of the memory cell.
- the reference word line is coupled between the voltage pump and a control gate of the reference memory cell.
- the reference load circuit is coupled to the reference word line to provide a current load that approximately matches a current load of the x-decoder circuit.
- a non-volatile memory device comprises, a memory array, a voltage read pump, a x-decoder circuit, a non-volatile reference memory cell, a reference word line, a reference load circuit and a current sensing circuit.
- the memory array has a plurality of sectors of non-volatile memory cells arranged in columns and rows.
- the voltage read pump is used to supply a read voltage supply.
- the x-decoder circuit selectively couples an output of the voltage read pump to an addressed word line during a read operation.
- the word line is coupled to a control gate of a selected memory cell.
- the reference word line is coupled between the voltage read pump and a control gate of the reference memory cell.
- the reference load circuit is coupled to the reference word line to provide a current load that approximately matches a current load of the x-decoder circuit during the read operation.
- the current sensing circuit is used to compare currents in an array bit line coupled to the selected memory cell with a reference bit line coupled to the reference memory cell.
- a non-volatile memory system in another embodiment, includes an external processor, a memory array, control circuitry, a plurality of word lines, a voltage read pump, a x-decode circuit, a reference memory cell, a reference word line, a reference load circuit and a current sensing circuit.
- the external processor provides external read commands.
- the memory array has a plurality of array sectors. Each array sector has a plurality of memory cells.
- the control circuitry is used to control read operations to the memory array. Moreover, the control circuitry is coupled to receive the external read commands from the external processor.
- the plurality of word lines are coupled to activate the memory cells in the array sectors. Moreover, each word line is coupled to a control gate of an associated memory cell.
- the voltage read pump is used to supply a read voltage.
- the x-decode circuit is used to selectively couple the read voltage to a word line of an addressed memory cell.
- the x-decode requires a current (Idecode) during a read operation.
- the reference memory cell provides a reference current.
- the reference word line is coupled between a control gate of the reference memory cell and the voltage read pump.
- the reference load circuit is coupled to the reference word line to provide a current load (Iload). Current Iload is approximately equal to Idecode.
- the current sensing circuit is used to compare currents in an array bit line coupled to the addressed memory cell with a current in a reference bit line coupled to the reference memory cell to determine the programmed state of the addressed memory cell.
- a method of operating a flash memory during a read operation comprising, coupling a read voltage to a word line, wherein the word line is coupled to a control gate of a non-volatile memory cell to be read, coupling the read voltage to a reference word line, wherein the reference word line is coupled to a control gate of a reference memory cell and coupling a current load to the reference word line to approximately match a current load on the word line.
- a method of operating a non-volatile memory comprising, coupling a read voltage to an x-decoder circuit to enable the x-decoder circuit to select an addressed word line during a read operation, coupling the read voltage to a reference word line and coupling a reference load circuit to the reference word line to approximately match a current draw through the x-decoder circuit during a read operation.
- a method of operating a flash memory comprising, coupling a first voltage to a plurality of switch circuits during a read operation, outputting a second voltage from one of the switch circuits to an internal data line in response to the first voltage, wherein the switch circuit is a switch circuit coupled to an array sector having a memory cell that is addressed to be read, activating a row driver circuit coupled to the internal data line with the second voltage, wherein the row driver circuit outputs a cell access voltage to a word line coupled to a control gate of the memory cell that is addressed to be read to activate the memory cell, activating a reference load circuit coupled to a pre-selected internal data line having the second voltage coupled thereon, wherein the reference load circuit produces a predetermined current load that approximately matches a current load of the row driver circuit, coupling the pre-selected internal data line to a reference word line coupled to a control gate of a reference cell, wherein a reference access voltage is coupled to the reference word line to activate the reference cell and sensing
- FIG. 2 is a block diagram of a read path in the prior art
- FIG. 3 is a schematic-block diagram of a row driver circuit of the prior art
- FIG. 4 is block diagram illustrating how a memory cell is read in the prior art
- FIG. 5 is block diagram of a read path of one embodiment of the present invention.
- FIG. 6 is schematic-block diagram of one embodiment of the reference load circuit of the present invention.
- FIG. 8 is a schematic diagram of one embodiment of the current load circuit of the present invention.
- the present invention addresses a read reference scheme that improves reliability of a memory device in sensing the difference between a programmed bit and an erased bit. More specifically, the present invention approximately matches a current load in an array word line path during a read operation with the use of a reference load circuit coupled to a reference word line. Prior to describing the reference load circuit, a general description of one embodiment of the flash memory device of the present invention is described.
- the flash memory device 100 includes a memory array 102 .
- the memory array 102 is made of non-volatile memory cells (cells) that are arranged in sectors.
- the flash memory device 100 also includes control circuitry 104 to control read, erase and other memory operation of the memory array 102 .
- the control circuitry is coupled to an external processor 200 for operation and testing.
- Address lines (A 0 -Ax) 106 couple the external processor 200 to an address buffer/latch 110 .
- the Address buffer/latch is coupled to an x-decoder circuit 114 and a y-decoder circuit 118 .
- an address counter 112 is couple between the control circuitry 104 and the x-decoder circuit 114 and the y-decoder circuit 118 .
- a sense amplifier circuit 116 is coupled to memory array 102 to read accessed cells.
- Data lines (DQ 0 -DQx) 108 couple the sense amplifier circuit 116 to the external processor 200 .
- a voltage read pump 120 to provide a read voltage and a voltage read regulator 122 to regulate the voltage to a predetermined value.
- a typical voltage value from the voltage read regulator is approximately 4.2 volts.
- the voltage pump or voltage read pump 120 supplies a voltage to the voltage read regulator 122 .
- An output of the voltage read regulator 122 is the read voltage or Vread voltage.
- This voltage is coupled to a plurality of switch circuits 130 in the x-decoder circuit 114 .
- the switch circuits 130 output a word line voltage Vx ( 1 - 33 ) to be received by their associated array sector 150 .
- the associated switch circuit 130 For example during a read operation on a selected array sector 150 , its associated switch circuit 130 outputs a positive word line voltage Vx on an internal data line 132 to access a selected cell. Moreover, during an erase operation of an array sector 150 , the output of its associated switch circuit 130 will be at ground.
- the word line voltage Vx for one array sector 150 can be different from another array sector 150 so different operations (i.e. read or erase) can be performed on different array sectors 150 simultaneously.
- Each row driver circuit 140 receives the word line voltage Vx from an associated switch circuit 130 .
- a row driver circuit 140 is illustrated.
- each row driver circuit 140 contains a row driver 172 for each word line WL and a decode matrix circuit 170 .
- each array sector 150 has one hundred twenty eight word lines WL.
- each row driver circuit 140 has one hundred twenty eight row drivers 172 .
- the decode matrix code circuit 170 includes a tree matrix of decodes that point to a word line WL that has be selected.
- the decode matrix circuit 170 draws an active current (Idecode) from an interior data line 132 having voltage Vx, in pointing to the word line WL selected.
- only one word line WL per array sector 150 is pointed to or selected by the decode matrix circuit 170 at a time.
- an active low logic signal is applied to p-channel transistor 174 .
- the active current Iload then activates the decode matrix circuit 170 .
- the decode matrix circuit 170 then sends an active low logic signal to the row driver 172 associated with the word line WL selected.
- An activation voltage is then applied to the word line WL selected, to activate the selected cell.
- the activation voltage can be referred to as the cell access voltage. Since, decode matrix circuits 170 are common in the art, a detailed description of their operation is not provide herein.
- the memory array 102 is shown having a reference array sector 160 .
- the reference array sector 160 is sometime referred to as a “mini” array and is where a reference cell is located.
- voltage Vread from the voltage read regulator, is coupled to the reference word line (REFWL) to activate a reference memory cell.
- REFWL reference word line
- FIG. 4 a simplified illustration of the memory array 102 having a cell 152 to be read and the sense amplifier circuit 116 having a sense amplifier 117 is shown of the prior art.
- FIG. 4 illustrates how a cell 152 in an array sector 150 is read. Voltage Vx is applied to a control gate of cell 152 to activate cell 152 .
- the cell access voltage is applied to the control gate of the cell to be read. This accounts for the current drain by the row driver circuit 140 on the interior data line 132 .
- voltage Vread is applied to a control gate of reference cell 162 at the same time to activated the reference cell 162 .
- the sense amplifier 117 in the sense amplifier circuit 116 compares current in a reference bit line 164 created by the reference cell 162 with current in a array bit line 154 from the selected cell 152 in determining the program state of the cell 152 . The greater the margin of difference between the reference bit line 164 and the array bit line 154 , the more accurate the output of the sense amplifier 117 .
- the reference load circuit 300 is coupled between a pre-selected interior data line 134 having voltage Vx( 19 ) and the reference word line REFWL.
- the pre-selected interior data line 134 with voltage Vx( 19 ) is used because, in this embodiment, array sector ( 19 ) 150 is the array sector 150 that is the closest to the reference array sector 160 . That is, the pre-selected interior data line 134 with the voltage Vx( 19 ) is used because of its location.
- the reference load circuit 300 could be coupled to any of the interior data lines with a voltage signal of Vx and that the present invention is not limited to coupling the reference load circuit 300 to the pre-selected interior data line 134 with the voltage Vx( 19 ).
- the present invention is illustrated with thirty three switch circuits 130 , thirty three row driver circuits 140 , thirty three array sectors 150 and 128 word lines WL for each array sector 150 , other amounts of switch circuits 130 , row drivers circuits 140 , array sectors and word lines WL could be used and that the present invention is not limited to the aforementioned amounts.
- the reference load circuit 300 approximately replicates the current Idecode draw during a read operation with a current Iload so the voltage applied to the reference word line REFWL approximately matches the voltage in word line WL that is coupled to a cell being read.
- the reference load circuit 300 includes a current load circuit 310 , a control circuit 320 , and five p-channel transistors 322 , 324 , 326 , 328 and 330 .
- P-channel transistor 330 is a pass-through transistor that selectively couples voltage signals to the reference word line REFWL.
- the control circuit 320 is a circuit that selectively couples either voltage Vx( 19 ) or voltage Vread to the reference word line REFWL by activating respective p-channel transistors 322 and 324 or 326 and 328 . More specifically, control circuit 320 couples either a voltage that approximately matches the cell access voltage applied to a word line that is coupled to a cell to be read or a voltage Vread. The voltage coupled to the reference word line REFWL that approximately matches the cell access voltage can be referred to as a reference access voltage.
- a Vread input signal is selectively coupled to an input of the control circuit 320 . When the Vread input signal is activated, the control circuit 320 sends an active low logic signal to activate p-channel transistors 326 and 328 .
- P-channel transistors 326 and 328 can be referred to as second p-channel transistors. This couples voltage Vread to the reference word line REFWL. Voltage Vread is used, in this embodiment, as a default voltage for the reference word line REFWL before an actual read operation begins.
- a Vx( 19 ) input signal is also selectively coupled to another input of the control circuit 320 . When the Vx ( 19 ) input signal is activated, the control circuit 320 sends an active low logic signal to activate p-channel transistors 322 and 324 . P-channel transistors 322 and 324 can be referred to as first p-channel transistors. This couples voltage Vx( 19 ) to the reference word line REFWL.
- the Vx input signal is coupled to the control circuit 320 during a read operation and during erase verify (when a cell is being read to determine if it is in an erased state).
- a voltage source Vcc is coupled to the control circuit 320 .
- FIG. 7 Another embodiment of the reference load circuit 300 is illustrated in FIG. 7 .
- this embodiment has a current load circuit 310 and a P-channel pass-through transistor 330 that selectively couples the pre-selected interior data line 134 to the reference word line REFWL.
- a control circuit is not used because voltage Vread is not selectively coupled to the reference word line REFWL.
- the current load circuit 310 includes three n-channel transistors 342 , 344 , and 346 coupled in series and a p-channel transistor 340 .
- the three n-channel transistors 342 , 344 and 346 are pre-selected to approximately replicate the transistor path in the tree matrix of decodes that point to a word line WL that is coupled to a cell that is selected to be read.
- the gates of the n-channel transistors 342 , 344 and 346 are coupled to a voltage source Vcc.
- the p-channel transistor 340 turns the current load matching circuit on and off. Coupling an active low logic signal to the gate of p-channel transistor 340 turns the load matching circuit on. Moreover, the active low logic signal is coupled to the gate of the p-channel transistor during a read or verify operation.
- a current Iload passes through the current load matching circuit 310 .
- Current Iload approximately matches current Idecode going though a decode matrix circuit 170 that is used to point to the word line having the cell to be read. Because the current drain of current Iload and current Idecode approximately matches, the voltage on the reference word line REFWL approximately matches the voltage on the word line WL that is coupled to the cell being read. Thus, the voltage applied to the control gate of the reference cell will be approximately equal to the voltage applied to the control gate of the memory cell being read.
- a flash memory device comprises a word line, a reference word line and a reference load circuit.
- the word line is coupled to a control gate of a memory cell.
- the reference word line is coupled to a control gate of a reference memory cell.
- the reference load circuit is coupled to the reference word line to approximately match a current load on the word line so a voltage level on the reference word line will be approximately equally to a voltage level on the word line during a read operation.
Abstract
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Cited By (5)
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US6501686B2 (en) * | 2000-08-09 | 2002-12-31 | Infineon Technologies Ag | Electronic driver circuit for word lines in a memory matrix, and memory apparatus |
US20040047175A1 (en) * | 2002-09-10 | 2004-03-11 | Texas Instruments Incorporated | System and method for pulling electrically isolated memory cells in a memory array to a non-floating state |
US20040052119A1 (en) * | 2002-09-13 | 2004-03-18 | Fujitsu Limited | Nonvolatile semiconductor memory device |
US20070125249A1 (en) * | 2005-07-19 | 2007-06-07 | Man Roland Druckmaschinen Ag | Arrangement and method for synchronizing printing presses and additional components |
US9042154B2 (en) | 2012-08-28 | 2015-05-26 | Micron Technology, Inc. | Non-volatile memory including reference signal path |
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US9042154B2 (en) | 2012-08-28 | 2015-05-26 | Micron Technology, Inc. | Non-volatile memory including reference signal path |
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