US6553512B1 - Method and apparatus for resolving CPU deadlocks - Google Patents
Method and apparatus for resolving CPU deadlocks Download PDFInfo
- Publication number
- US6553512B1 US6553512B1 US09/505,978 US50597800A US6553512B1 US 6553512 B1 US6553512 B1 US 6553512B1 US 50597800 A US50597800 A US 50597800A US 6553512 B1 US6553512 B1 US 6553512B1
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- Prior art keywords
- cpu
- deadlock
- mca
- bus error
- abort
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0793—Remedial or corrective actions
Definitions
- the technical field relates generally to digital computer systems and more particularly, but not by way of limitation, to systems for detecting errors within the instructions processed in such computer systems.
- a central processing unit may stop making forward progress for various reasons. For example, a CPU deadlock may occur when the code makes a memory reference to a non-existing memory. In some systems, the memory controllers will not respond to such an erroneous memory reference, causing the system to deadlock, waiting for data to return from a memory that does not exist. When a CPU deadlock occurs, there must be some mechanism for releasing the CPU from this deadlocked state.
- triggering a bus error substantially impacts the system by requiring the system to be restarted.
- triggering a bus error requires resetting the memory controllers. Triggering a bus error is expensive in terms of time and software required to fix the problem.
- a bus may have multiple CPUs, in which case all of them usually must be reset upon the triggering of a bus error.
- What is needed is method and an apparatus to resolve the CPU deadlock without triggering a bus error, if possible.
- a method for handling errors that deadlock a CPU by first attempting to resolve the deadlock without issuing a bus error and without restarting the computer. If the deadlock cannot be resolved without issuing a bus error, then a bus error is issued and the computer attempts to restart itself.
- the method involves comparing the number of clock cycles taken to execute an instruction to a designated abort value. When the instruction has taken the full abort value of cycles but has not retired, a machine-check abort (MCA) is issued to attempt to resolve the deadlock.
- MCA machine-check abort
- the method also involves comparing the number of clock cycles to a larger bus error value. If the MCA does not break the deadlock within a certain period—i.e., before the bus error value is reached—then a bus error is issued and the computer attempts to reset.
- a computer system includes a CPU, a counter, and a software programmable register.
- the counter determines the number of clock cycles consumed during the execution of an instruction and stores that number in the register.
- the number of clock cycles taken is compared to execute an instruction to a designated abort value.
- MCA machine-check abort
- the number of clock cycles is also compared to a larger bus error value. If the MCA does not break the deadlock within a certain period—i.e., before the bus error value is reached—then a bus error is issued and the CPU attempts to reset itself.
- FIG. 1 is a flow chart showing a method for resolving CPU deadlocks.
- FIG. 2 is a more detailed flow chart of FIG. 1 .
- FIG. 3 is a block diagram of the computer system capable of resolving CPU deadlocks.
- a means is provided for handling CPU deadlocks without causing a bus error and without resetting the computer system, when possible.
- Many CPU deadlocks are caused by memory bus errors and cannot be resolved without resetting the system.
- Some CPU deadlocks may be caused by errors other than memory bus errors. This is particularly true in mixed-architecture CPUs (i.e. those architectures capable of processing more than one type of instruction set) such as the IA-64 architecture.
- a deadlock may be caused during hardware emulation of the IA-32 architecture on the CPU.
- the system may be able to recover without resetting the system.
- Existing methods of handling CPU deadlocks simply cause the bus error every time and reset the system.
- An apparatus and a method attempt to resolve CPU deadlocks without resetting the system by invoking a abort (MCA) before triggering a memory bus error. This gives the system the opportunity to resolve the error without resetting if that is possible.
- MCA abort
- FIG. 1 shows a flow chart of the method of operation for resolving CPU deadlocks.
- the CPU processes instructions 110 . This processing continues until a CPU error occurs, which deadlocks the CPU. If an error occurs 120 , then the system triggers 130 an MCA.
- the MCA invokes a software mechanism that attempts to resolve the CPU error without resetting the CPU. If the MCA is successful 140 , then the CPU continues processing instructions 110 . If the machine-check abort fails to resolve the CPU problem, then a bus error is triggered 150 and the CPU attempts to reset itself in the traditional fashion.
- FIG. 2 is a more detailed flow chart of one embodiment of the operation for resolving CPU deadlocks.
- a counter is set 102 to zero.
- the CPU attempts to process 112 an instruction. As soon as the instruction is retired 104 , the counter is reset 102 to zero and the process begins anew. If the instruction is not retired 104 , then the counter is incremented 106 .
- a test function 108 determines whether the MCA has been disabled. As explained below, when an MCA issues, future MCAs are disabled 132 . If the MCA is disabled, then the test function 108 skips the MCA-related functions 122 , 130 , 132 .
- the CPU continues to process the instruction as usual 112 , for so long as the counter does not reach a predefined abort value 120 (2 n ⁇ 1 in the embodiment shown). If the counter does reach the abort value, then the MCA is triggered 130 , with the hope that the MCA will resolve the CPU problem. At the same time, a software programmable bit is also set 132 to prevent any further MCAs from issuing. The counter is then compared 142 to a predefined bus error value (2 n in the embodiment shown). If the counter has not reached the bus error value, then the CPU continues processing 112 . If the counter reaches or exceeds the bus error value, then a bus error is triggered 150 , and the CPU tries to reset 160 . The CPU then clears the counter 102 and continues processing 112 .
- FIG. 3 shows a block diagram of the hardware for resolving CPU deadlocks.
- a computer system 10 has a CPU 20 electrically connected to a counter 30 .
- the counter 30 increments 112 every clock cycle while the CPU 20 attempts to execute an instruction.
- the counter 30 reaches 122 a predetermined abort value (represented as 2 n ⁇ 1 in the embodiment of FIG. 3 )
- the system invokes an MCA 40 to attempt to resolve the problem.
- the counter 30 continues to increment 112 .
- a predetermined bus error value represented as 2 n in the embodiment of FIG. 3
- traditional methods of handling the deadlock are used, such as invoking a bus error 50 and restarting the system.
- the counter 30 receives a retire instruction signal 22 from the CPU 20 whenever an instruction retires. That retire instruction signal 22 resets the counter 30 as illustrated by the reset port 32 shown.
- the MCA causes the current CPU state to be destroyed and uses a special software handler that tries to repair the CPU.
- the MCA is an event that causes the system to restart at a particular memory address so that it can attempt to repair the CPU.
- the MCA may run on all of the CPUs or just some, for instance if only some CPUs take the MCA.
- the CPU quits the execution of its current code and the CPU is restarted at a particular memory address, from which code is executed.
- triggering the MCA only the current CPU is reset, and the machine tries to resolve the deadlock without resetting any other CPUs on the bus.
- the MCA checks the status registers. In the event that the MCA determines that the deadlock cannot be resolved without resetting the entire system, then it triggers a bus error.
Abstract
Description
Claims (20)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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US09/505,978 US6553512B1 (en) | 2000-02-16 | 2000-02-16 | Method and apparatus for resolving CPU deadlocks |
DE10056828A DE10056828B4 (en) | 2000-02-16 | 2000-11-16 | Method and device for releasing CPU deadlocks |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/505,978 US6553512B1 (en) | 2000-02-16 | 2000-02-16 | Method and apparatus for resolving CPU deadlocks |
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US6553512B1 true US6553512B1 (en) | 2003-04-22 |
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US09/505,978 Expired - Lifetime US6553512B1 (en) | 2000-02-16 | 2000-02-16 | Method and apparatus for resolving CPU deadlocks |
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DE (1) | DE10056828B4 (en) |
Cited By (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010023392A1 (en) * | 2000-03-17 | 2001-09-20 | Norihiro Nakatsuhama | Abnormality detection device for detecting an abnormality in a communication bus |
US20020116664A1 (en) * | 2000-12-22 | 2002-08-22 | Steven Tu | Method and apparatus for machine check abort handling in a multiprocessing system |
US20020124207A1 (en) * | 2001-01-23 | 2002-09-05 | Masao Ohwada | System for facilitated analysis of PCI bus malfuntion |
US20040054876A1 (en) * | 2002-09-13 | 2004-03-18 | Grisenthwaite Richard Roy | Synchronising pipelines in a data processing apparatus |
US20040054837A1 (en) * | 2001-01-31 | 2004-03-18 | International Business Machines Corporation | Controlling flow of data between data processing systems via a memory |
US6742135B1 (en) * | 2000-11-07 | 2004-05-25 | At&T Corp. | Fault-tolerant match-and-set locking mechanism for multiprocessor systems |
US6973590B1 (en) * | 2001-11-14 | 2005-12-06 | Unisys Corporation | Terminating a child process without risk of data corruption to a shared resource for subsequent processes |
US20060061689A1 (en) * | 2004-09-09 | 2006-03-23 | Chen Jiann-Tsuen | Deadlock detection and recovery logic for flow control based data path design |
US20060282205A1 (en) * | 2005-06-09 | 2006-12-14 | Lange Arthur F | System for guiding a farm implement between swaths |
US20070028127A1 (en) * | 2005-07-26 | 2007-02-01 | Samsung Electronics Co., Ltd. | Universal serial bus system, and method of driving the same |
US7383114B1 (en) | 2003-08-29 | 2008-06-03 | Trimble Navigation Limited | Method and apparatus for steering a farm implement to a path |
US20080263379A1 (en) * | 2007-04-17 | 2008-10-23 | Advanced Micro Devices, Inc. | Watchdog timer device and methods thereof |
CN103268276A (en) * | 2012-03-29 | 2013-08-28 | 威盛电子股份有限公司 | Deadlock/livelock resolution using service processor |
CN105849705A (en) * | 2014-12-13 | 2016-08-10 | 上海兆芯集成电路有限公司 | Pattern detector for detecting hangs |
EP3066559A4 (en) * | 2014-12-13 | 2017-07-19 | VIA Alliance Semiconductor Co., Ltd. | Logic analyzer for detecting hangs |
US9753799B2 (en) | 2014-12-13 | 2017-09-05 | Via Alliance Semiconductor Co., Ltd. | Conditional pattern detector for detecting hangs |
US10169137B2 (en) | 2015-11-18 | 2019-01-01 | International Business Machines Corporation | Dynamically detecting and interrupting excessive execution time |
US10324842B2 (en) | 2014-12-13 | 2019-06-18 | Via Alliance Semiconductor Co., Ltd | Distributed hang recovery logic |
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- 2000-02-16 US US09/505,978 patent/US6553512B1/en not_active Expired - Lifetime
- 2000-11-16 DE DE10056828A patent/DE10056828B4/en not_active Expired - Fee Related
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Cited By (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7424383B2 (en) * | 2000-03-17 | 2008-09-09 | Fujitsu Limited | Abnormality detection device for detecting an abnormality in a communication bus |
US20010023392A1 (en) * | 2000-03-17 | 2001-09-20 | Norihiro Nakatsuhama | Abnormality detection device for detecting an abnormality in a communication bus |
US7536582B1 (en) * | 2000-11-07 | 2009-05-19 | At&T Corp. | Fault-tolerant match-and-set locking mechanism for multiprocessor systems |
US6742135B1 (en) * | 2000-11-07 | 2004-05-25 | At&T Corp. | Fault-tolerant match-and-set locking mechanism for multiprocessor systems |
US6684346B2 (en) * | 2000-12-22 | 2004-01-27 | Intel Corporation | Method and apparatus for machine check abort handling in a multiprocessing system |
US20020116664A1 (en) * | 2000-12-22 | 2002-08-22 | Steven Tu | Method and apparatus for machine check abort handling in a multiprocessing system |
US7216252B1 (en) * | 2000-12-22 | 2007-05-08 | Intel Corporation | Method and apparatus for machine check abort handling in a multiprocessing system |
US7003701B2 (en) * | 2001-01-23 | 2006-02-21 | Nec Corporation | System for facilitated analysis of PCI bus malfunction |
US20020124207A1 (en) * | 2001-01-23 | 2002-09-05 | Masao Ohwada | System for facilitated analysis of PCI bus malfuntion |
US20040054837A1 (en) * | 2001-01-31 | 2004-03-18 | International Business Machines Corporation | Controlling flow of data between data processing systems via a memory |
US7409468B2 (en) * | 2001-01-31 | 2008-08-05 | International Business Machines Corporation | Controlling flow of data between data processing systems via a memory |
US6973590B1 (en) * | 2001-11-14 | 2005-12-06 | Unisys Corporation | Terminating a child process without risk of data corruption to a shared resource for subsequent processes |
US20040054876A1 (en) * | 2002-09-13 | 2004-03-18 | Grisenthwaite Richard Roy | Synchronising pipelines in a data processing apparatus |
US7024543B2 (en) * | 2002-09-13 | 2006-04-04 | Arm Limited | Synchronising pipelines in a data processing apparatus |
US7383114B1 (en) | 2003-08-29 | 2008-06-03 | Trimble Navigation Limited | Method and apparatus for steering a farm implement to a path |
US7418625B2 (en) * | 2004-09-09 | 2008-08-26 | Broadcom Corporation | Deadlock detection and recovery logic for flow control based data path design |
US20060061689A1 (en) * | 2004-09-09 | 2006-03-23 | Chen Jiann-Tsuen | Deadlock detection and recovery logic for flow control based data path design |
US20060282205A1 (en) * | 2005-06-09 | 2006-12-14 | Lange Arthur F | System for guiding a farm implement between swaths |
US7860628B2 (en) | 2005-06-09 | 2010-12-28 | Trimble Navigation Limited | System for guiding a farm implement between swaths |
US20070028127A1 (en) * | 2005-07-26 | 2007-02-01 | Samsung Electronics Co., Ltd. | Universal serial bus system, and method of driving the same |
US20080263379A1 (en) * | 2007-04-17 | 2008-10-23 | Advanced Micro Devices, Inc. | Watchdog timer device and methods thereof |
US9575816B2 (en) | 2012-03-29 | 2017-02-21 | Via Technologies, Inc. | Deadlock/livelock resolution using service processor |
EP2645237A3 (en) * | 2012-03-29 | 2015-05-27 | VIA Technologies, Inc. | Deadlock/livelock resolution using service processor |
CN103268276A (en) * | 2012-03-29 | 2013-08-28 | 威盛电子股份有限公司 | Deadlock/livelock resolution using service processor |
CN105849705A (en) * | 2014-12-13 | 2016-08-10 | 上海兆芯集成电路有限公司 | Pattern detector for detecting hangs |
EP3066559A4 (en) * | 2014-12-13 | 2017-07-19 | VIA Alliance Semiconductor Co., Ltd. | Logic analyzer for detecting hangs |
EP3047380A4 (en) * | 2014-12-13 | 2017-07-19 | VIA Alliance Semiconductor Co., Ltd. | Pattern detector for detecting hangs |
US9753799B2 (en) | 2014-12-13 | 2017-09-05 | Via Alliance Semiconductor Co., Ltd. | Conditional pattern detector for detecting hangs |
US9946651B2 (en) | 2014-12-13 | 2018-04-17 | Via Alliance Semiconductor Co., Ltd | Pattern detector for detecting hangs |
US10067871B2 (en) | 2014-12-13 | 2018-09-04 | Via Alliance Semiconductor Co., Ltd | Logic analyzer for detecting hangs |
CN105849705B (en) * | 2014-12-13 | 2019-06-04 | 上海兆芯集成电路有限公司 | For detecting the logic analyzer of pause |
US10324842B2 (en) | 2014-12-13 | 2019-06-18 | Via Alliance Semiconductor Co., Ltd | Distributed hang recovery logic |
US10169137B2 (en) | 2015-11-18 | 2019-01-01 | International Business Machines Corporation | Dynamically detecting and interrupting excessive execution time |
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Publication number | Publication date |
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DE10056828B4 (en) | 2004-05-06 |
DE10056828A1 (en) | 2001-09-06 |
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