US6627990B1 - Thermally enhanced stacked die package - Google Patents

Thermally enhanced stacked die package Download PDF

Info

Publication number
US6627990B1
US6627990B1 US10/359,407 US35940703A US6627990B1 US 6627990 B1 US6627990 B1 US 6627990B1 US 35940703 A US35940703 A US 35940703A US 6627990 B1 US6627990 B1 US 6627990B1
Authority
US
United States
Prior art keywords
die
substrate
metal interposer
stacked
design
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US10/359,407
Inventor
Il Kwon Shim
Kambhampati Ramakrishna
Seng Gaun Chow
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Stats Chippac Pte Ltd
Original Assignee
ST Assembly Test Services Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ST Assembly Test Services Pte Ltd filed Critical ST Assembly Test Services Pte Ltd
Priority to US10/359,407 priority Critical patent/US6627990B1/en
Assigned to ST ASSEMBLY TEST SERVICES PTE LTD reassignment ST ASSEMBLY TEST SERVICES PTE LTD ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHOW, SENG GUAN, RAMAKRISHNA, KAMBHAMPATI, SHIM, IL KWON
Application granted granted Critical
Publication of US6627990B1 publication Critical patent/US6627990B1/en
Priority to SG200400190A priority patent/SG113495A1/en
Assigned to STATS CHIPPAC LTD. reassignment STATS CHIPPAC LTD. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: ST ASSEMBLY TEST SERVICES LTD.
Assigned to CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT reassignment CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: STATS CHIPPAC LTD., STATS CHIPPAC, INC.
Assigned to STATS CHIPPAC PTE. LTE. reassignment STATS CHIPPAC PTE. LTE. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: STATS CHIPPAC LTD.
Assigned to STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD., STATS CHIPPAC, INC. reassignment STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Anticipated expiration legal-status Critical
Assigned to STATS ChipPAC Pte. Ltd. reassignment STATS ChipPAC Pte. Ltd. CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0400. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Assignors: STATS CHIPPAC LTD.
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06575—Auxiliary carrier between devices, the carrier having no electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06579—TAB carriers; beam leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06589—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates generally to electronic packaging and specifically to stacked die/chip packages.
  • U.S. Pat. No. 6,261,865 B1 to Akram describes a multi-chip semiconductor package using a lead-on-chip lead frame and method of construction.
  • U.S. Pat. No. 6,118,176 to Tao et al. describes a stacked chip assembly generally includes a first chip, a second chip and a lead frame.
  • U.S. Pat. No. 6,297,547 B1 to Akram describes a multiple die package in which a first and second die are mounted on a leadframe.
  • U.S. Pat. No. Re. 36,613 to Ball describes a multiple stacked die device that contains up to four dies and permits close-tolerance stacking by a low-loop-profile wire-bonding operation and a thin-adhesive layer between the stacked dies.
  • U.S. Pat. No. 6,080,264 to Ball describes an apparatus and method for increasing integrated circuit density comprising utilizing chips with both direct (flip chip type) chip to conductors connection technology and wire bonds and/or tape automated bonding (TAB).
  • direct (flip chip type) chip to conductors connection technology and wire bonds and/or tape automated bonding (TAB).
  • TAB tape automated bonding
  • U.S. Pat. No. 6,087,718 to Cho describes a stacked-type semiconductor chip package of a lead-on chip structure which is modified for stacking chips in the package.
  • U.S. Pat. No. 6,337,521 B1 to Masuda describes a semiconductor device and a method of manufacturing the same.
  • the device comprising two semiconductor chips stacked on each other with their backs opposite to each other and sealed with a mold resin.
  • Another object of one or more embodiments of the present invention to provide stacked die/chip package designs having reduced die attach interface area to reduce stress and moisture sensitivity.
  • a stacked die design comprising: a substrate having a lower surface and an upper surface; a lower die connected to the substrate; a thermally conductive metal interposer thermally connected to the substrate; and an upper die thermally connected to the metal interposer.
  • the lower die and the upper die being spaced apart and comprising a stacked die whereby any heat generated by the upper die is transferred to the substrate by the metal interposer.
  • FIGS. 1 and 2 schematically illustrate a first preferred electrically isolated metal interposer embodiment of the present invention with FIG. 1 being a cross-sectional view of the overhead plan view FIG. 2 taken along line 1 — 1 .
  • FIGS. 3 and 4 schematically illustrate a second preferred electrically grounded metal interposer embodiment of the present invention with FIG. 3 being a cross-sectional view of the top down plan view FIG. 4 taken along line 3 — 3 .
  • FIG. 5 schematically illustrates a top down plan view of the second preferred electrically grounded metal interposer embodiment of the present invention after the die attachment (D/A) process.
  • FIGS. 6 and 7 schematically illustrate a third preferred electrically grounded metal interposer with support columns embodiment of the present invention having a metal interposer above the lower die/chip, with FIG. 6 being a cross-sectional view of the top down plan view FIG. 7 taken along line 6 — 6 .
  • FIGS. 8 to 9 schematically illustrate a fourth preferred electrically grounded metal interposer with support columns embodiment of the present invention having a metal interposer below the lower die/chip with: FIG. 8 being a cross-sectional electrically isolated metal interposer view of the top down plan view FIG. 9 taken along line 8 — 8 .
  • FIG. 10 is top down plan view of a modification of the fourth embodiment wherein the upper portion of the metal interposer comprises four discrete pads the end of each support column.
  • FIGS. 1 and 2 First Embodiment—Electrically isolated Metal Interposer 20 ; FIGS. 1 and 2
  • the first embodiment of the present invention illustrates a package 10 having a electrically isolated metal interposer stacked die/chip design with no ground.
  • Lower die/chip 12 is attached to a substrate 14 preferably using an adhesive material 18 .
  • Substrate 14 may include solder balls or metallized lands 16 for interconnection to the system level printed circuit board (not shown) affixed to the lower surface of substrate 14 as shown in FIG. 1 .
  • Solder balls 16 are preferably comprised of a eutectic tin-lead solder alloy, tin, lead, silver, gold, indium and more preferably a eutectic tin-lead solder alloy.
  • the substrate 14 is preferably an epoxy-glass laminate, a polyimide tape, a ceramic, a copper alloy leadframe or an aluminum alloy leadframe.
  • Adhesive material 18 is preferably comprised of a thermally conductive organic/ inorganic filler.
  • Lower die/chip wires 26 may then be attached to the upper surface of lower die/chip 12 and to the upper surface of the substrate 14 as shown in FIG. 1 .
  • Metal interposer 20 is then attached to the substantial center of lower die/chip 12 using adhesive material 18 .
  • Metal interposer 20 is generally a solid, thermally conductive structure including a ring-shaped outer ring die pad 22 connected to the center 21 of metal interposer 20 by tie bars/internal support columns 24 . Internal support columns/tie bars 24 are used to connect the center die pad 21 to the ring-shaped outer die pad 22 .
  • Metal interposer 20 is preferably comprised of a copper alloy, an aluminum alloy or an iron alloy and is more preferably comprised of a copper alloy. Metal interposer 20 is electrically conductive.
  • Upper die/chip 30 is then substantially centered over, and attached to, the upper surface of the ring-shaped outer ring die pad 22 using adhesive material 18 .
  • Upper die/chip wires 34 may then be attached to the upper surface of upper die/chip 30 and to the upper surface of the substrate 14 as shown in FIG. 1 .
  • the metal interposer 20 is a thermal conductor, permitting heat from the upper die/chip 30 to be taken away from the upper die/chip 30 and through the lower die/chip 12 into the substrate 14 and away from package 10 through the solder balls or metallized lands 16 .
  • An encapsulate/molding material 36 is then formed around the upper die/chip 30 , the upper and lower die/chip wires 26 , 34 and over the lower die/chip 12 and the substrate 14 as shown in FIG. 1 .
  • the lower and upper die/chip wires 26 , 34 may be attached to the respective lower and upper dies/chips 12 , 30 after the lower and upper dies/chips 12 , 30 are affixed to the metal interposer 20 .
  • the wires 26 , 34 may be attached in one pass (equipment set-up) if the upper die 30 is small along its length and/or width and does not interfere with the wire connection of the lower die 12 to the substrate 14 wiring process.
  • FIG. 2 is a top-down, plan view of FIG. 1 (with upper and lower die/chips 12 , 30 not shown) with FIG. 1 being a cross-section of FIG. 2 along line 1 — 1 (with upper and lower die/chips 12 , 30 shown).
  • FIG. 2 illustrates package 10 having the center 21 of metal interposer 20 connected to its ring-shaped outer ring die pad 22 through tie bars 24 .
  • Encapsulant 36 envelopes the metal interposer 20 (and upper and lower die/chips 12 , 30 (not shown)).
  • tie bars 24 of metal interposer 20 are illustrated in FIG. 2 in a “+” design, other essentially symmetrical designs of tie bars 24 are possible such as, for example, an “X” design.
  • first embodiment electrically isolated metal interposer package 10 has no ground.
  • the second embodiment of the present invention illustrates a package 110 having a electrically grounded metal interposer with support column stacked die/chip design.
  • Lower die/chip 112 is attached to a substrate 114 preferably using an adhesive material 118 .
  • Substrate 114 may include solder balls or metallized lands 116 for interconnection to the system level printed circuit board (not shown) affixed to the lower surface of substrate 114 as shown in FIG. 3 .
  • Solder balls 116 are preferably comprised of a eutectic tin-lead solder alloy, tin, lead, silver, gold, indium and more preferably a eutectic tin-lead solder alloy.
  • the substrate 114 is preferably an epoxy-glass laminate, a polyimide tape, a ceramic, a copper alloy leadframe or an aluminum alloy leadframe.
  • Adhesive material 118 is preferably comprised of a thermally conductive organic/inorganic filler.
  • Lower die wires may then be attached to the upper surface of lower die/chip 112 and to the upper surface of the substrate 114 .
  • the wires may be attached in one pass (equipment set-up) if the upper die 130 is small along its length and/or width and does not interfere with the wire connection of the lower die 112 to the substrate 114 wiring process.
  • Metal interposer 120 is then attached to the substantial center of lower die/chip 112 using adhesive material 118 .
  • Metal interposer 120 is a thermally conductive structure including outer portions 122 and a center portion 121 that is connected to the substantial center of lower die/chip 112 .
  • the outer portions 122 of metal interposer 120 are electrically grounded to substrate 114 as at 138 through leg portions/external support columns 123 .
  • External support columns 123 are used to support the ring-shaped outer die pad 122 connecting to underlying substrate 114 in place.
  • Metal interposer 120 is preferably comprised of a copper alloy, an aluminum alloy or an iron alloy and is more preferably a copper alloy. Metal interposer 120 is electrically conductive.
  • Upper die/chip 130 is then substantially centered over, and attached to, the upper surfaces of the outer portions 122 of metal interposer 120 using adhesive material 118 .
  • the metal interposer 120 is a thermal conductor, permitting heat from the upper die/chip 130 to be taken away from the upper die/chip 130 and through the lower die/chip 112 into the substrate 114 and away from package 110 through the solder balls or metallized lands 116 . Heat also flows from the upper die 130 to the substrate 114 through the legs 123 of the metal interposer 120 .
  • Upper die/chip wires may then be attached to the upper surface of upper die/chip 130 and to the upper surface of the substrate 114 .
  • the wires (not shown) may be attached in one pass (equipment set-up) if the upper die 130 is small along its length and/or width and does not interfere with the wire connection of the lower die 112 to the substrate 114 wiring process.
  • An encapsulate/molding material 136 is then formed around the upper die/chip 130 , the upper and lower die/chip wires and over the lower die/chip 112 and the substrate 114 as shown in FIG. 3 .
  • the lower and upper die/chip wires may be attached to the respective lower and upper dies/chips 112 , 130 after the lower and upper dies/chips 112 , 130 are affixed to the metal interposer 120 . If the upper die/chip 130 has bond pads on only two opposite sides, more support columns could be added, with the limit to the number added being encapsulate/mold 136 flow.
  • FIG. 4 is a top-down, plan view of FIG. 3 with FIG. 3 being a cross-section of FIG. 2 along line 3 — 3 .
  • FIG. 4 illustrates package 110 having the center and outer portions 121 , 122 of metal interposer 120 .
  • Encapsulant 136 envelopes the metal interposer 120 (and upper and lower die/chips 112 , 130 (not shown)).
  • FIG. 5 is a top down, plan view of FIG. 3 after die attachment.
  • the third embodiment of the present invention illustrates a package 210 having a electrically grounded metal interposer with support columns stacked die/chip design.
  • Lower die/chip 212 is attached to a substrate 214 preferably using an adhesive material 218 .
  • Substrate 214 may include solder balls or metallized lands 216 for interconnection to the system level printed circuit board (not shown) affixed to the lower surface of substrate 214 as shown in FIG. 6 .
  • Solder balls 216 are preferably comprised of a eutectic tin-lead solder alloy, tin, lead, silver, gold, indium and more preferably a eutectic tin-lead solder alloy.
  • the substrate 214 is preferably an epoxy-glass laminate, a polyimide tape, a ceramic, a copper alloy leadframe or an aluminum alloy leadframe.
  • Adhesive material 218 is preferably comprised of a thermally conductive organic/ inorganic filler.
  • Lower die wires may then be attached to the upper surface of lower die/chip 212 and to the upper surface of the substrate 214 .
  • Metal interposer 220 is then substantially centered over the lower die/chip 212 and the upper portion 222 of metal interposer 220 is attached, and electrically grounded, to substrate 214 through leg portions/external support columns 223 as at 238 using adhesive material 218 . External support columns 223 are used to support the ring-shaped outer die pad 222 connecting to underlying substrate 214 in place.
  • Metal interposer 220 is a thermally conductive structure.
  • Metal interposer 220 is preferably comprised of a copper alloy, an aluminum alloy or an iron alloy and is more preferably a copper alloy. Metal interposer 20 is electrically conductive.
  • a thermal glue 240 may be interposed between the upper portion 222 of metal interposer 220 and the upper surface of lower die/chip 212 as shown in FIG. 6 .
  • the thermal glue 240 is thermally conductive and permits transfer of heat from the upper die 230 to the lower die 212 or from the lower die 212 to the upper die 230 depending upon the temperature difference.
  • Upper die/chip 230 is then substantially centered over, and attached to, the upper surfaces of the upper portion 222 of metal interposer 220 using adhesive material 218 .
  • the metal interposer 220 is a thermal conductor, permitting heat from the upper die/chip 230 to be taken away from the upper die/chip 230 and into the substrate 214 and away from package 210 through the solder balls or metallized lands 216 . Heat also flows from the upper die 230 to the substrate 214 through the legs 223 of the metal interposer 220 .
  • Upper die/chip wires may then be attached to the upper surface of upper die/chip 230 and to the upper surface of the substrate 214 .
  • An encapsulate/molding material 236 is then formed around the upper die/chip 230 , the upper and lower die/chip wires and over the lower die/chip 212 and the substrate 214 as shown in FIG. 6 .
  • the lower and upper die/chip wires may be attached to the respective lower and upper dies/chips 212 , 230 after the lower and upper dies/chips 212 , 230 are affixed to the metal interposer 220 .
  • the wires may be attached in one pass (equipment set-up) if the upper die 230 is small along its length and/or width and does not interfere with the wire connection of the lower die 212 to the substrate 214 wiring process. If the upper die/chip 230 has bond pads on only two opposite sides, more support columns could be added, with the limit to the number added being encapsulate/mold 236 flow.
  • FIG. 7 is a top-down, plan view of FIG. 6, with FIG. 6 being a cross-section of FIG. 7 along line 6 — 6 .
  • FIG. 7 illustrates package 210 having metal interposer 220 electrically grounded to substrate 214 through leg portions/external support columns 223 as at 238 .
  • Encapsulant 236 envelopes the metal interposer 220 (and upper and lower die/chips 212 , 230 (not shown)).
  • FIGS. 9 to 11 Fourth Embodiment—Electrically Grounded Metal Interposer 320 ; FIGS. 9 to 11
  • the fourth embodiment of the present invention illustrates a package 310 having another electrically grounded metal interposer with support columns stacked die/chip design.
  • metal interposer 320 is affixed, and electrically grounded, to the substantial center of substrate 314 at its lower center portion 321 preferably using adhesive material 318 .
  • Metal interposer 320 is a thermally conductive structure and further includes upper portion 322 connected to the lower center portion 321 through leg portions/external support columns 324 .
  • the substrate 314 is preferably an epoxy-glass laminate, a polyimide tape, a ceramic, a copper alloy leadframe or an aluminum alloy leadframe.
  • Metal interposer 320 is preferably comprised of a copper alloy, an aluminum alloy or an iron alloy and is more preferably a copper alloy.
  • Metal interposer 20 is electrically conductive.
  • Adhesive material 318 is preferably comprised of a thermally conductive organic/inorganic filler.
  • Substrate 314 may include solder balls or metallized lands 316 for interconnection to the system level printed circuit board (not shown) affixed to the lower surface of substrate 314 as shown in FIG. 8 .
  • Solder balls 316 are preferably comprised of a eutectic tin-lead solder alloy, tin, lead, silver, gold, indium and more preferably a eutectic tin-lead solder alloy.
  • Lower die/chip 312 is then substantially centered, and attached to, the lower center portion of metal interposer 320 preferably using adhesive material 318 .
  • Lower die wires 326 may then be attached to the upper surface of lower die/chip 312 and to the upper surface of the substrate 314 .
  • Upper die/chip 330 is then substantially centered over, and attached to, the upper surfaces of the upper portion 322 of metal interposer 320 preferably using adhesive material 318 .
  • the metal interposer 320 is a thermal conductor, permitting heat from the upper die/chip 330 to be taken away from the upper die/chip 330 and into the substrate 314 and away from package 310 via the leg portions/external support columns 324 through the solder balls or metallized lands 316 . Any heat from the lower die/chip 312 may be likewise taken away from the lower die/chip 312 and into the substrate 314 and away from package 310 through the solder balls or metallized lands 316 .
  • Upper die/chip wires 334 may then be attached to the upper surface of upper die/chip 330 and to the upper surface of the substrate 314 .
  • An encapsulate/molding material 336 is then formed around the upper die/chip 330 , the upper and lower die/chip wires 334 , 326 and over the lower die/chip 312 and the substrate 314 as shown in FIG. 8 .
  • the upper and lower die/chip wires 334 , 326 may be attached to the respective upper and lower dies/chips 332 , 312 after the upper and lower dies/chips 330 , 312 are affixed to the metal interposer 320 .
  • the upper die/chip 330 has bond pads on only two opposite sides, more support columns could be added, with the limit to the number added being encapsulate/mold 336 flow.
  • FIG. 9 is a top-down, plan view of FIG. 8, with FIG. 8 being a cross-section of FIG. 9 along line 8 — 8 .
  • FIG. 9 illustrates package 310 having metal interposer 320 electrically grounded to substrate 214 through leg portions/external support columns 223 as at 238 .
  • Encapsulant 236 envelopes the metal interposer 220 (and upper and lower die/chips 212 , 230 (not shown)).
  • FIG. 10 is top down plan view of a modification of the fourth embodiment wherein the upper portion of the metal interposer 320 comprises four discrete pads 337 the end of each leg portion/support column 324 .
  • the stacked die/chip package designs of the embodiments of the present invention have reduced die attach interface area to reduce stress and moisture sensitivity.
  • metal interposer to substrate attachment stress as the metal interposer is more preferably comprised of a copper alloy which closely matches in CTE with laminate substrates;
  • upper die/chip grounding is made possible, such upper die/chip grounding also isolates the upper die/chip from the lower die/chip in high frequency operation such as switching noise or interference.

Abstract

A stacked die design, and a method of forming the same, comprising: a substrate having a lower surface and an upper surface; a lower die connected to the substrate; a thermally conductive metal interposer thermally connected to the lower die and/or the substrate; and an upper die thermally connected to the metal interposer. The lower die and the upper die being spaced apart and comprising a stacked die whereby any heat generated by the upper die is transferred to the substrate by the metal interposer.

Description

FIELD OF THE INVENTION
The present invention relates generally to electronic packaging and specifically to stacked die/chip packages.
BACKGROUND OF THE INVENTION
Current practice involves using solid element spacers between stacked dies/chips. Such spacers are typically comprised of organic adhesive alone or in combination with ceramic/silicon. However, the top die/chip has been found to have thermal issues. The solid element spacers cannot be comprised of electrically conductive material and such solid element spacers generally have low thermal conductivity.
U.S. Pat. No. 6,261,865 B1 to Akram describes a multi-chip semiconductor package using a lead-on-chip lead frame and method of construction.
U.S. Pat. No. 6,087,722 to Lee et al. describes a multi-chip package that does not include a die pad.
U.S. Pat. No. 6,118,176 to Tao et al. describes a stacked chip assembly generally includes a first chip, a second chip and a lead frame.
U.S. Pat. No. 6,297,547 B1 to Akram describes a multiple die package in which a first and second die are mounted on a leadframe.
U.S. Pat. No. 5,814,881 to Alagaratnam et al. describes a stacked integrated chip package and method of making same.
U.S. Pat. No. Re. 36,613 to Ball describes a multiple stacked die device that contains up to four dies and permits close-tolerance stacking by a low-loop-profile wire-bonding operation and a thin-adhesive layer between the stacked dies.
U.S. Pat. No. 6,080,264 to Ball describes an apparatus and method for increasing integrated circuit density comprising utilizing chips with both direct (flip chip type) chip to conductors connection technology and wire bonds and/or tape automated bonding (TAB).
U.S. Pat. No. 6,087,718 to Cho describes a stacked-type semiconductor chip package of a lead-on chip structure which is modified for stacking chips in the package.
U.S. Pat. No. 6,307,257 B1 to Huang et al. describes a dual-chip integrated circuit (IC) package with a chip-die pad formed form leadframe leads.
U.S. Pat. No. 6,337,521 B1 to Masuda describes a semiconductor device and a method of manufacturing the same. The device comprising two semiconductor chips stacked on each other with their backs opposite to each other and sealed with a mold resin.
SUMMARY OF THE INVENTION
Accordingly, it is an object of one or more embodiments of the present invention to provide thermally enhanced stacked die/chip package designs.
Another object of one or more embodiments of the present invention to provide stacked die/chip package designs having reduced die attach interface area to reduce stress and moisture sensitivity.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a stacked die design, and a method of forming the same, comprising: a substrate having a lower surface and an upper surface; a lower die connected to the substrate; a thermally conductive metal interposer thermally connected to the substrate; and an upper die thermally connected to the metal interposer. The lower die and the upper die being spaced apart and comprising a stacked die whereby any heat generated by the upper die is transferred to the substrate by the metal interposer.
BRIEF DESCRIPTION OF THE DRAWINGS
The features and advantages of the method of the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or corresponding elements, regions and portions and in which:
FIGS. 1 and 2 schematically illustrate a first preferred electrically isolated metal interposer embodiment of the present invention with FIG. 1 being a cross-sectional view of the overhead plan view FIG. 2 taken along line 1—1.
FIGS. 3 and 4 schematically illustrate a second preferred electrically grounded metal interposer embodiment of the present invention with FIG. 3 being a cross-sectional view of the top down plan view FIG. 4 taken along line 3—3.
FIG. 5 schematically illustrates a top down plan view of the second preferred electrically grounded metal interposer embodiment of the present invention after the die attachment (D/A) process.
FIGS. 6 and 7 schematically illustrate a third preferred electrically grounded metal interposer with support columns embodiment of the present invention having a metal interposer above the lower die/chip, with FIG. 6 being a cross-sectional view of the top down plan view FIG. 7 taken along line 6—6.
FIGS. 8 to 9 schematically illustrate a fourth preferred electrically grounded metal interposer with support columns embodiment of the present invention having a metal interposer below the lower die/chip with: FIG. 8 being a cross-sectional electrically isolated metal interposer view of the top down plan view FIG. 9 taken along line 8—8.
FIG. 10 is top down plan view of a modification of the fourth embodiment wherein the upper portion of the metal interposer comprises four discrete pads the end of each support column.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
First Embodiment—Electrically isolated Metal Interposer 20; FIGS. 1 and 2
As shown in FIGS. 1 and 2, the first embodiment of the present invention illustrates a package 10 having a electrically isolated metal interposer stacked die/chip design with no ground.
Lower die/chip 12 is attached to a substrate 14 preferably using an adhesive material 18. Substrate 14 may include solder balls or metallized lands 16 for interconnection to the system level printed circuit board (not shown) affixed to the lower surface of substrate 14 as shown in FIG. 1. Solder balls 16 are preferably comprised of a eutectic tin-lead solder alloy, tin, lead, silver, gold, indium and more preferably a eutectic tin-lead solder alloy.
The substrate 14 is preferably an epoxy-glass laminate, a polyimide tape, a ceramic, a copper alloy leadframe or an aluminum alloy leadframe.
Adhesive material 18 is preferably comprised of a thermally conductive organic/ inorganic filler.
Lower die/chip wires 26 may then be attached to the upper surface of lower die/chip 12 and to the upper surface of the substrate 14 as shown in FIG. 1.
Metal interposer 20 is then attached to the substantial center of lower die/chip 12 using adhesive material 18. Metal interposer 20 is generally a solid, thermally conductive structure including a ring-shaped outer ring die pad 22 connected to the center 21 of metal interposer 20 by tie bars/internal support columns 24. Internal support columns/tie bars 24 are used to connect the center die pad 21 to the ring-shaped outer die pad 22.
Metal interposer 20 is preferably comprised of a copper alloy, an aluminum alloy or an iron alloy and is more preferably comprised of a copper alloy. Metal interposer 20 is electrically conductive.
Upper die/chip 30 is then substantially centered over, and attached to, the upper surface of the ring-shaped outer ring die pad 22 using adhesive material 18.
Upper die/chip wires 34 may then be attached to the upper surface of upper die/chip 30 and to the upper surface of the substrate 14 as shown in FIG. 1.
It is noted that the metal interposer 20 is a thermal conductor, permitting heat from the upper die/chip 30 to be taken away from the upper die/chip 30 and through the lower die/chip 12 into the substrate 14 and away from package 10 through the solder balls or metallized lands 16.
An encapsulate/molding material 36 is then formed around the upper die/chip 30, the upper and lower die/ chip wires 26, 34 and over the lower die/chip 12 and the substrate 14 as shown in FIG. 1.
Alternately, the lower and upper die/ chip wires 26, 34 may be attached to the respective lower and upper dies/chips 12, 30 after the lower and upper dies/chips 12, 30 are affixed to the metal interposer 20. The wires 26, 34 may be attached in one pass (equipment set-up) if the upper die 30 is small along its length and/or width and does not interfere with the wire connection of the lower die 12 to the substrate 14 wiring process.
FIG. 2 is a top-down, plan view of FIG. 1 (with upper and lower die/chips 12, 30 not shown) with FIG. 1 being a cross-section of FIG. 2 along line 1—1 (with upper and lower die/chips 12, 30 shown). FIG. 2 illustrates package 10 having the center 21 of metal interposer 20 connected to its ring-shaped outer ring die pad 22 through tie bars 24. Encapsulant 36 envelopes the metal interposer 20 (and upper and lower die/chips 12, 30 (not shown)).
It is noted that while the tie bars 24 of metal interposer 20 are illustrated in FIG. 2 in a “+” design, other essentially symmetrical designs of tie bars 24 are possible such as, for example, an “X” design.
It is noted that the first embodiment electrically isolated metal interposer package 10 has no ground.
Second Embodiment—Electrically Grounded Metal Interposer 120; FIGS. 3 to 6
As shown in FIGS. 3 to 5, the second embodiment of the present invention illustrates a package 110 having a electrically grounded metal interposer with support column stacked die/chip design.
Lower die/chip 112 is attached to a substrate 114 preferably using an adhesive material 118. Substrate 114 may include solder balls or metallized lands 116 for interconnection to the system level printed circuit board (not shown) affixed to the lower surface of substrate 114 as shown in FIG. 3. Solder balls 116 are preferably comprised of a eutectic tin-lead solder alloy, tin, lead, silver, gold, indium and more preferably a eutectic tin-lead solder alloy.
The substrate 114 is preferably an epoxy-glass laminate, a polyimide tape, a ceramic, a copper alloy leadframe or an aluminum alloy leadframe.
Adhesive material 118 is preferably comprised of a thermally conductive organic/inorganic filler.
Lower die wires (not shown) may then be attached to the upper surface of lower die/chip 112 and to the upper surface of the substrate 114. The wires (not shown) may be attached in one pass (equipment set-up) if the upper die 130 is small along its length and/or width and does not interfere with the wire connection of the lower die 112 to the substrate 114 wiring process.
Metal interposer 120 is then attached to the substantial center of lower die/chip 112 using adhesive material 118. Metal interposer 120 is a thermally conductive structure including outer portions 122 and a center portion 121 that is connected to the substantial center of lower die/chip 112. The outer portions 122 of metal interposer 120 are electrically grounded to substrate 114 as at 138 through leg portions/external support columns 123. External support columns 123 are used to support the ring-shaped outer die pad 122 connecting to underlying substrate 114 in place.
Metal interposer 120 is preferably comprised of a copper alloy, an aluminum alloy or an iron alloy and is more preferably a copper alloy. Metal interposer 120 is electrically conductive.
Upper die/chip 130 is then substantially centered over, and attached to, the upper surfaces of the outer portions 122 of metal interposer 120 using adhesive material 118.
It is noted that the metal interposer 120 is a thermal conductor, permitting heat from the upper die/chip 130 to be taken away from the upper die/chip 130 and through the lower die/chip 112 into the substrate 114 and away from package 110 through the solder balls or metallized lands 116. Heat also flows from the upper die 130 to the substrate 114 through the legs 123 of the metal interposer 120.
Upper die/chip wires (not shown) may then be attached to the upper surface of upper die/chip 130 and to the upper surface of the substrate 114. The wires (not shown) may be attached in one pass (equipment set-up) if the upper die 130 is small along its length and/or width and does not interfere with the wire connection of the lower die 112 to the substrate 114 wiring process.
An encapsulate/molding material 136 is then formed around the upper die/chip 130, the upper and lower die/chip wires and over the lower die/chip 112 and the substrate 114 as shown in FIG. 3.
Alternately, the lower and upper die/chip wires may be attached to the respective lower and upper dies/ chips 112, 130 after the lower and upper dies/ chips 112,130 are affixed to the metal interposer 120. If the upper die/chip 130 has bond pads on only two opposite sides, more support columns could be added, with the limit to the number added being encapsulate/mold 136 flow.
FIG. 4 is a top-down, plan view of FIG. 3 with FIG. 3 being a cross-section of FIG. 2 along line 3—3. FIG. 4 illustrates package 110 having the center and outer portions 121, 122 of metal interposer 120. Encapsulant 136 envelopes the metal interposer 120 (and upper and lower die/chips 112, 130 (not shown)).
FIG. 5 is a top down, plan view of FIG. 3 after die attachment.
Third Embodiment—Electrically Grounded Metal Interposer 220; FIGS. 7 and 8
As shown in FIGS. 7 and 8, the third embodiment of the present invention illustrates a package 210 having a electrically grounded metal interposer with support columns stacked die/chip design.
Lower die/chip 212 is attached to a substrate 214 preferably using an adhesive material 218. Substrate 214 may include solder balls or metallized lands 216 for interconnection to the system level printed circuit board (not shown) affixed to the lower surface of substrate 214 as shown in FIG. 6. Solder balls 216 are preferably comprised of a eutectic tin-lead solder alloy, tin, lead, silver, gold, indium and more preferably a eutectic tin-lead solder alloy.
The substrate 214 is preferably an epoxy-glass laminate, a polyimide tape, a ceramic, a copper alloy leadframe or an aluminum alloy leadframe.
Adhesive material 218 is preferably comprised of a thermally conductive organic/ inorganic filler.
Lower die wires (not shown) may then be attached to the upper surface of lower die/chip 212 and to the upper surface of the substrate 214.
Metal interposer 220 is then substantially centered over the lower die/chip 212 and the upper portion 222 of metal interposer 220 is attached, and electrically grounded, to substrate 214 through leg portions/external support columns 223 as at 238 using adhesive material 218. External support columns 223 are used to support the ring-shaped outer die pad 222 connecting to underlying substrate 214 in place. Metal interposer 220 is a thermally conductive structure.
Metal interposer 220 is preferably comprised of a copper alloy, an aluminum alloy or an iron alloy and is more preferably a copper alloy. Metal interposer 20 is electrically conductive.
Optionally, a thermal glue 240 may be interposed between the upper portion 222 of metal interposer 220 and the upper surface of lower die/chip 212 as shown in FIG. 6. The thermal glue 240 is thermally conductive and permits transfer of heat from the upper die 230 to the lower die 212 or from the lower die 212 to the upper die 230 depending upon the temperature difference.
Upper die/chip 230 is then substantially centered over, and attached to, the upper surfaces of the upper portion 222 of metal interposer 220 using adhesive material 218.
It is noted that the metal interposer 220 is a thermal conductor, permitting heat from the upper die/chip 230 to be taken away from the upper die/chip 230 and into the substrate 214 and away from package 210 through the solder balls or metallized lands 216. Heat also flows from the upper die 230 to the substrate 214 through the legs 223 of the metal interposer 220.
Upper die/chip wires (not shown) may then be attached to the upper surface of upper die/chip 230 and to the upper surface of the substrate 214.
An encapsulate/molding material 236 is then formed around the upper die/chip 230, the upper and lower die/chip wires and over the lower die/chip 212 and the substrate 214 as shown in FIG. 6.
Alternately, the lower and upper die/chip wires may be attached to the respective lower and upper dies/ chips 212, 230 after the lower and upper dies/ chips 212, 230 are affixed to the metal interposer 220. The wires may be attached in one pass (equipment set-up) if the upper die 230 is small along its length and/or width and does not interfere with the wire connection of the lower die 212 to the substrate 214 wiring process. If the upper die/chip 230 has bond pads on only two opposite sides, more support columns could be added, with the limit to the number added being encapsulate/mold 236 flow.
FIG. 7 is a top-down, plan view of FIG. 6, with FIG. 6 being a cross-section of FIG. 7 along line 6—6. FIG. 7 illustrates package 210 having metal interposer 220 electrically grounded to substrate 214 through leg portions/external support columns 223 as at 238. Encapsulant 236 envelopes the metal interposer 220 (and upper and lower die/chips 212, 230 (not shown)).
Fourth Embodiment—Electrically Grounded Metal Interposer 320; FIGS. 9 to 11
As shown in FIGS. 9 to 11, the fourth embodiment of the present invention illustrates a package 310 having another electrically grounded metal interposer with support columns stacked die/chip design.
In the fourth embodiment, metal interposer 320 is affixed, and electrically grounded, to the substantial center of substrate 314 at its lower center portion 321 preferably using adhesive material 318. Metal interposer 320 is a thermally conductive structure and further includes upper portion 322 connected to the lower center portion 321 through leg portions/external support columns 324.
The substrate 314 is preferably an epoxy-glass laminate, a polyimide tape, a ceramic, a copper alloy leadframe or an aluminum alloy leadframe.
Metal interposer 320 is preferably comprised of a copper alloy, an aluminum alloy or an iron alloy and is more preferably a copper alloy. Metal interposer 20 is electrically conductive.
Adhesive material 318 is preferably comprised of a thermally conductive organic/inorganic filler.
Substrate 314 may include solder balls or metallized lands 316 for interconnection to the system level printed circuit board (not shown) affixed to the lower surface of substrate 314 as shown in FIG. 8. Solder balls 316 are preferably comprised of a eutectic tin-lead solder alloy, tin, lead, silver, gold, indium and more preferably a eutectic tin-lead solder alloy.
Lower die/chip 312 is then substantially centered, and attached to, the lower center portion of metal interposer 320 preferably using adhesive material 318.
Lower die wires 326 may then be attached to the upper surface of lower die/chip 312 and to the upper surface of the substrate 314.
Upper die/chip 330 is then substantially centered over, and attached to, the upper surfaces of the upper portion 322 of metal interposer 320 preferably using adhesive material 318.
It is noted that the metal interposer 320 is a thermal conductor, permitting heat from the upper die/chip 330 to be taken away from the upper die/chip 330 and into the substrate 314 and away from package 310 via the leg portions/external support columns 324 through the solder balls or metallized lands 316. Any heat from the lower die/chip 312 may be likewise taken away from the lower die/chip 312 and into the substrate 314 and away from package 310 through the solder balls or metallized lands 316.
Upper die/chip wires 334 may then be attached to the upper surface of upper die/chip 330 and to the upper surface of the substrate 314.
An encapsulate/molding material 336 is then formed around the upper die/chip 330, the upper and lower die/ chip wires 334, 326 and over the lower die/chip 312 and the substrate 314 as shown in FIG. 8.
Alternately, the upper and lower die/ chip wires 334, 326 may be attached to the respective upper and lower dies/chips 332, 312 after the upper and lower dies/ chips 330, 312 are affixed to the metal interposer 320.
If the upper die/chip 330 has bond pads on only two opposite sides, more support columns could be added, with the limit to the number added being encapsulate/mold 336 flow.
FIG. 9 is a top-down, plan view of FIG. 8, with FIG. 8 being a cross-section of FIG. 9 along line 8—8. FIG. 9 illustrates package 310 having metal interposer 320 electrically grounded to substrate 214 through leg portions/external support columns 223 as at 238. Encapsulant 236 envelopes the metal interposer 220 (and upper and lower die/chips 212, 230 (not shown)).
FIG. 10 is top down plan view of a modification of the fourth embodiment wherein the upper portion of the metal interposer 320 comprises four discrete pads 337 the end of each leg portion/support column 324.
It is noted that the stacked die/chip package designs of the embodiments of the present invention have reduced die attach interface area to reduce stress and moisture sensitivity.
Advantages of the Present Invention
The advantages of one or more embodiments of the present invention include:
1. lower mechanical stress for the upper die/chip attachment, especially at the metal interposer to the upper die attachment interface at the die attach area is reduced due to “ring” shape;
2. lower metal interposer to substrate attachment stress as the metal interposer is more preferably comprised of a copper alloy which closely matches in CTE with laminate substrates;
3. optional additional heat removal from the upper or lower die/chip is provided which is very useful in die/chip combinations where the upper die also generates heat;
4. additional support columns may be added as necessary with the limit of support columns being added limited by the encapsulate/mold flow; and
5. upper die/chip grounding is made possible, such upper die/chip grounding also isolates the upper die/chip from the lower die/chip in high frequency operation such as switching noise or interference.
While particular embodiments of the present invention have been illustrated and described, it is not intended to limit the invention, except as defined by the following claims.

Claims (56)

We claim:
1. A stacked die design, comprising:
a substrate having a lower surface and an upper surface;
a lower die connected to the substrate; the lower die having a lower surface and an upper surface;
a thermally conductive metal interposer thermally connected to the substrate; and
an upper die thermally connected to the metal interposer; the upper die having a lower surface and an upper surface; the lower die and the upper die being spaced apart and comprising a stacked die;
whereby any heat generated by the upper die is transferred to the substrate by the metal interposer.
2. The stacked die design of claim 1, wherein the substrate is an epoxy-glass laminate, a polyimide tape, a ceramic, a copper alloy leadframe or an aluminum alloy leadframe.
3. The stacked die design of claim 1, further including solder balls or metallized lands affixed to the lower surface of the substrate; whereby any heat transferred to the substrate is transferred to the solder balls or metallized lands.
4. The stacked die design of claim 1, further including solder balls or metallized lands affixed to the lower surface of the substrate; the solder balls being comprised of a eutectic tin-lead solder alloy, tin, lead, silver, gold, or indium.
5. The stacked die design of claim 1, further including solder balls or metallized lands affixed to the lower surface of the substrate; the solder balls being comprised of a copper alloy.
6. The stacked die design of claim 1, wherein the metal interposer is comprised of a copper alloy, an aluminum alloy or an iron alloy.
7. The stacked die design of claim 1, wherein the metal interposer is comprised of a copper alloy.
8. The stacked die design of claim 1, wherein the metal interposer is interposed between the lower die and the upper die.
9. The stacked die design of claim 1, wherein the metal interposer is interposed between the lower die and the upper die; and the metal interposer being affixed to the upper surface of the lower die and to the lower surface of the upper die.
10. The stacked die design of claim 1, wherein the metal interposer/stacked die is not electrically grounded.
11. The stacked die design of claim 1, wherein the metal interposer is connected to: the upper surface of the substrate; the lower surface of the upper die; and the upper surface of the lower die.
12. The stacked die design of claim 1, wherein the metal interposer is connected to: the upper surface of the substrate; the lower surface of the upper die; and the upper surface of the lower die; whereby the metal interposer is electrically connected to the substrate to ground at least the upper die.
13. The stacked die design of claim 1, wherein the metal interposer is a double down-set metal interposer.
14. The stacked die design of claim 1, wherein the metal interposer is connected to: the upper surface of the substrate; and the lower surface of the upper die.
15. The stacked die design of claim 1, wherein the metal interposer is connected to: the upper surface of the substrate; and the lower surface of the upper die; whereby the metal interposer is electrically connected to the substrate to ground at least the upper die.
16. The stacked die design of claim 1, wherein a thermal glue is interposed between the lower die and the upper die.
17. The stacked die design of claim 1, wherein a thermal glue is interposed between the lower die and the upper die; the thermal glue being thermally conductive and permitting transfer of any heat generated between the upper die and the lower die.
18. The stacked die design of claim 1, wherein the metal interposer is connected to: the upper surface of the substrate; the lower surface of the lower die; and the lower surface of the upper die.
19. The stacked die design of claim 1, wherein the metal interposer is connected to: the upper surface of the substrate; the lower surface of the lower die; and the lower surface of the upper die; whereby the metal interposer is electrically grounded to the substrate to ground the lower and upper dies.
20. A stacked die design, comprising:
a substrate having a lower surface and an upper surface;
a lower die connected to the substrate; the lower die having a lower surface and an upper surface;
a thermally conductive metal interposer thermally connected to the substrate; the metal interposer being comprised of a copper alloy, an aluminum alloy or an iron alloy; and
an upper die thermally connected to the metal interposer; the upper die having a lower surface and an upper surface; the lower die and the upper die being spaced apart and comprising a stacked die;
whereby any heat generated by the upper die is transferred to the substrate by the metal interposer.
21. The stacked die design of claim 20, wherein the substrate is an epoxy-glass laminate, a polyimide tape, a ceramic, a copper alloy leadframe or an aluminum alloy leadframe.
22. The stacked die design of claim 20, further including solder balls or metallized lands affixed to the lower surface of the substrate; whereby any heat transferred to the substrate is transferred to the solder balls or metallized lands.
23. The stacked die design of claim 20, further including solder balls or metallized lands affixed to the lower surface of the substrate; the solder balls being comprised of a eutectic tin-lead solder alloy, tin, lead, silver, gold, or indium.
24. The stacked die design of claim 20, further including solder balls or metallized lands affixed to the lower surface of the substrate; the solder balls being comprised of a copper alloy.
25. The stacked die design of claim 20, wherein the metal interposer is comprised of a copper alloy.
26. The stacked die design of claim 20, wherein the metal interposer is interposed between the lower die and the upper die.
27. The stacked die design of claim 20, wherein the metal interposer is interposed between the lower die and the upper die; and the metal interposer being affixed to the upper surface of the lower die and to the lower surface of the upper die.
28. The stacked die design of claim 20, wherein the metal interposer/stacked die is not electrically grounded.
29. The stacked die design of claim 20, wherein the metal interposer is connected to: the upper surface of the substrate; the lower surface of the upper die; and the upper surface of the lower die.
30. The stacked die design of claim 20, wherein the metal interposer is connected to: the upper surface of the substrate; the lower surface of the upper die; and the upper surface of the lower die; whereby the metal interposer is electrically connected to the substrate to ground at least the upper die.
31. The stacked die design of claim 20, wherein the metal interposer is a double down-set metal interposer.
32. The stacked die design of claim 20, wherein the metal interposer is connected to: the upper surface of the substrate; and the lower surface of the upper die.
33. The stacked die design of claim 20, wherein the metal interposer is connected to: the upper surface of the substrate; and the lower surface of the upper die; whereby the metal interposer is electrically connected to the substrate to ground at least the upper die.
34. The stacked die design of claim 20, wherein a thermal glue is interposed between the lower die and the upper die.
35. The stacked die design of claim 20, wherein a thermal glue is interposed between the lower die and the upper die; the thermal glue being thermally conductive and permitting transfer of any heat generated between the upper die and the lower die.
36. The stacked die design of claim 20, wherein the metal interposer is connected to: the upper surface of the substrate; the lower surface of the lower die; and the lower surface of the upper die.
37. The stacked die design of claim 20, wherein the metal interposer is connected to: the upper surface of the substrate; the lower surface of the lower die; and the lower surface of the upper die; whereby the metal interposer is electrically grounded to the substrate to ground the lower and upper dies.
38. A method of forming a stacked die design, comprising:
providing a substrate having a lower surface and an upper surface;
providing a lower die connected to the substrate; the lower die having a lower surface and an upper surface;
providing a thermally conductive metal interposer thermally connected to the substrate; and
providing an upper die thermally connected to the metal interposer; the upper die having a lower surface and an upper surface; the lower die and the upper die being spaced apart and comprising a stacked die;
whereby any heat generated by the upper die is transferred to the substrate by the metal interposer.
39. The method of claim 38, wherein the substrate is an epoxy-glass laminate, a polyimide tape, a ceramic, a copper alloy leadframe or an aluminum alloy leadframe.
40. The method of claim 38, further including affixing solder balls or metallized lands affixed to the lower surface of the substrate; whereby any heat transferred to the substrate is transferred to the solder balls or metallized lands.
41. The method of claim 38, further including affixing solder balls or metallized lands affixed to the lower surface of the substrate; the solder balls being comprised of a eutectic tin-lead solder alloy, tin, lead, silver, gold, or indium.
42. The method of claim 38, further including affixing solder balls or metallized lands affixed to the lower surface of the substrate; the solder balls being comprised of a copper alloy.
43. The method of claim 38, wherein the metal interposer is comprised of a copper alloy, an aluminum alloy or an iron alloy.
44. The method of claim 38, wherein the metal interposer is comprised of a copper alloy.
45. The method of claim 38, wherein the metal interposer is interposed between the lower die and the upper die.
46. The method of claim 38, wherein the metal interposer is interposed between the lower die and the upper die; and the metal interposer being affixed to the upper surface of the lower die and to the lower surface of the upper die.
47. The method of claim 38, wherein the metal interposer/stacked die is not electrically grounded.
48. The method of claim 38, wherein the metal interposer is connected to: the upper surface of the substrate; the lower surface of the upper die; and the upper surface of the lower die.
49. The method of claim 38, wherein the metal interposer is connected to: the upper surface of the substrate; the lower surface of the upper die; and the upper surface of the lower die; whereby the metal interposer is electrically connected to the substrate to ground at least the upper die.
50. The method of claim 38, wherein the metal interposer is a double down-set metal interposer.
51. The method of claim 38, wherein the metal interposer is connected to: the upper surface of the substrate; and the lower surface of the upper die.
52. The method of claim 38, wherein the metal interposer is connected to: the upper surface of the substrate; and the lower surface of the upper die; whereby the metal interposer is electrically connected to the substrate to ground at least the upper die.
53. The method of claim 38, wherein a thermal glue is interposed between the lower die and the upper die.
54. The method of claim 38, wherein a thermal glue is interposed between the lower die and the upper die; the thermal glue being thermally conductive and permitting transfer of any heat generated between the upper die and the lower die.
55. The method of claim 38, wherein the metal interposer is connected to: the upper surface of the substrate; the lower surface of the lower die; and the lower surface of the upper die.
56. The method of claim 38, wherein the metal interposer is connected to: the upper surface of the substrate; the lower surface of the lower die; and the lower surface of the upper die; whereby the metal interposer is electrically grounded to the substrate to ground the lower and upper dies.
US10/359,407 2003-02-06 2003-02-06 Thermally enhanced stacked die package Expired - Lifetime US6627990B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US10/359,407 US6627990B1 (en) 2003-02-06 2003-02-06 Thermally enhanced stacked die package
SG200400190A SG113495A1 (en) 2003-02-06 2004-01-15 Thermally enhanced stacked die package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/359,407 US6627990B1 (en) 2003-02-06 2003-02-06 Thermally enhanced stacked die package

Publications (1)

Publication Number Publication Date
US6627990B1 true US6627990B1 (en) 2003-09-30

Family

ID=28454578

Family Applications (1)

Application Number Title Priority Date Filing Date
US10/359,407 Expired - Lifetime US6627990B1 (en) 2003-02-06 2003-02-06 Thermally enhanced stacked die package

Country Status (2)

Country Link
US (1) US6627990B1 (en)
SG (1) SG113495A1 (en)

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040061146A1 (en) * 2002-09-30 2004-04-01 Shiann-Tsong Tsai Multi-chip semiconductor package and fabrication method thereof
US20040195591A1 (en) * 2002-11-22 2004-10-07 John Gehman Digital and RF system and method therefor
US20050230800A1 (en) * 2004-04-16 2005-10-20 St Assembly Test Services Ltd. Thermally enhanced stacked die package and fabrication method
US20060006517A1 (en) * 2004-07-08 2006-01-12 Lee Jin-Yang Multi-chip package having heat dissipating path
US20060071345A1 (en) * 2004-09-30 2006-04-06 Stmicroelectronics, Inc. Copper interposer for reducing warping of integrated circuit packages and method of making IC packages
WO2008016333A1 (en) * 2006-08-03 2008-02-07 Stats Chippac Ltd Integrated circuit package-on-package stacking system
US20080054433A1 (en) * 2006-09-05 2008-03-06 Samsung Electronics Co., Ltd. Multi-chip package with spacer for blocking interchip heat transfer
US20080150106A1 (en) * 2006-12-22 2008-06-26 United Test And Assembly Center, Ltd. Inverted lf in substrate
US20100001081A1 (en) * 2007-03-23 2010-01-07 Fujitsu Limited Electronic device, electronic apparatus mounted with electronic device, article equipped with electronic device and method of producing electronic device
US20100258928A1 (en) * 2009-04-14 2010-10-14 Chi Heejo Integrated circuit packaging system with stacked integrated circuit and method of manufacture thereof
US7829986B2 (en) * 2006-04-01 2010-11-09 Stats Chippac Ltd. Integrated circuit package system with net spacer
EP2381472A1 (en) * 2010-04-26 2011-10-26 Commissariat à l'Énergie Atomique et aux Énergies Alternatives Method for manufacturing a microelectronic device and microelectronic device thus manufactured
US20120043116A1 (en) * 2010-08-23 2012-02-23 Samsung Electronics Co., Ltd. Interconnection Structure Of Interposer With Low CTE And Packaging Component Having The Same
US8525334B2 (en) 2010-04-27 2013-09-03 International Rectifier Corporation Semiconductor on semiconductor substrate multi-chip-scale package
US8569870B1 (en) 2012-06-25 2013-10-29 Stats Chippac Ltd. Integrated circuit packaging system with shielding spacer and method of manufacture thereof
WO2015086184A1 (en) * 2013-12-13 2015-06-18 Abb Technology Ag Semiconductor stack arrangement and semiconductor module

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5814881A (en) * 1996-12-20 1998-09-29 Lsi Logic Corporation Stacked integrated chip package and method of making same
US6080264A (en) * 1996-05-20 2000-06-27 Micron Technology, Inc. Combination of semiconductor interconnect
US6087718A (en) * 1996-12-27 2000-07-11 Lg Semicon Co., Ltd. Stacking type semiconductor chip package
US6087722A (en) * 1998-05-28 2000-07-11 Samsung Electronics Co., Ltd. Multi-chip package
US6118176A (en) * 1999-04-26 2000-09-12 Advanced Semiconductor Engineering, Inc. Stacked chip assembly utilizing a lead frame
US6261865B1 (en) * 1998-10-06 2001-07-17 Micron Technology, Inc. Multi chip semiconductor package and method of construction
US6297547B1 (en) * 1998-02-13 2001-10-02 Micron Technology Inc. Mounting multiple semiconductor dies in a package
US6307257B1 (en) * 1999-05-14 2001-10-23 Siliconware Precision Industries, Co., Ltd. Dual-chip integrated circuit package with a chip-die pad formed from leadframe leads
US6337521B1 (en) * 1999-09-22 2002-01-08 Hitachi, Ltd. Semiconductor device and a method of manufacturing the same

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6080264A (en) * 1996-05-20 2000-06-27 Micron Technology, Inc. Combination of semiconductor interconnect
US5814881A (en) * 1996-12-20 1998-09-29 Lsi Logic Corporation Stacked integrated chip package and method of making same
US6087718A (en) * 1996-12-27 2000-07-11 Lg Semicon Co., Ltd. Stacking type semiconductor chip package
US6297547B1 (en) * 1998-02-13 2001-10-02 Micron Technology Inc. Mounting multiple semiconductor dies in a package
US6087722A (en) * 1998-05-28 2000-07-11 Samsung Electronics Co., Ltd. Multi-chip package
US6261865B1 (en) * 1998-10-06 2001-07-17 Micron Technology, Inc. Multi chip semiconductor package and method of construction
US6118176A (en) * 1999-04-26 2000-09-12 Advanced Semiconductor Engineering, Inc. Stacked chip assembly utilizing a lead frame
US6307257B1 (en) * 1999-05-14 2001-10-23 Siliconware Precision Industries, Co., Ltd. Dual-chip integrated circuit package with a chip-die pad formed from leadframe leads
US6337521B1 (en) * 1999-09-22 2002-01-08 Hitachi, Ltd. Semiconductor device and a method of manufacturing the same

Cited By (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6825064B2 (en) * 2002-09-30 2004-11-30 Ultratera Corporation Multi-chip semiconductor package and fabrication method thereof
US20040061146A1 (en) * 2002-09-30 2004-04-01 Shiann-Tsong Tsai Multi-chip semiconductor package and fabrication method thereof
US7479407B2 (en) * 2002-11-22 2009-01-20 Freescale Semiconductor, Inc. Digital and RF system and method therefor
US20040195591A1 (en) * 2002-11-22 2004-10-07 John Gehman Digital and RF system and method therefor
US20050230800A1 (en) * 2004-04-16 2005-10-20 St Assembly Test Services Ltd. Thermally enhanced stacked die package and fabrication method
US7205651B2 (en) 2004-04-16 2007-04-17 St Assembly Test Services Ltd. Thermally enhanced stacked die package and fabrication method
US20070148821A1 (en) * 2004-04-16 2007-06-28 Byung Tai Do Thermally enhanced stacked die package and fabrication method
US20060006517A1 (en) * 2004-07-08 2006-01-12 Lee Jin-Yang Multi-chip package having heat dissipating path
US20060071345A1 (en) * 2004-09-30 2006-04-06 Stmicroelectronics, Inc. Copper interposer for reducing warping of integrated circuit packages and method of making IC packages
US7196425B2 (en) * 2004-09-30 2007-03-27 Stmicroelectronics, Inc. Copper interposer for reducing warping of integrated circuit packages and method of making IC packages
US7829986B2 (en) * 2006-04-01 2010-11-09 Stats Chippac Ltd. Integrated circuit package system with net spacer
US20080029858A1 (en) * 2006-08-03 2008-02-07 Stats Chippac Ltd. Integrated circuit package-on-package stacking system
US7535086B2 (en) 2006-08-03 2009-05-19 Stats Chippac Ltd. Integrated circuit package-on-package stacking system
US20090179312A1 (en) * 2006-08-03 2009-07-16 Merilo Dioscoro A Integrated circuit package-on-package stacking system
WO2008016333A1 (en) * 2006-08-03 2008-02-07 Stats Chippac Ltd Integrated circuit package-on-package stacking system
US7868434B2 (en) 2006-08-03 2011-01-11 Stats Chippac Ltd. Integrated circuit package-on-package stacking system
US7718472B2 (en) 2006-08-03 2010-05-18 Stats Chippac Ltd. Integrated circuit package-on-package stacking system and method of manufacture thereof
US20100176497A1 (en) * 2006-08-03 2010-07-15 Merilo Dioscoro A Integrated circuit package-on-package stacking system
US8698304B2 (en) 2006-09-05 2014-04-15 Samsung Electronics Co., Ltd. Multi-chip package with spacer for blocking interchip heat transfer
US20080054433A1 (en) * 2006-09-05 2008-03-06 Samsung Electronics Co., Ltd. Multi-chip package with spacer for blocking interchip heat transfer
US7642638B2 (en) * 2006-12-22 2010-01-05 United Test And Assembly Center Ltd. Inverted lead frame in substrate
US20080150106A1 (en) * 2006-12-22 2008-06-26 United Test And Assembly Center, Ltd. Inverted lf in substrate
US7789316B2 (en) * 2007-03-23 2010-09-07 Fujitsu Limited Electronic device, electronic apparatus mounted with electronic device, article equipped with electronic device and method of producing electronic device
US20100001081A1 (en) * 2007-03-23 2010-01-07 Fujitsu Limited Electronic device, electronic apparatus mounted with electronic device, article equipped with electronic device and method of producing electronic device
US20100258928A1 (en) * 2009-04-14 2010-10-14 Chi Heejo Integrated circuit packaging system with stacked integrated circuit and method of manufacture thereof
US8039316B2 (en) 2009-04-14 2011-10-18 Stats Chippac Ltd. Integrated circuit packaging system with stacked integrated circuit and heat spreader with openings and method of manufacture thereof
EP2381472A1 (en) * 2010-04-26 2011-10-26 Commissariat à l'Énergie Atomique et aux Énergies Alternatives Method for manufacturing a microelectronic device and microelectronic device thus manufactured
US8530276B2 (en) 2010-04-26 2013-09-10 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method for manufacturing a microelectronic device and a microelectronic device thus manufactured
US8525334B2 (en) 2010-04-27 2013-09-03 International Rectifier Corporation Semiconductor on semiconductor substrate multi-chip-scale package
US20120043116A1 (en) * 2010-08-23 2012-02-23 Samsung Electronics Co., Ltd. Interconnection Structure Of Interposer With Low CTE And Packaging Component Having The Same
CN102376688A (en) * 2010-08-23 2012-03-14 三星电子株式会社 Interconnection structure for interposer and packaging component having the same
US8569870B1 (en) 2012-06-25 2013-10-29 Stats Chippac Ltd. Integrated circuit packaging system with shielding spacer and method of manufacture thereof
WO2015086184A1 (en) * 2013-12-13 2015-06-18 Abb Technology Ag Semiconductor stack arrangement and semiconductor module

Also Published As

Publication number Publication date
SG113495A1 (en) 2005-08-29

Similar Documents

Publication Publication Date Title
US6630373B2 (en) Ground plane for exposed package
US6781242B1 (en) Thin ball grid array package
US6818980B1 (en) Stacked semiconductor package and method of manufacturing the same
US6404049B1 (en) Semiconductor device, manufacturing method thereof and mounting board
US7342305B1 (en) Thermally enhanced cavity-down integrated circuit package
US6201302B1 (en) Semiconductor package having multi-dies
US6545347B2 (en) Enhanced leadless chip carrier
US6853070B2 (en) Die-down ball grid array package with die-attached heat spreader and method for making the same
US6597059B1 (en) Thermally enhanced chip scale lead on chip semiconductor package
US7259457B2 (en) Die-up ball grid array package including a substrate capable of mounting an integrated circuit die and method for making the same
US6984878B2 (en) Leadless leadframe with an improved die pad for mold locking
US6723585B1 (en) Leadless package
JP5227501B2 (en) Stack die package and method of manufacturing the same
US7253508B2 (en) Semiconductor package with a flip chip on a solder-resist leadframe
US20020158318A1 (en) Multi-chip module
US6627990B1 (en) Thermally enhanced stacked die package
US20040061202A1 (en) Leadframe for die stacking applications and related die stacking concepts
US7361995B2 (en) Molded high density electronic packaging structure for high performance applications
KR101685068B1 (en) System in package and method for manufacturing the same
KR20140045461A (en) Integrated circuit package
US20050194698A1 (en) Integrated circuit package with keep-out zone overlapping undercut zone
US20060231960A1 (en) Non-cavity semiconductor packages
KR100473336B1 (en) semiconductor package
KR101185854B1 (en) Semiconductor package
KR20140045248A (en) Integrated circuit package and method for manufacturing the same

Legal Events

Date Code Title Description
AS Assignment

Owner name: ST ASSEMBLY TEST SERVICES PTE LTD, SINGAPORE

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SHIM, IL KWON;RAMAKRISHNA, KAMBHAMPATI;CHOW, SENG GUAN;REEL/FRAME:013749/0909

Effective date: 20030124

STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12

AS Assignment

Owner name: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT, HONG KONG

Free format text: SECURITY INTEREST;ASSIGNORS:STATS CHIPPAC, INC.;STATS CHIPPAC LTD.;REEL/FRAME:036288/0748

Effective date: 20150806

Owner name: STATS CHIPPAC LTD., SINGAPORE

Free format text: CHANGE OF NAME;ASSIGNOR:ST ASSEMBLY TEST SERVICES LTD.;REEL/FRAME:036286/0590

Effective date: 20040608

Owner name: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY

Free format text: SECURITY INTEREST;ASSIGNORS:STATS CHIPPAC, INC.;STATS CHIPPAC LTD.;REEL/FRAME:036288/0748

Effective date: 20150806

AS Assignment

Owner name: STATS CHIPPAC PTE. LTE., SINGAPORE

Free format text: CHANGE OF NAME;ASSIGNOR:STATS CHIPPAC LTD.;REEL/FRAME:038378/0400

Effective date: 20160329

AS Assignment

Owner name: STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD., SINGAPORE

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT;REEL/FRAME:052950/0497

Effective date: 20190503

Owner name: STATS CHIPPAC, INC., CALIFORNIA

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT;REEL/FRAME:052950/0497

Effective date: 20190503

AS Assignment

Owner name: STATS CHIPPAC PTE. LTD., DISTRICT OF COLUMBIA

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S NAME PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0400. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT;ASSIGNOR:STATS CHIPPAC LTD.;REEL/FRAME:064806/0593

Effective date: 20160329