US6671862B1 - Method and apparatus for simplifying a circuit model - Google Patents
Method and apparatus for simplifying a circuit model Download PDFInfo
- Publication number
- US6671862B1 US6671862B1 US10/213,960 US21396002A US6671862B1 US 6671862 B1 US6671862 B1 US 6671862B1 US 21396002 A US21396002 A US 21396002A US 6671862 B1 US6671862 B1 US 6671862B1
- Authority
- US
- United States
- Prior art keywords
- circuit
- model
- active device
- input
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
Claims (20)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/213,960 US6671862B1 (en) | 2002-08-07 | 2002-08-07 | Method and apparatus for simplifying a circuit model |
GB0317109A GB2391660A (en) | 2002-08-07 | 2003-07-22 | Simplifying a circuit model by removing parasitic capacitance and resistance based on time constant values |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/213,960 US6671862B1 (en) | 2002-08-07 | 2002-08-07 | Method and apparatus for simplifying a circuit model |
Publications (1)
Publication Number | Publication Date |
---|---|
US6671862B1 true US6671862B1 (en) | 2003-12-30 |
Family
ID=27788758
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/213,960 Expired - Lifetime US6671862B1 (en) | 2002-08-07 | 2002-08-07 | Method and apparatus for simplifying a circuit model |
Country Status (2)
Country | Link |
---|---|
US (1) | US6671862B1 (en) |
GB (1) | GB2391660A (en) |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060031055A1 (en) * | 2004-04-07 | 2006-02-09 | Sheehan Bernard N | Branch merge reduction of RLCM networks |
US7137089B1 (en) * | 2004-09-01 | 2006-11-14 | National Semiconductor Corporation | Systems and methods for reducing IR-drop noise |
US20070299647A1 (en) * | 2005-07-26 | 2007-12-27 | Mentor Graphics Corporation | Accelerated Analog and/or Rf Simulation |
US20090206493A1 (en) * | 2003-11-08 | 2009-08-20 | Stats Chippac, Ltd. | Flip Chip Interconnection Pad Layout |
US20110074047A1 (en) * | 2003-11-08 | 2011-03-31 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Pad Layout for Flipchip Semiconductor Die |
US8392867B2 (en) | 2011-01-13 | 2013-03-05 | International Business Machines Corporation | System, method and program storage device for developing condensed netlists representative of groups of active devices in an integrated circuit and for modeling the performance of the integrated circuit based on the condensed netlists |
JP2014182430A (en) * | 2013-03-18 | 2014-09-29 | Fujitsu Ltd | Design support device, design support program, and design support method |
US10402532B1 (en) * | 2016-04-07 | 2019-09-03 | Cadence Design Systems, Inc. | Methods, systems, and computer program products for implementing an electronic design with electrical analyses with compensation circuit components |
US10521529B2 (en) * | 2016-06-21 | 2019-12-31 | Realtek Semiconductor Corp. | Simulation method for mixed-signal circuit system and related electronic device |
US10672439B2 (en) * | 2018-07-10 | 2020-06-02 | Globalfoundries Inc. | Data dependent keeper on global data lines |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5638294A (en) * | 1993-12-21 | 1997-06-10 | Mitsubishi Denki Kabushiki Kaisha | Device and method for calculating delay time |
US5699264A (en) * | 1995-12-12 | 1997-12-16 | Mitsubishi Electric Semiconductor Software Co., Ltd. | Semiconductor circuit design verifying apparatus |
US5875114A (en) * | 1996-08-27 | 1999-02-23 | Mitsubishi Denki Kabushiki Kaisha | Interconnect delay calculation apparatus and path delay value verification apparatus for designing semiconductor integrated circuit and circuit model data storage device |
US6463574B1 (en) * | 1998-06-12 | 2002-10-08 | Sun Microsystems, Inc. | Apparatus and method for inserting repeaters into a complex integrated circuit |
US6463570B1 (en) * | 2000-07-26 | 2002-10-08 | Advanced Micro Devices | Apparatus and method for verifying process integrity |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0831111B2 (en) * | 1990-11-27 | 1996-03-27 | 三菱電機株式会社 | Layout pattern verification system |
JPH1092938A (en) * | 1996-09-10 | 1998-04-10 | Fujitsu Ltd | Layout method, layout apparatus and database |
-
2002
- 2002-08-07 US US10/213,960 patent/US6671862B1/en not_active Expired - Lifetime
-
2003
- 2003-07-22 GB GB0317109A patent/GB2391660A/en not_active Withdrawn
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5638294A (en) * | 1993-12-21 | 1997-06-10 | Mitsubishi Denki Kabushiki Kaisha | Device and method for calculating delay time |
US5699264A (en) * | 1995-12-12 | 1997-12-16 | Mitsubishi Electric Semiconductor Software Co., Ltd. | Semiconductor circuit design verifying apparatus |
US5875114A (en) * | 1996-08-27 | 1999-02-23 | Mitsubishi Denki Kabushiki Kaisha | Interconnect delay calculation apparatus and path delay value verification apparatus for designing semiconductor integrated circuit and circuit model data storage device |
US6463574B1 (en) * | 1998-06-12 | 2002-10-08 | Sun Microsystems, Inc. | Apparatus and method for inserting repeaters into a complex integrated circuit |
US6463570B1 (en) * | 2000-07-26 | 2002-10-08 | Advanced Micro Devices | Apparatus and method for verifying process integrity |
Non-Patent Citations (4)
Title |
---|
A.J. van Genderen & N.P. van der Meijs; Extracting Simple But Accurate RC Models For VLSI Interconnection; 1988 IEEE International Symposium On Circuits And Systems; pp. 2351-2354; Jun. 7-9, 1988. |
Anirudh Devgan & Peter R. O'Brien; Realizable Reduction For RC Interconnect Circuits; 1999 IEEE/ACM International Conference On Computer-Aided Design; pp. 204-207; Nov. 7-11, 1999. |
Bernard N. Sheehan; TICER: Realizable Reduction Of Extracted RC Circuits; 1999 IEEE/ACM International Conference On Computer-Aided Design; pp. 200-203; Nov. 7-11, 1999. |
Shun-Lin Su, Vasant B. Rao, & Timothy N. Trick; A Simple And Accurate Node Reduction Technique For Interconnect Modeling In Circuit Extraction; IEEE International Conference On Computer-Aided Design, ICCAD-86 Digest of Technical Papers; pp. 270-273; Nov. 11-13, 1986. |
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9780057B2 (en) | 2003-11-08 | 2017-10-03 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming pad layout for flipchip semiconductor die |
US8129837B2 (en) | 2003-11-08 | 2012-03-06 | Stats Chippac, Ltd. | Flip chip interconnection pad layout |
US20110074047A1 (en) * | 2003-11-08 | 2011-03-31 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Pad Layout for Flipchip Semiconductor Die |
US20090206493A1 (en) * | 2003-11-08 | 2009-08-20 | Stats Chippac, Ltd. | Flip Chip Interconnection Pad Layout |
US7774174B2 (en) * | 2004-04-07 | 2010-08-10 | Mentor Graphics Corporation | Branch merge reduction of RLCM networks |
US20060031055A1 (en) * | 2004-04-07 | 2006-02-09 | Sheehan Bernard N | Branch merge reduction of RLCM networks |
US7137089B1 (en) * | 2004-09-01 | 2006-11-14 | National Semiconductor Corporation | Systems and methods for reducing IR-drop noise |
US20070001234A1 (en) * | 2004-09-01 | 2007-01-04 | Kong Myung J | Systems and methods for reducing IR-drop noise |
US7546557B2 (en) | 2004-09-01 | 2009-06-09 | National Semiconductor Corporation | Systems and methods for reducing IR-drop noise |
US20070299647A1 (en) * | 2005-07-26 | 2007-12-27 | Mentor Graphics Corporation | Accelerated Analog and/or Rf Simulation |
US8700377B2 (en) * | 2005-07-26 | 2014-04-15 | Mentor Graphics Corporation | Accelerated analog and/or RF simulation |
US8392867B2 (en) | 2011-01-13 | 2013-03-05 | International Business Machines Corporation | System, method and program storage device for developing condensed netlists representative of groups of active devices in an integrated circuit and for modeling the performance of the integrated circuit based on the condensed netlists |
JP2014182430A (en) * | 2013-03-18 | 2014-09-29 | Fujitsu Ltd | Design support device, design support program, and design support method |
US10402532B1 (en) * | 2016-04-07 | 2019-09-03 | Cadence Design Systems, Inc. | Methods, systems, and computer program products for implementing an electronic design with electrical analyses with compensation circuit components |
US10521529B2 (en) * | 2016-06-21 | 2019-12-31 | Realtek Semiconductor Corp. | Simulation method for mixed-signal circuit system and related electronic device |
US10672439B2 (en) * | 2018-07-10 | 2020-06-02 | Globalfoundries Inc. | Data dependent keeper on global data lines |
Also Published As
Publication number | Publication date |
---|---|
GB0317109D0 (en) | 2003-08-27 |
GB2391660A (en) | 2004-02-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: HEWLETT-PACKARD COMPANY, COLORADO Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SEWARD, ROBERT Y.;REEL/FRAME:013561/0720 Effective date: 20020829 |
|
AS | Assignment |
Owner name: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P., COLORAD Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HEWLETT-PACKARD COMPANY;REEL/FRAME:013776/0928 Effective date: 20030131 Owner name: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.,COLORADO Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HEWLETT-PACKARD COMPANY;REEL/FRAME:013776/0928 Effective date: 20030131 |
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Free format text: PATENTED CASE |
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Year of fee payment: 4 |
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Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.;HEWLETT-PACKARD COMPANY;REEL/FRAME:026198/0139 Effective date: 20101019 |
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