US6723643B1 - Method for chemical mechanical polishing of thin films using end-point indicator structures - Google Patents

Method for chemical mechanical polishing of thin films using end-point indicator structures Download PDF

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US6723643B1
US6723643B1 US10/391,435 US39143503A US6723643B1 US 6723643 B1 US6723643 B1 US 6723643B1 US 39143503 A US39143503 A US 39143503A US 6723643 B1 US6723643 B1 US 6723643B1
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cmp
layer
depositing
substrate
cmr
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Wei Pan
David R. Evans
Allen W. Burmaster
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Xenogenic Development LLC
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Sharp Laboratories of America Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Patterning of the switching material
    • H10N70/066—Patterning of the switching material by filling of openings, e.g. damascene method
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8836—Complex metal oxides, e.g. perovskites, spinels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/31—Material having complex metal oxide, e.g. perovskite structure

Definitions

  • This Application is related to Device and method for reversible resistance change induced by electric pulses in non-crystalline perovskite unipolar programmable memory; Ser. No. 10/072,225, filed Feb. 7, 2002.
  • This invention relates to CMP processes for use in fabrication of integrated circuits generally, and specifically to CMP used to fabricate a non-volatile resistance RAM structure and CMOS processes to make the memory devices, particularly CMR/PCMO devices.
  • CMR Colossal Magnetoresistance
  • PCMO Pr 0.7 CaO 0.3 MnO 3
  • RRAM novel non-volatile resistance random access memory
  • a PCMO thin film has been grown on both epitaxial YBa 2 Cu 3 O 7 (YBCO) and partial epitaxial Pt substrates via pulsed laser abrasion (PLA) technique, Liu et al., Electric - pulse - induced reversible resistance change effect in magnetoresistive films, Applied Physics Letters, 76, 2749, 2000; and Liu et al., U.S. Pat. No. 6,204,139, granted Mar. 20, 2001, for Method of switching the properties of perovskite materials used in thin film resistors.
  • X-Ray diffraction (XRD) polar figures confirm the epitaxial properties of PCMO thin films.
  • Liu et al. A new concept for non - volatile memory: the electric - pulse induced resistive change effect in Colossal Magnetoresistive thin films, JPL Publication 01-15; Non-Volatile Memory Technology Symposium 2001; November, 2001, pp 18-24, provides additional research information in the field of CMR-containing integrated circuits.
  • U.S. Pat. No. 6,204,139 describes the resistance change which occurred when electric pulses are applied at room temperature to PCMO thin films.
  • the PCMO thin films were deposited on both epitaxial YBa 2 Cu 3 O 7 (YBCO) and partial epitaxial Pt substrates by pulsed laser deposition (PLD).
  • YBCO epitaxial YBa 2 Cu 3 O 7
  • PLD pulsed laser deposition
  • a method of CMP thin films during fabrication of IC devices includes preparing a substrate, including building IC component structures on the substrate; depositing a bottom electrode on the substrate; depositing a first CMP layer having a first known CMP selectivity on the substrate; patterning the first CMP layer to form a pattern having a lower margin; forming indicator structures on the first CMP layer in the pattern; depositing a second CMP layer having a second known CMP selectivity relative to that of the first CMP layer, including depositing portions of the second CMP layer in the pattern of the first CMP layer; CMP the structure so that the indicator structures are removed and any portion of the first CMP layer and second CMP layer are removed to a level corresponding to the lower margin; and completing the IC structure.
  • Another object of the invention is to provide a method for CMP of CMR materials formed on oxide layers or nitride layers.
  • a further object of the invention is to provide for CMP of CMR materials with a silica and ammonium hydroxide slurry.
  • FIG. 1 depicts a prior art RRAM cell having a damascene structure for PCMO deposition.
  • FIG. 2 is a schematic representation of metal patterns which are pre-laid under CMR films for CMP CMR end point detection.
  • FIGS. 3-7 depict steps in an end-point-structure-making process.
  • FIGS. 8-10 are photos of various steps in the method of the invention.
  • the method of the invention provides a practical method for end point detecting as well as colossal magnetoresistive (CMR) thickness control in chemical mechanical polishing (CMP) CMR-containing IC devices.
  • CMR colossal magnetoresistive
  • CMP chemical mechanical polishing
  • an integrated circuit substrate 10 has any number of IC components formed thereon, including a bottom electrode 12 , and an oxide or nitride layer 14 , referred to herein as a first CMP layer having a known CMP selectivity.
  • a damascene trench 16 is formed in the first CMP layer, exposing a portion of the upper surface of bottom electrode 12 .
  • special patterned end-point indicator structures 18 are laid down before the deposition of a CMR film 20 , which indicator structures may be seen to extend upwardly into the CMR, or other IC film.
  • Indicator structures 18 may also be formed under “dented” portions of the overlying IC film layer.
  • CMR material is transparent in thin layers, therefor, the indicator structures may be seen though the overlying CMR layer.
  • This pattern is gradually polished off during CMP of the CMR film. The end point of CMP is obtained when indicator structure 18 pattern is gone, resulting in a portion of the CMR layer and first CMP layer being removed by CMP, until indicator structures are gone, leaving the CMR layer only in trench 16 .
  • the method of the invention is described in connection with a preferred embodiment relating to a specific type of IC component, e.g., PCMO, the method of the invention is not limited to use with the IC component used as an example, and may be applied to an IC fabrication.
  • the method of the invention is a process that constructs the end-point indicator structures on the wafer surface includes the following steps:
  • substrate 10 includes any number of IC structures, including a bottom electrode 12 , e.g., a platinum bottom electrode.
  • An oxide or nitride first CMP layer 14 is formed over the substrate and bottom electrode. Layer 14 is also referred to herein as a first CMP layer.
  • a trench 16 is formed in first CMP layer 14 .
  • a photo resist layer 22 is applied to the wafer. The photo resist is pattered with a metal mask 24 which contains an end-point structure pattern.
  • the wafer is placed in a buffered oxide etch (BOE) 50:1 after being developed for one to two minutes. This will provide an etched step of between about 20 nm to 40 nm in depth.
  • BOE buffered oxide etch
  • a metal indicator layer 26 is deposited, e.g., titanium to a thickness of about 5 nm or aluminum to a thickness of about 10 nm, with PVD being the accepted method for such deposition. E-beam evaporation is one technique which is appropriate for this purpose.
  • the metal-coated wafers are dipped into a photoresist removal solution, e.g., acetone or EKC, resulting in the structure of FIG. 5, having indicator structures 28 formed in trenches in first CMP layer 14 .
  • a photoresist removal solution e.g., acetone or EKC
  • a layer of CMR material 30 is deposited in the structure.
  • layer 30 may be any material which is (1) required to be partially removed or smoothed by CMP; and (2) has a known CMP selectivity relative to the CMP selectivity of layer 14 .
  • Layer 30 is also referred to herein as a second CMP layer.
  • layer 14 the first CMP layer, has a first known CMP selectivity
  • Layer 14 may be silicon dioxide or silicon nitride.
  • Layer 30 is a second CMP layer having a second known CMP selectivity relative to the first known CMP selectivity.
  • SiO 2 PCMO and SiN
  • SiO 2 polishes at a CMP rate faster than PCMO
  • Other CMR materials polish at about the same rate as PCMO.
  • CMP is performed in a slurry which will work on oxide, nitride and CMR materials.
  • the method of the invention uses a silica+ammonium hydroxide (NH 4 OH) slurry, which has been found to be effective on CMR materials as well as on SiO 2 and SiN.
  • CMP continues until end-point indicator structures 28 are removed, indicating that the CMP is complete and that a desired amount of the CMR has been removed.
  • FIG. 7 the structure is depicted after CMP, wherein only a portion of first CMP layer 14 remains, with trench 16 being filled with CMR material 30 .
  • the indicator structures, the upper portion of CMR layer 30 and a portion of first CMP layer 14 have been removed by CMP, which is performed until the indicator structures are removed.
  • FIG. 8 is a photo of an indicator structure 28 , formed on a SiN layer 32 , which has a transparent PCMO CMR layer 34 deposited thereon. A trench 16 is also filled with PCMO CMR material.
  • FIG. 9 depicts partial removal of PCMO CMR layer 34 outside of trench 16 and partial removal of indicator structure 28 . In FIG. 10, all that remains in PCMO CMR material 34 in trench 16 and SiN layer 32 . Careful observation of the demise of indicator structures 28 provides a positive indicator of the extend of the CMP process, and provides an indicator which is used to stop the CMP process before the CMP process removes significant portions of the first CMP layer.

Abstract

A method of CMP thin films during fabrication of IC devices includes preparing a substrate, including building IC component structures on the substrate; depositing a bottom electrode on the substrate; depositing a first CMP layer having a first known CMP selectivity on the substrate; patterning the first CMP layer to form a pattern having a lower margin; forming indicator structures on the first CMP layer in the pattern; depositing a second CMP layer having a second known CMP selectivity relative to that of the first CMP layer, including depositing portions of the second CMP layer in the pattern of the first CMP layer; CMP the structure so that the indicator structures are removed and any portion of the first CMP layer and second CMP layer are removed to a level corresponding to the lower margin; and completing the IC structure.

Description

RELATED APPLICATION
This Application is related to Device and method for reversible resistance change induced by electric pulses in non-crystalline perovskite unipolar programmable memory; Ser. No. 10/072,225, filed Feb. 7, 2002.
FIELD OF THE INVENTION
This invention relates to CMP processes for use in fabrication of integrated circuits generally, and specifically to CMP used to fabricate a non-volatile resistance RAM structure and CMOS processes to make the memory devices, particularly CMR/PCMO devices.
BACKGROUND OF THE INVENTION
Colossal Magnetoresistance (CMR) materials, such as Pr0.7CaO0.3MnO3 (PCMO) for example, have been found to have varying resistance states depending on the polarity and strength of an electric pulse passed through the material. These types of material may be used for novel non-volatile resistance random access memory (RRAM) applications. However, the integration of CMR films into CMOS ICs remains a challenge.
Know techniques for incorporation of CMR materials into CMOS ICs include the use of a damascene structure along with chemical mechanical polishing (CMP), which has been used to pattern CMR films into a CMOS circuit, as shown in FIG. 1. A commercially available slurry, silica plus NH4OH, which is generally used to polish SiO2, however, this slurry is not known to have been used in the CMP of CMR films. As is to be expected, CMP selectivity between CMR films and SiO2 films is poor. That means that CMP of CMR films will not stop on the underlying oxide, such as tetraethylorthosilicate oxide (oxane) TEOS film. This leads to over polishing of CMR films and makes CMR thickness control difficult. Additionally, because of the high PCMO processing temperature, e.g., 500° C. to 650° C., required to form proper PCMO structure for RRAM applications, there is some inter-reaction at the SiO2/PCMO interface, which makes thickness measurement of SiO2 unreliable. This characteristic of CMR CMP has precluded the use of SiO2 thickness measurements to determine the end point of CMP CMR films and also for controlling CMR film thickness.
A PCMO thin film has been grown on both epitaxial YBa2Cu3O7 (YBCO) and partial epitaxial Pt substrates via pulsed laser abrasion (PLA) technique, Liu et al., Electric-pulse-induced reversible resistance change effect in magnetoresistive films, Applied Physics Letters, 76, 2749, 2000; and Liu et al., U.S. Pat. No. 6,204,139, granted Mar. 20, 2001, for Method of switching the properties of perovskite materials used in thin film resistors. X-Ray diffraction (XRD) polar figures confirm the epitaxial properties of PCMO thin films. Liu et al., A new concept for non-volatile memory: the electric-pulse induced resistive change effect in Colossal Magnetoresistive thin films, JPL Publication 01-15; Non-Volatile Memory Technology Symposium 2001; November, 2001, pp 18-24, provides additional research information in the field of CMR-containing integrated circuits.
U.S. Pat. No. 6,204,139 describes the resistance change which occurred when electric pulses are applied at room temperature to PCMO thin films. The PCMO thin films were deposited on both epitaxial YBa2Cu3O7 (YBCO) and partial epitaxial Pt substrates by pulsed laser deposition (PLD). The polarity of the electric pulse determines the character of the resistance change, i.e., increase or decrease.
SUMMARY OF THE INVENTION
A method of CMP thin films during fabrication of IC devices includes preparing a substrate, including building IC component structures on the substrate; depositing a bottom electrode on the substrate; depositing a first CMP layer having a first known CMP selectivity on the substrate; patterning the first CMP layer to form a pattern having a lower margin; forming indicator structures on the first CMP layer in the pattern; depositing a second CMP layer having a second known CMP selectivity relative to that of the first CMP layer, including depositing portions of the second CMP layer in the pattern of the first CMP layer; CMP the structure so that the indicator structures are removed and any portion of the first CMP layer and second CMP layer are removed to a level corresponding to the lower margin; and completing the IC structure.
It is an object of the invention to provide an indicator useful in CMP of integrated circuit component layers having poor CMP selectivity.
Another object of the invention is to provide a method for CMP of CMR materials formed on oxide layers or nitride layers.
A further object of the invention is to provide for CMP of CMR materials with a silica and ammonium hydroxide slurry.
This summary and objectives of the invention are provided to enable quick comprehension of the nature of the invention. A more thorough understanding of the invention may be obtained by reference to the following detailed description of the preferred embodiment of the invention in connection with the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 depicts a prior art RRAM cell having a damascene structure for PCMO deposition.
FIG. 2 is a schematic representation of metal patterns which are pre-laid under CMR films for CMP CMR end point detection.
FIGS. 3-7 depict steps in an end-point-structure-making process.
FIGS. 8-10 are photos of various steps in the method of the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
The method of the invention provides a practical method for end point detecting as well as colossal magnetoresistive (CMR) thickness control in chemical mechanical polishing (CMP) CMR-containing IC devices. As previously noted, the problem solved by the method of the invention is that of determining when to cease CMP of an IC component layer when there is little difference in the CMP rates of layered materials.
Referring to FIG. 2, an integrated circuit substrate 10 has any number of IC components formed thereon, including a bottom electrode 12, and an oxide or nitride layer 14, referred to herein as a first CMP layer having a known CMP selectivity. A damascene trench 16 is formed in the first CMP layer, exposing a portion of the upper surface of bottom electrode 12. In the method of the invention, special patterned end-point indicator structures 18 are laid down before the deposition of a CMR film 20, which indicator structures may be seen to extend upwardly into the CMR, or other IC film. Indicator structures 18 may also be formed under “dented” portions of the overlying IC film layer. CMR material is transparent in thin layers, therefor, the indicator structures may be seen though the overlying CMR layer. This pattern, however, is gradually polished off during CMP of the CMR film. The end point of CMP is obtained when indicator structure 18 pattern is gone, resulting in a portion of the CMR layer and first CMP layer being removed by CMP, until indicator structures are gone, leaving the CMR layer only in trench 16.
Although the method of the invention is described in connection with a preferred embodiment relating to a specific type of IC component, e.g., PCMO, the method of the invention is not limited to use with the IC component used as an example, and may be applied to an IC fabrication. The method of the invention is a process that constructs the end-point indicator structures on the wafer surface includes the following steps:
Referring now to FIG. 3, substrate 10 includes any number of IC structures, including a bottom electrode 12, e.g., a platinum bottom electrode. An oxide or nitride first CMP layer 14 is formed over the substrate and bottom electrode. Layer 14 is also referred to herein as a first CMP layer. A trench 16 is formed in first CMP layer 14. A photo resist layer 22 is applied to the wafer. The photo resist is pattered with a metal mask 24 which contains an end-point structure pattern. The wafer is placed in a buffered oxide etch (BOE) 50:1 after being developed for one to two minutes. This will provide an etched step of between about 20 nm to 40 nm in depth.
The photoresist is retained in place, a metal indicator layer 26 is deposited, e.g., titanium to a thickness of about 5 nm or aluminum to a thickness of about 10 nm, with PVD being the accepted method for such deposition. E-beam evaporation is one technique which is appropriate for this purpose. The metal-coated wafers are dipped into a photoresist removal solution, e.g., acetone or EKC, resulting in the structure of FIG. 5, having indicator structures 28 formed in trenches in first CMP layer 14.
As shown in FIG. 6, a layer of CMR material 30 is deposited in the structure. However, as will be appreciated by one of ordinary skill in the art, layer 30 may be any material which is (1) required to be partially removed or smoothed by CMP; and (2) has a known CMP selectivity relative to the CMP selectivity of layer 14. Layer 30 is also referred to herein as a second CMP layer. As previously noted, layer 14, the first CMP layer, has a first known CMP selectivity, Layer 14 may be silicon dioxide or silicon nitride. Layer 30 is a second CMP layer having a second known CMP selectivity relative to the first known CMP selectivity. In the case of SiO2, PCMO and SiN, SiO2 polishes at a CMP rate faster than PCMO, and PCMO polishes at a CMP rate faster than SiN. Other CMR materials polish at about the same rate as PCMO.
After the first and second CMP layers and the indicators structures are laid down, CMP is performed in a slurry which will work on oxide, nitride and CMR materials. The method of the invention uses a silica+ammonium hydroxide (NH4OH) slurry, which has been found to be effective on CMR materials as well as on SiO2 and SiN. CMP continues until end-point indicator structures 28 are removed, indicating that the CMP is complete and that a desired amount of the CMR has been removed. Referring to FIG. 7, the structure is depicted after CMP, wherein only a portion of first CMP layer 14 remains, with trench 16 being filled with CMR material 30. The indicator structures, the upper portion of CMR layer 30 and a portion of first CMP layer 14 have been removed by CMP, which is performed until the indicator structures are removed.
FIG. 8 is a photo of an indicator structure 28, formed on a SiN layer 32, which has a transparent PCMO CMR layer 34 deposited thereon. A trench 16 is also filled with PCMO CMR material. FIG. 9 depicts partial removal of PCMO CMR layer 34 outside of trench 16 and partial removal of indicator structure 28. In FIG. 10, all that remains in PCMO CMR material 34 in trench 16 and SiN layer 32. Careful observation of the demise of indicator structures 28 provides a positive indicator of the extend of the CMP process, and provides an indicator which is used to stop the CMP process before the CMP process removes significant portions of the first CMP layer.
Thus, a method for CMP of CMR thin films has been disclosed. It will be appreciated that further variations and modifications thereof may be made within the scope of the invention as defined in the appended claims.

Claims (12)

We claim:
1. A method of CMP thin films during fabrication of IC devices, comprising:
preparing a substrate, including building IC component structures on the substrate;
depositing a bottom electrode on the substrate;
depositing a first CMP layer having a first known CMP selectivity on the substrate;
patterning the first CMP layer to form a pattern having a lower margin thereto;
forming indicator structures on the first CMP layer in the pattern;
depositing a second CMP layer having a second known CMP selectivity relative to that of the first CMP layer, including depositing portions of the second CMP layer in the pattern of the first CMP layer;
CMP the structure so that the indicator structures are removed and any portion of the first CMP layer and second CMP layer are removed to a level corresponding to the lower margin; and
completing the IC structure.
2. The method of claim 1 wherein said depositing a first CMP layer includes depositing a layer of material taken from the group of materials consisting of oxides and nitrides.
3. The method of claim 1 wherein said depositing a layer of second CMP material includes depositing a layer of PCMO.
4. The method of claim 1 wherein said forming indicator structures includes depositing a layer of metal take from the group of metals consisting of titanium and aluminum.
5. The method of claim 1 wherein said CMP includes CMP with a slurry formed of silica and ammonium hydroxide.
6. A method of CMP thin films during fabrication of IC devices, comprising:
preparing a substrate, including building IC component structures on the substrate;
depositing a bottom electrode on the substrate;
depositing an first CMP layer having a first known CMP selectivity on the substrate;
patterning the first CMP layer to form a pattern having a lower margin;
forming indicator structures on the first CMP layer in the pattern;
depositing a CMR layer having a second known CMP selectivity relative to that of the oxide layer, including depositing portions of the CMR layer in the pattern of the first CMP layer;
CMP the structure with a slurry of silica and ammonium hydroxide so that the indicator structures are removed and any portion of the first CMP layer and CMR layer are removed to a level corresponding to the lower margin; and
completing the IC structure.
7. The method of claim 6 wherein said forming indicator structures includes depositing a layer of metal take from the group of metals consisting of titanium and aluminum.
8. The method of claim 6 wherein said depositing a first CMP layer includes depositing a layer of material taken from the group of materials consisting of oxides and nitrides.
9. The method of claim 6 wherein said depositing a CMR layer includes depositing a layer of PCMO.
10. A method of CMP thin films during fabrication of IC devices, comprising:
preparing a substrate, including building IC component structures on the substrate;
depositing a bottom electrode on the substrate;
depositing an first CMP layer taken from the group of materials consisting of silicon dioxide and silicon nitride having a first known CMP selectivity on the substrate;
patterning the first CMP layer to form a pattern having a lower margin;
forming indicator structures on the first CMP layer in the pattern;
depositing a CMR layer having a second known CMP selectivity relative to that of the oxide layer, including depositing portions of the CMR layer in the pattern of the first CMP layer;
CMP the structure with a slurry of silica and ammonium hydroxide so that the indicator structures are removed and any portion of the first CMP layer and CMR layer are removed to a level corresponding to the lower margin; and
completing the IC structure.
11. The method of claim 10 wherein said forming indicator structures includes depositing a layer of metal take from the group of metals consisting of titanium and aluminum.
12. The method of claim 10 wherein said depositing a CMR layer includes depositing a layer of PCMO.
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US20060081467A1 (en) * 2004-10-15 2006-04-20 Makoto Nagashima Systems and methods for magnetron deposition
US20060081466A1 (en) * 2004-10-15 2006-04-20 Makoto Nagashima High uniformity 1-D multiple magnet magnetron source
US20060099813A1 (en) * 2004-10-21 2006-05-11 Sharp Laboratories Of America, Inc. Chemical mechanical polish of PCMO thin films for RRAM applications
US20060276036A1 (en) * 2004-10-15 2006-12-07 Makoto Nagashima Systems and methods for plasma etching
US20070084717A1 (en) * 2005-10-16 2007-04-19 Makoto Nagashima Back-biased face target sputtering based high density non-volatile caching data storage
US20070084716A1 (en) * 2005-10-16 2007-04-19 Makoto Nagashima Back-biased face target sputtering based high density non-volatile data storage
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US20070224770A1 (en) * 2006-03-25 2007-09-27 Makoto Nagashima Systems and methods for fabricating self-aligned memory cell
US20080011600A1 (en) * 2006-07-14 2008-01-17 Makoto Nagashima Dual hexagonal shaped plasma source
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