US6724088B1 - Quantum conductive barrier for contact to shallow diffusion region - Google Patents
Quantum conductive barrier for contact to shallow diffusion region Download PDFInfo
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- US6724088B1 US6724088B1 US09/295,132 US29513299A US6724088B1 US 6724088 B1 US6724088 B1 US 6724088B1 US 29513299 A US29513299 A US 29513299A US 6724088 B1 US6724088 B1 US 6724088B1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0895—Tunnel injectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- various materials are used to form the components of the transistor such as the source and drain diffusion regions, electrical contacts (studs) to the diffusion regions, various dielectric regions, gate conductor, gate oxide, etc.
- the studs are typically metal (i.e. tungsten) or a highly doped polycrystalline silicon (polysilicon) material whereas the source and drain diffusion regions may be very shallow regions of more precise dopant level in the monocrystalline semiconductor substrate.
- the successful functioning of the transistor depends in part on the ability of these diverse materials to maintain their original or desirably modified character during manufacture/useful life of the device.
- the contact metallurgy (the conductive stud) is prone to “spike through” to the junction edge, which results in excessive leakage currents.
- One technique which is commonly employed in the art avoids contact metallurgy “spike through” by forming a locally deep junction in the contact hole prior to the deposition of the conductive stud material.
- crystal defects are likely to propagate from the interface between the contact metallurgy and the silicon substrate into the depletion region of the source-drain diffusion. These silicon defects also result in increased junction leakage currents.
- the contact metallurgy may interact with the monocrystalline semiconductor substrate altering the doping of the diffusion in an undesirable manner.
- dopant may diffuse from the junction into the stud. This lowers the average doping concentration and increases the resistance of the diffusion. Increased diffusion resistance slows the switching speed of the MOSFET.
- dopant from the stud may diffuse into the semiconductor substrate. The out-diffusion from the stud may result in an excessively deep diffusion, which degrades the electrical characteristics (i.e. poorer threshold voltage control, increased off-state leakage current) of the MOSFET.
- the invention provides technology which enables contact structures of improved reliability and performance. More specifically, the invention enables improved contact between conductive studs and shallow diffusion regions by incorporation of a quantum conductive barrier layer at the interface between the conductive stud and shallow diffusion region.
- the invention encompasses a structure on a semiconductor substrate, the structure comprising (a) a shallow doped region in the substrate, and (b) an electrical contact to the shallow doped region, wherein the structure further comprises (c) a quantum conductive barrier layer between the doped region and the electrical contact, the doped region being in electrically connected to the electrical contact through the quantum conductive barrier layer.
- the invention further encompasses MOSFET transistor structures containing the quantum conductive barriers of the invention at the interfaces between the conductive studs and the source and drain diffusion regions.
- the invention encompasses a method of forming a structure on a semiconductor substrate, the structure comprising (a) a shallow doped region in the substrate, (b) an electrical contact to the shallow doped region, and (c) a quantum conductive barrier layer between the doped region and said electrical contact, the method comprising:
- Preferred quantum conductive barrier layer materials are silicon nitride or silicon oxynitride.
- the quantum conductive layer(s) is preferably formed by reacting the exposed surface of the shallow doped region with a nitrogen compound.
- FIG. 1 is a schematic cross section of a MOSFET transistor showing the quantum conductive barrier layers of the invention.
- the invention provides contact structures of improved reliability and performance. More specifically, the invention enables improved contact between conductive studs and shallow diffusion regions by incorporation of a quantum conductive barrier layer at the interface between the conductive stud and shallow diffusion region. The invention also provides methods for making these structures.
- the quantum conductive layers of the invention are very thin films of materials which in their bulk properties would be considered dielectrics (i.e., electrical insulators). In very thin layers, however, these materials become electrically conductive. Advantageously, these thin layers also have the ability (a) to prevent or slow diffusion of chemical species from one side of the layer to the other.
- the bulk resistivity (measured in a thick section at 25° C.) of the materials used to make up the quantum conductive layers of the invention is preferably at least about 10 6 ohm-m, more preferably at least about 10 8 ohm-m, most preferably at least about 10 11 ohm-m.
- the quantum conductive layer preferably has a thickness of about 50 ⁇ or less, more preferably about 5-30 ⁇ , most preferably about 5-15 ⁇ .
- the resulting layers preferably have a film resistance of less than about 1 K-ohm- ⁇ m 2 , more preferably less than about 100 ohm- ⁇ m 2 .
- the series resistance introduced by the quantum conductive layer is equal to the film resistance (ohm- ⁇ m 2 ) divided by the cross-sectional area ( ⁇ m 2 ) of the quantum conductive layer normal to the direction of current.
- the quantum conductive layers of the invention are preferably substantially uniform, however some variation in thickness may be permissible.
- the layer thickness is kept in a range permitting the quantum conductive effect to take place for all points on the layer while performing the desired barrier function.
- Preferred quantum conductive materials are inorganic oxides or nitrides, more preferably silicon nitride compounds selected from the group consisting of silicon nitride or silicon oxynitride. These compounds may be stoichiometric or non-stoichiometric. Alternatively, other ceramic materials, such as, for example, alumina, germanium oxide, yttria-stabilized zirconia or other forms of zirconia may be used. The layer composition may be determined by secondary ion mass spectroscopy (SIMS) or other suitable technique.
- SIMS secondary ion mass spectroscopy
- the invention encompasses structures comprising (a) a shallow doped region in a semiconductor substrate, and (b) an electrical contact to the shallow doped region, wherein the structure further comprises (c) a quantum conductive barrier layer between the doped region and the electrical contact, the doped region being in electrically connected to the electrical contact through the quantum conductive barrier layer.
- the invention is not limited to any specific device configuration incorporating the structures of the invention, however, the structures of the invention are preferably incorporated into a MOSFET or other transistor devices. Examples of various transistor structures are disclosed in U.S. Pat. Nos. 4,691,219; 4,833,094; 5,216,282; 5,363,327; 5,614,431; and 5,792,703, the disclosures of which are incorporated herein by reference.
- FIG. 1 illustrates one embodiment of the invention.
- FIG. 1 shows a schematic side view of a MOSFET 40 in a substrate 60 . Shallow source/drain diffusions (doped regions) 42 and 44 are formed in substrate 60 .
- a gate conductor 46 is formed over a gate oxide 48 between the source/drain diffusions.
- Side wall spacer 50 is preferably located along the sides of gate conductor 46 .
- Conductive studs 52 and 54 contact diffusions 42 and 44 through quantum conductive barrier layers 56 and 58 respectively.
- Conductive studs 52 and 54 are separated from the gate conductor stack by insulating layer 62 .
- the quantum conductive layer of the invention located at the interface between the conductive studs and the shallow diffusions advantageously acts to prevent or inhibit diffusion of dopants from the studs to the diffusions and further into substrate 60 .
- the quantum conductive layer minimizes any deepening of the shallow diffusions caused by unwanted dopant migration from the conductive studs.
- the invention is not limited to any specific material compositions for the various components of the shallow diffusions, the conductive studs or other components. If desired, materials described in the art for forming MOSFETs or other devices employing shallow diffusions may be used.
- the studs 52 and 54 would typically be made of tungsten or a doped polycrystalline silicon.
- Substrate 60 would typically be a monocrystalline semiconductor material (most typically silicon, lightly doped silicon or silicon having lightly doped bands).
- the shallow diffusions would typically be formed by diffusing an appropriate N-type or P-type dopant into the substrate.
- the insulating layer(s) is typically a silicon dioxide. If present, the gate conductor may be a doped polysilicon or other conductive gate stack composition.
- the sidewall may be a silicon oxide, silicon nitride, or other appropriate insulating material.
- Transistor devices or other structures of the invention containing the quantum conductive layers between conductive studs and shallow diffusions may be formed by inserting a quantum conductive layer formation step at an appropriate point(s) in the overall transistor (or other device) manufacturing process.
- the overall manufacturing process used may be any of those disclosed known in the art such as those described in the patents mentioned above. Alternatively, other variations on manufacturing processes for transistors (or other structures involving contact between a conductive stud and shallow diffusion) may be used.
- the invention encompasses a method of forming a structure on a semiconductor substrate, the structure comprising (a) a shallow doped region in the substrate, (b) an electrical contact to the shallow doped region, and (c) a quantum conductive barrier layer between the doped region and said electrical contact, the method comprising:
- the shallow source-drain diffusions may be formed by using methods such as very low energy ion implantation, plasma immersion doping, or doping from a solid source in combination with laser annealing to limit the thermal budget. These methods allow source-drain junction depths in the range of about 20-50 nm to be achieved.
- the quantum conductive layers of the invention may be formed by various methods. The choice of method may depend on the composition of the surface on which the layer is to be formed and/or the desired quantum conductive layer composition.
- the quantum conductive layer is preferably formed by reacting a portion of the silicon at the exposed surface with a nitrogen-containing compound in the atmosphere contacting the surface.
- a nitrogen-containing compound are those which are easily handled in a gaseous state. Examples of preferred nitrogen compounds are selected from the group consisting of ammonia, NO, N 2 O or (under plasma conditions) monatomic nitrogen. Ammonia is the preferred nitrogen compound.
- the atmosphere may also contain one or more diluent gases such as N 2 , helium or argon.
- the partial pressure of the nitrogen compound is preferably about 1-760 Torr, more preferably, about 5-10 Torr.
- the reaction is typically facilitated by heating to a temperature of about 300-950° C., more preferably about 350-750° C.
- the reaction may be conducted until the desired layer thickness is formed.
- the reaction is conducted for about 1-30 minutes, more preferably about 10-20 minutes.
- the reaction is typically self-limiting under these conditions.
- the exposed diffusion surface may be pre-cleaned by a chemical etch (e.g., HF solution) and/or by a high temperature (e.g., about 900°-1000° C.) bake in a hydrogen atmosphere (or other appropriate reducing atmosphere) to remove some or all of any pre-existing oxide surface layer.
- a chemical etch e.g., HF solution
- a high temperature e.g., about 900°-1000° C.
- hydrogen atmosphere or other appropriate reducing atmosphere
- the above nitrogen reaction process may be conducted with a substrate having a pre-existing very thin oxide layer.
- the relative contents of oxygen and nitrogen in the quantum conductive layer can be controlled by the temperature and time of the nitrogen compound reaction, with higher temperatures and longer reaction times giving a more nitrogen-rich layer.
- oxynitride layers may be formed by introducing a very minor amount of oxygen into the nitrogen compound-containing atmosphere. In general, this method is less preferred since control of the oxygen content and/or layer thickness may be difficult.
- the quantum conductive layer may be formed by chemical vapor deposition.
- the reactants for forming the quantum conductive layer may be those typically used to form a layer of the corresponding dielectric material, however the reaction conditions (time, temperature, pressure) and/or proportions of the reactants must be appropriately reduced to avoid deposition of an excessively thick film. See, for example, the process for forming germanium oxide thin films described in U.S. Pat. Nos. 5,648,861 and 5,051,786, the disclosures of which are incorporated herein by reference. Alternative methods for forming the desired films may be found in the “Handbook of Thin Film Technology” by Maissel & Glang, McGraw-Hill Book Co. (1970) and in similar treatises. Appropriate etching techniques may be used to reduce excess film thickness where necessary.
Abstract
Description
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US09/295,132 US6724088B1 (en) | 1999-04-20 | 1999-04-20 | Quantum conductive barrier for contact to shallow diffusion region |
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US09/295,132 US6724088B1 (en) | 1999-04-20 | 1999-04-20 | Quantum conductive barrier for contact to shallow diffusion region |
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Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
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US20040063277A1 (en) * | 2002-09-27 | 2004-04-01 | International Business Machines Corporation | Semiconductor method and structure for simultaneously forming a trench capacitor dielectric and trench sidewall device dielectric |
EP2359394A2 (en) * | 2008-12-19 | 2011-08-24 | Intel Corporation | Metal-insulator-semiconductor tunneling contacts |
CN104051530A (en) * | 2013-03-14 | 2014-09-17 | 台湾积体电路制造股份有限公司 | Metal-Oxide-Semiconductor Field-Effect Transistor with Metal-Insulator Semiconductor Contact Structure to Reduce Schottky Barrier |
US9209261B2 (en) | 2002-08-12 | 2015-12-08 | Acorn Technologies, Inc. | Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions |
US9270083B2 (en) | 2011-08-12 | 2016-02-23 | Acorn Technologies, Inc. | Tensile strained semiconductor photon emission and detection devices and integrated photonics system |
US9362376B2 (en) | 2011-11-23 | 2016-06-07 | Acorn Technologies, Inc. | Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers |
US9536973B2 (en) | 2013-03-14 | 2017-01-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal-oxide-semiconductor field-effect transistor with metal-insulator-semiconductor contact structure to reduce schottky barrier |
US9583614B2 (en) | 2002-08-12 | 2017-02-28 | Acorn Technologies, Inc. | Insulated gate field effect transistor having passivated schottky barriers to the channel |
US9620611B1 (en) | 2016-06-17 | 2017-04-11 | Acorn Technology, Inc. | MIS contact structure with metal oxide conductor |
US10170627B2 (en) | 2016-11-18 | 2019-01-01 | Acorn Technologies, Inc. | Nanowire transistor with source and drain induced by electrical contacts with negative schottky barrier height |
US10833194B2 (en) | 2010-08-27 | 2020-11-10 | Acorn Semi, Llc | SOI wafers and devices with buried stressor |
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