US6803647B2 - Mounting structure of semiconductor device and mounting method thereof - Google Patents

Mounting structure of semiconductor device and mounting method thereof Download PDF

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Publication number
US6803647B2
US6803647B2 US09/788,596 US78859601A US6803647B2 US 6803647 B2 US6803647 B2 US 6803647B2 US 78859601 A US78859601 A US 78859601A US 6803647 B2 US6803647 B2 US 6803647B2
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leads
insulating sheet
solder balls
wiring substrate
connection pads
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US20010017425A1 (en
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Hirokazu Miyazaki
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NEC Corp
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NEC Corp
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0388—Other aspects of conductors
    • H05K2201/0397—Tab
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10378—Interposers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10977—Encapsulated connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • H05K3/3426—Leaded components characterised by the leads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4084—Through-connections; Vertical interconnect access [VIA] connections by deforming at least one of the conductive layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4092—Integral conductive tabs, i.e. conductive parts partly detached from the substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a mounting structure of a semiconductor device which can be easily detached from a wiring substrate after being mounted on the wiring substrate and a mounting method thereof.
  • a semiconductor chip 21 and a wiring substrate 25 are connected to each other by welded solder balls 26 of the semiconductor chip 21 . Further, resin 29 is injected into the gap between the semiconductor chip 21 and the wiring substrate 25 so as to cover the solder balls 26 . The resin 29 is injected for the purpose of alleviating the thermal stress caused by the difference in the coefficient of thermal expansion between the semiconductor chip 21 and the wiring substrate 25 .
  • the semiconductor chip 21 and the wiring substrate 25 repeat expansion and contraction by heat generated by operations (on/off operation) of the device.
  • the coefficient of thermal expansion of the semiconductor chip 21 is about 3.5 ppm whereas the coefficient of thermal expansion of the wiring substrate 25 is about 16 ppm in case of a printed board and about 8 ppm in case of an alumina substrate. Due to this difference in the coefficient of thermal expansion between the semiconductor chip 21 and the wiring substrate 25 , the solder balls 26 are alternately subject to compressive stress and tensile stress. As a result, the solder balls 26 are broken at an early stage due to thermal fatigue, which causes electric disconnection, resulting in a signal transmission stop or a power supply stop.
  • the resin 29 alleviates stress on the solder balls 26 . This suppresses the deterioration of the solder balls 26 , and the reliability of the connection between the semiconductor chip 21 and the wiring substrate 25 is improved. It is to be noted that epoxy-based resin is mainly used as the resin 29 .
  • An object of the present invention is to provide a mounting structure of a semiconductor device in which a semiconductor chip can be detached from a wiring substrate and high reliability is realized.
  • a mounting structure of a semiconductor device with excellent connection reliability can alleviate the stress on solder balls caused by the difference in the coefficient of thermal expansion between a semiconductor chip and a wiring substrate when the semiconductor chip is mounted on the wiring substrate.
  • a mounting structure of a semiconductor device with excellent maintainability can be provided in which a semiconductor chip can be easily detached from a wiring substrate after the semiconductor chip has been mounted on the wiring substrate.
  • an insulating sheet having a plurality of leads is attached between a semiconductor chip and a wiring substrate, the plurality of leads electrically connecting a plurality of solder balls and a plurality of corresponding connection pads, respectively.
  • the insulating sheet has holes therethrough at positions corresponding to those of the plurality of connection pads.
  • each of the plurality of leads is fixed on a first surface of the insulating sheet, while the other end is inserted in one of the holes.
  • Each of the plurality of solder balls is electrically connected to the fixed one end of a corresponding one of the plurality of leads, while each of the plurality of connection pads is electrically connected to the other end of a corresponding one of the plurality of leads protruding from one of the holes.
  • a mounting method of a semiconductor device includes providing an insulating sheet having holes therethrough at positions corresponding to those of a plurality of connection pads and having a plurality of leads, one end of each of the plurality of leads being fixed on a first surface of the insulating sheet and the other end of each of the plurality of leads protruding from a second surface of the insulating sheet through one of the holes, electrically connecting the other end of each of the plurality of leads of the insulating sheet to a corresponding one of the plurality of connection pads of a wiring substrate, and electrically connecting each of a plurality of solder balls of a semiconductor chip to the fixed one end of a corresponding one of the plurality of leads.
  • an insulating sheet has a plurality of holes therethrough and a plurality of leads, one end thereof being fixed on a first surface of the insulating sheet and the other end thereof being shaped to be afloat in the holes.
  • a method of manufacturing an insulating sheet comprises the steps of providing a metal film on one surface of the insulating sheet, masking and etching the metal film to form a plurality of leads, cutting out predetermined places of the insulating sheet to provide a plurality of holes through the insulating sheet, and making one end of each of the plurality of leads fall into a corresponding one of the plurality of holes.
  • FIG. 1 illustrates the structure of a first embodiment according to the present invention
  • FIG. 2 is a perspective view illustrating the structure of the first embodiment
  • FIGS. 3 ( a ) to 3 ( e ) illustrate a method of manufacturing an insulating sheet
  • FIGS. 4 ( a ) to 4 ( d ) illustrate a mounting method of the mounting structure according to the first embodiment
  • FIG. 5 illustrates another structure of an insulating sheet
  • FIG. 6 illustrates the structure of a second embodiment according to the present invention.
  • FIG. 7 illustrates a conventional structure of a semiconductor device.
  • the first embodiment of the present invention includes a semiconductor chip 1 , an insulating sheet 2 , and a wiring substrate 5 .
  • a plurality of pads 3 for electric connection to the external are arranged to be lattice-like on one surface of the semiconductor chip 1 .
  • Solder balls 6 are attached to the plurality of pads 3 , respectively.
  • a Stannum/Plumbum (Sn/Pb) alloy, an Stannum/Bismuth/Argentum (Sn/Bi/Ag) alloy, a Stannum/Silver (Sn/Ag) alloy or the like is used for the composition of the solder balls 6 .
  • the wiring substrate 5 has therein internal wirings 7 formed of a conductive material such as Copper (Cu). Further, the wiring substrate 5 has on its surface where the semiconductor chip 1 is mounted a plurality of connection pads 8 corresponding to the pads 3 of the semiconductor chip 1 , respectively. The respective plurality of connection pads 8 are connected to the internal wirings 7 to be electrically connected to a power source layer or other components.
  • a conductive material such as Copper (Cu).
  • the insulating sheet 2 is formed of an insulating material such as polyimide resin, Teflon resin, epoxy resin and alumina at the thickness of about 0.1 mm-0.5 mm.
  • the coefficient of thermal expansion of the insulating sheet should be between the coefficient of thermal expansion of the semiconductor and the coefficient of thermal expansion of the wiring substrate.
  • the insulating sheet 2 also has windows 10 therethrough formed by cutting out places corresponding to the connection pads 8 on the wiring substrate 5 .
  • the insulating sheet 2 has a plurality of leads 4 , one end (hereinafter referred as a first end) of each leads being fixed on the insulating sheet 2 and the other end (hereinafter referred as a second end) of each leads being inserted into the windows 10 to be in a floated state.
  • First ends 11 of the leads 4 are fixed on the insulating sheet 2 at positions corresponding to the solder balls 6 of the semiconductor chip 1 , respectively. Moreover, the leads 4 are curved or bent so that unfixed second ends 12 protrude through the windows 10 from a opposite surface of the insulating sheet 2 . The unfixed second ends 12 of the leads 4 are positioned to places corresponding to the places of the connection pads 8 on the wiring substrate 5 , respectively.
  • a method of manufacturing the insulating sheet 2 is described.
  • a metal film 14 is formed on an insulating sheet 13 by plating or the like (FIG. 3 ( a )).
  • the metal film 14 is etched to form leads 15 (FIG. 3 ( b )).
  • Some parts of the insulating sheet 13 are cutout to provide windows 16 (FIG. 3 ( c )).
  • one end of each of the leads 15 is made to fall into one of the windows 16 as second end (FIG. 3 ( d )).
  • Another method of manufacturing the insulating sheet 2 is as follows. First, the windows 16 are provided in the insulating sheet 13 (FIG. 3 ( e )). Then, one end of each of the plurality of leads 15 prepared in advance is fixed to the insulating sheet 13 as first end (FIG. 3 ( c )). After that, the other end of each of the plurality of leads 15 as second end is made to fall into one of the windows 16 (FIG. 3 ( d )).
  • the insulating sheet 2 is mounted on the wiring substrate 5 with the surface of the insulating sheet 2 where second ends 12 are protruding therefrom being facing the wiring substrate 5 .
  • the second ends 12 of the leads 4 are aligned and connected to the corresponding connection pads 8 on the wiring substrate 5 , respectively (FIG. 4 ( a )).
  • the second ends 12 may be connected to the connection pads 8 by pressing or soldering. This electrically connects the leads 4 to the wiring substrate 5 below the windows 10 through the second ends 12 and the connection pads 8 .
  • the semiconductor chip 1 is mounted on the surface of the insulating sheet 2 which is opposite to the surface connected to the wiring substrate 5 , that is, on the surface of the insulating sheet 2 having first ends 11 fixed thereto.
  • the solder balls 6 are aligned and connected by welding to the corresponding the first ends 11 , respectively (FIG. 4 ( b )).
  • the connection pads 8 are connected to the unfixed second ends 12 of the leads 4 . Therefore, even when the wiring substrate 5 is deformed and stress is caused, the resilience of the leads 4 can absorb and alleviate the stress.
  • the necessity to encapsulate the solder balls 6 of the semiconductor chip 1 with resin or the like is eliminated, and thus, even after the semiconductor chip 1 is mounted on the wiring substrate 5 , the semiconductor chip 1 can be easily detached from the wiring substrate 5 by fusing the solder balls 6 . Therefore, the maintainability of the semiconductor chip 1 is improved.
  • the leads 4 provided for the insulating sheet 2 may be any resilient conductive material, including Cu and Au.
  • the first ends 11 of the leads 4 , to which the solder balls 6 are to be welded are appropriately processed into a circular shape, a polygonal shape or the like to fit the shape of the solder balls 6 .
  • FIG. 2 illustrates the structure where one window 10 is provided with regard to the plurality of connection pads 8
  • the structure may be that a window is provided with regard to each of the connection pads 8 .
  • connection pads 8 on a wiring substrate 5 are connected to second ends 12 of leads 4 , and first ends 11 of the leads 4 are connected to solder balls 6 of a semiconductor chip 1 by welding the solder balls 6 , respectively.
  • the second embodiment differs from the first embodiment in that resin 9 for encapsulation is filled into the gap between the wiring substrate 5 and an insulating sheet 2 and into windows 10 in the insulating sheet 2 when the wiring substrate 5 is connected to the insulating sheet 2 .
  • the resin 9 is filled into the gap between the insulating sheet 2 and the wiring substrate 5 and into the windows 10 (FIG. 4 ( c )).
  • the first ends 11 are connected to the solder balls 6 , and the semiconductor chip 1 is mounted on the insulating sheet 2 (FIG. 4 ( d )).
  • the leads 4 absorb and alleviate the thermal stress caused between the semiconductor chip 1 and the wiring substrate 5 , the stress on the solder balls 6 is alleviated to improve the reliability of the connection.
  • the semiconductor chip 1 can be easily detached from the wiring substrate 5 by fusing the solder balls 6 , which improves the maintainability.
  • the connection between the second ends 12 and the connection pads 8 can be ensured without impairing the resilience of the leads 4 .
  • the thermal stress caused by the difference in the coefficient of thermal expansion between the semiconductor chip and the wiring substrate can be absorbed.
  • the stress on the solder balls is alleviated to improve the reliability of the connection between the semiconductor chip and the wiring substrate.
  • the semiconductor chip can be easily detached from the wiring substrate by fusing the solder balls. Therefore, the semiconductor chip can be easily replaced, which improves the maintainability of the semiconductor device.
  • the connection between the leads and the connection pads can be ensured without impairing the resilience of the leads.
  • the structure where the insulating sheet is sandwiched between the semiconductor chip and the wiring substrate makes it possible to mount the semiconductor chip on various wiring substrates of various shapes, which enhances the degree of freedom of the semiconductor device.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

An insulating sheet which connects a semiconductor chip and a wiring substrate is provided between the semiconductor chip and the wiring substrate. The insulating sheet has windows therethrough at positions corresponding to those of connection pads of the wiring substrate and has leads, one end of each of the leads being fixed on the sheet and the other end of each of the leads protruding from the opposite surface of the sheet through a window. Each of solder balls of the semiconductor chip is connected to the fixed one end of one of the leads, and each of the connection pads is connected to the other end of each of the leads to electrically connect the semiconductor chip and the wiring substrate.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a mounting structure of a semiconductor device which can be easily detached from a wiring substrate after being mounted on the wiring substrate and a mounting method thereof.
2. Description of the Related Art
Conventionally, a method is known where a semiconductor chip is mounted on a wiring substrate through solder balls densely provided on one surface of the semiconductor chip. In such a conventional mounting structure of a semiconductor device, resin referred to as underfill is filled into the gap between the semiconductor chip and the wiring substrate. For example, Japanese Patent Application Laid-open No. Hei 10-284635 discloses a semiconductor device in which filling resin is embedded in a gap between a semiconductor chip and a substrate so as to cover solder balls.
With reference to FIG. 7, in such a conventional semiconductor device, a semiconductor chip 21 and a wiring substrate 25 are connected to each other by welded solder balls 26 of the semiconductor chip 21. Further, resin 29 is injected into the gap between the semiconductor chip 21 and the wiring substrate 25 so as to cover the solder balls 26. The resin 29 is injected for the purpose of alleviating the thermal stress caused by the difference in the coefficient of thermal expansion between the semiconductor chip 21 and the wiring substrate 25. The semiconductor chip 21 and the wiring substrate 25 repeat expansion and contraction by heat generated by operations (on/off operation) of the device. However, the coefficient of thermal expansion of the semiconductor chip 21 is about 3.5 ppm whereas the coefficient of thermal expansion of the wiring substrate 25 is about 16 ppm in case of a printed board and about 8 ppm in case of an alumina substrate. Due to this difference in the coefficient of thermal expansion between the semiconductor chip 21 and the wiring substrate 25, the solder balls 26 are alternately subject to compressive stress and tensile stress. As a result, the solder balls 26 are broken at an early stage due to thermal fatigue, which causes electric disconnection, resulting in a signal transmission stop or a power supply stop.
Therefore, by filling the resin 29 into the gap between the semiconductor chip 21 and the wiring substrate 25 so as to cover the solder balls 26. The resin 29 alleviates stress on the solder balls 26. This suppresses the deterioration of the solder balls 26, and the reliability of the connection between the semiconductor chip 21 and the wiring substrate 25 is improved. It is to be noted that epoxy-based resin is mainly used as the resin 29.
However, in the conventional semiconductor device described above, since the semiconductor chip 21 and the wiring substrate 25 are mechanically firmly bonded to each other with the resin 29, once the semiconductor chip 21 is attached to the wiring substrate 25, the semiconductor chip 21 can not be easily detached from the wiring substrate 25. Therefore, there has been a problem in that the semiconductor chip 21 can not be easily replaced and the maintainability is lowered.
An object of the present invention is to provide a mounting structure of a semiconductor device in which a semiconductor chip can be detached from a wiring substrate and high reliability is realized.
According to the present invention, a mounting structure of a semiconductor device with excellent connection reliability can alleviate the stress on solder balls caused by the difference in the coefficient of thermal expansion between a semiconductor chip and a wiring substrate when the semiconductor chip is mounted on the wiring substrate.
Further, according to the present invention, a mounting structure of a semiconductor device with excellent maintainability can be provided in which a semiconductor chip can be easily detached from a wiring substrate after the semiconductor chip has been mounted on the wiring substrate.
SUMMARY OF THE INVENTION
According to an aspect of the present invention, in a mounting structure of a semiconductor device, an insulating sheet having a plurality of leads is attached between a semiconductor chip and a wiring substrate, the plurality of leads electrically connecting a plurality of solder balls and a plurality of corresponding connection pads, respectively.
The insulating sheet has holes therethrough at positions corresponding to those of the plurality of connection pads.
One end of each of the plurality of leads is fixed on a first surface of the insulating sheet, while the other end is inserted in one of the holes.
Each of the plurality of solder balls is electrically connected to the fixed one end of a corresponding one of the plurality of leads, while each of the plurality of connection pads is electrically connected to the other end of a corresponding one of the plurality of leads protruding from one of the holes.
According to another aspect of the present invention, a mounting method of a semiconductor device includes providing an insulating sheet having holes therethrough at positions corresponding to those of a plurality of connection pads and having a plurality of leads, one end of each of the plurality of leads being fixed on a first surface of the insulating sheet and the other end of each of the plurality of leads protruding from a second surface of the insulating sheet through one of the holes, electrically connecting the other end of each of the plurality of leads of the insulating sheet to a corresponding one of the plurality of connection pads of a wiring substrate, and electrically connecting each of a plurality of solder balls of a semiconductor chip to the fixed one end of a corresponding one of the plurality of leads.
According to still another aspect of the present invention, an insulating sheet has a plurality of holes therethrough and a plurality of leads, one end thereof being fixed on a first surface of the insulating sheet and the other end thereof being shaped to be afloat in the holes.
According to yet another aspect of the present invention, a method of manufacturing an insulating sheet comprises the steps of providing a metal film on one surface of the insulating sheet, masking and etching the metal film to form a plurality of leads, cutting out predetermined places of the insulating sheet to provide a plurality of holes through the insulating sheet, and making one end of each of the plurality of leads fall into a corresponding one of the plurality of holes.
BRIEF DESCRIPTION OF THE DRAWINGS
These and other objects, features and advantages of the invention will become more fully apparent from the following detailed description taken in conjunction with accompanying drawings:
FIG. 1 illustrates the structure of a first embodiment according to the present invention;
FIG. 2 is a perspective view illustrating the structure of the first embodiment;
FIGS. 3(a) to 3(e) illustrate a method of manufacturing an insulating sheet;
FIGS. 4(a) to 4(d) illustrate a mounting method of the mounting structure according to the first embodiment;
FIG. 5 illustrates another structure of an insulating sheet;
FIG. 6 illustrates the structure of a second embodiment according to the present invention; and
FIG. 7 illustrates a conventional structure of a semiconductor device.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
A first embodiment of a mounting structure of a semiconductor device is now described in detail with reference to the drawings. With reference to FIGS. 1 and 2, the first embodiment of the present invention includes a semiconductor chip 1, an insulating sheet 2, and a wiring substrate 5.
A plurality of pads 3 for electric connection to the external are arranged to be lattice-like on one surface of the semiconductor chip 1. Solder balls 6 are attached to the plurality of pads 3, respectively. A Stannum/Plumbum (Sn/Pb) alloy, an Stannum/Bismuth/Argentum (Sn/Bi/Ag) alloy, a Stannum/Silver (Sn/Ag) alloy or the like is used for the composition of the solder balls 6.
The wiring substrate 5 has therein internal wirings 7 formed of a conductive material such as Copper (Cu). Further, the wiring substrate 5 has on its surface where the semiconductor chip 1 is mounted a plurality of connection pads 8 corresponding to the pads 3 of the semiconductor chip 1, respectively. The respective plurality of connection pads 8 are connected to the internal wirings 7 to be electrically connected to a power source layer or other components.
The insulating sheet 2 is formed of an insulating material such as polyimide resin, Teflon resin, epoxy resin and alumina at the thickness of about 0.1 mm-0.5 mm. The coefficient of thermal expansion of the insulating sheet should be between the coefficient of thermal expansion of the semiconductor and the coefficient of thermal expansion of the wiring substrate. The insulating sheet 2 also has windows 10 therethrough formed by cutting out places corresponding to the connection pads 8 on the wiring substrate 5. Furthermore, the insulating sheet 2 has a plurality of leads 4, one end (hereinafter referred as a first end) of each leads being fixed on the insulating sheet 2 and the other end (hereinafter referred as a second end) of each leads being inserted into the windows 10 to be in a floated state. First ends 11 of the leads 4 are fixed on the insulating sheet 2 at positions corresponding to the solder balls 6 of the semiconductor chip 1, respectively. Moreover, the leads 4 are curved or bent so that unfixed second ends 12 protrude through the windows 10 from a opposite surface of the insulating sheet 2. The unfixed second ends 12 of the leads 4 are positioned to places corresponding to the places of the connection pads 8 on the wiring substrate 5, respectively.
A method of manufacturing the insulating sheet 2 is described. With reference to FIGS. 3(a) to 3(e), at first, a metal film 14 is formed on an insulating sheet 13 by plating or the like (FIG. 3(a)). Then, using a mask of a desired pattern (in this embodiment, the pattern of leads), the metal film 14 is etched to form leads 15 (FIG. 3(b)). Some parts of the insulating sheet 13 are cutout to provide windows 16 (FIG. 3(c)). Then, one end of each of the leads 15 is made to fall into one of the windows 16 as second end (FIG. 3(d)).
Another method of manufacturing the insulating sheet 2 is as follows. First, the windows 16 are provided in the insulating sheet 13 (FIG. 3(e)). Then, one end of each of the plurality of leads 15 prepared in advance is fixed to the insulating sheet 13 as first end (FIG. 3(c)). After that, the other end of each of the plurality of leads 15 as second end is made to fall into one of the windows 16 (FIG. 3(d)).
A mounting method of the mounting structure of the semiconductor device according to the present invention is described in detail with reference to the drawings.
With reference to FIGS. 4(a) to 4(d), the insulating sheet 2 is mounted on the wiring substrate 5 with the surface of the insulating sheet 2 where second ends 12 are protruding therefrom being facing the wiring substrate 5. Here, the second ends 12 of the leads 4 are aligned and connected to the corresponding connection pads 8 on the wiring substrate 5, respectively (FIG. 4(a)). The second ends 12 may be connected to the connection pads 8 by pressing or soldering. This electrically connects the leads 4 to the wiring substrate 5 below the windows 10 through the second ends 12 and the connection pads 8. Then, the semiconductor chip 1 is mounted on the surface of the insulating sheet 2 which is opposite to the surface connected to the wiring substrate 5, that is, on the surface of the insulating sheet 2 having first ends 11 fixed thereto. The solder balls 6 are aligned and connected by welding to the corresponding the first ends 11, respectively (FIG. 4(b)). This electrically connects the semiconductor chip 1 to the wiring substrate 5 through the leads 4 provided on the insulating sheet 2, which makes it possible to input/output an electric signal and supply power between the semiconductor chip 1 and the wiring substrate 5.
According to the first embodiment of the present invention, since the first ends 11 of the leads 4 are formed on the insulating sheet 2, even when the solder balls 6 are welded and mounted onto the first ends 11 of the insulating sheet 2, sufficient connection strength can be maintained. Furthermore, the connection pads 8 are connected to the unfixed second ends 12 of the leads 4. Therefore, even when the wiring substrate 5 is deformed and stress is caused, the resilience of the leads 4 can absorb and alleviate the stress.
Therefore, even when thermal stress is caused by the difference in the coefficient of thermal expansion between the semiconductor chip 1 and the wiring substrate 5, the resilience of the leads 4 absorbs the stress to alleviate the stress on the solder balls 6. Accordingly, disconnection at the solder balls 6 is prevented to improve the reliability of the connection.
As a result, the necessity to encapsulate the solder balls 6 of the semiconductor chip 1 with resin or the like is eliminated, and thus, even after the semiconductor chip 1 is mounted on the wiring substrate 5, the semiconductor chip 1 can be easily detached from the wiring substrate 5 by fusing the solder balls 6. Therefore, the maintainability of the semiconductor chip 1 is improved.
It is to be noted that the leads 4 provided for the insulating sheet 2 may be any resilient conductive material, including Cu and Au.
It is preferable that the first ends 11 of the leads 4, to which the solder balls 6 are to be welded, are appropriately processed into a circular shape, a polygonal shape or the like to fit the shape of the solder balls 6.
Furthermore, With reference to FIG. 5, though FIG. 2 illustrates the structure where one window 10 is provided with regard to the plurality of connection pads 8, the structure may be that a window is provided with regard to each of the connection pads 8.
Next, a second embodiment according to the present invention is described in detail with reference to the drawings.
With reference to FIG. 6, similarly to the structure of the first embodiment, connection pads 8 on a wiring substrate 5 are connected to second ends 12 of leads 4, and first ends 11 of the leads 4 are connected to solder balls 6 of a semiconductor chip 1 by welding the solder balls 6, respectively.
However, the second embodiment differs from the first embodiment in that resin 9 for encapsulation is filled into the gap between the wiring substrate 5 and an insulating sheet 2 and into windows 10 in the insulating sheet 2 when the wiring substrate 5 is connected to the insulating sheet 2.
This can reinforce the connection between the second ends 12 of the leads 4 and the connection pads 8. Thus, the connection between the insulating sheet 2 and the wiring substrate 5 can be ensured. Furthermore, the resilience of the resin 9 is added to the resilience of the leads 4, which further alleviates stress.
In this case, after the second ends 12 are connected to the connection pads 8 as illustrated in FIG. 4(a), the resin 9 is filled into the gap between the insulating sheet 2 and the wiring substrate 5 and into the windows 10 (FIG. 4 (c)). After that, the first ends 11 are connected to the solder balls 6, and the semiconductor chip 1 is mounted on the insulating sheet 2 (FIG. 4(d)).
According to the second embodiment, similarly to the case of the first embodiment, since the leads 4 absorb and alleviate the thermal stress caused between the semiconductor chip 1 and the wiring substrate 5, the stress on the solder balls 6 is alleviated to improve the reliability of the connection.
Furthermore, even after the semiconductor chip 1 is mounted on the wiring substrate 5, the semiconductor chip 1 can be easily detached from the wiring substrate 5 by fusing the solder balls 6, which improves the maintainability.
Moreover, by filling the resin 9 for encapsulation into the gap between the wiring substrate 5 and the insulating sheet 2 and into the windows 10 in the insulating sheet 2, the connection between the second ends 12 and the connection pads 8 can be ensured without impairing the resilience of the leads 4.
As is clear from the above description, according to the present invention, by utilizing the resilience of the leads of the insulating sheet, the thermal stress caused by the difference in the coefficient of thermal expansion between the semiconductor chip and the wiring substrate can be absorbed. As a result, the stress on the solder balls is alleviated to improve the reliability of the connection between the semiconductor chip and the wiring substrate.
Furthermore, since the necessity to cover the solder balls with resin is eliminated, even after the semiconductor chip is mounted on the wiring substrate, the semiconductor chip can be easily detached from the wiring substrate by fusing the solder balls. Therefore, the semiconductor chip can be easily replaced, which improves the maintainability of the semiconductor device.
Moreover, by filling the resin for encapsulation into the gap between the wiring substrate and the insulating sheet and into the windows in the insulating sheet, the connection between the leads and the connection pads can be ensured without impairing the resilience of the leads.
Furthermore, the structure where the insulating sheet is sandwiched between the semiconductor chip and the wiring substrate makes it possible to mount the semiconductor chip on various wiring substrates of various shapes, which enhances the degree of freedom of the semiconductor device.
While the present invention and its advantages have been described in conjunction with preferred embodiments in the above detailed descriptions, the present invention is not limited thereto, and various changes, substitutions and alternations can be made therein without departing from spirits and scope of the inventions as defined by the appended claims.

Claims (16)

What is claimed is:
1. A mounting structure of a semiconductor device comprising:
a semiconductor chip having a plurality of solder balls arranged in a grid array;
a wiring substrate having a plurality of connection pads; and
an insulating sheet having a plurality of holes therethrough and leads passing through said holes, said insulating sheet being arranged between said semiconductor chip and said wiring substrate, wherein,
said leads connect said solder balls and said connection pads through said holes, respectively, and
an end of each of said leads is fixed on a first surface of said insulating sheet and is in contact with a corresponding one of said solder balls.
2. The mounting structure of a semiconductor device as claimed in claim 1,
wherein said insulating sheet has holes at positions corresponding to those of said connection pads.
3. The mounting structure of a semiconductor device as claimed in claim 1,
wherein, a gap between said insulating sheet and said wiring substrate is filled with resin and a gap between solder balls is free of resin.
4. A mounting structure of a semiconductor device comprising:
a semiconductor chip which is provided with a plurality of solder balls arranged in a grid array;
a wiring substrate which is provided with a plurality of connection pads; and
an insulating sheet which has a plurality of leads and which is provided between said semiconductor chip and said wiring substrate, wherein,
said plurality of solder balls are electrically connected through said leads to corresponding ones of said connection pads, respectively,
said insulating sheet has holes therethrough at positions corresponding to those of said connection pads,
one end of each of said leads is fixed on a first surface of said insulating sheet while the other end of each of said leads is shaped to be in a floated state in the corresponding one of said holes,
the other end of each of said leads protrudes from a second surface of said insulating sheet through the corresponding one of said holes, and
each of said solder balls of said semiconductor chip is electrically connected to said fixed one end of a corresponding one of said leads.
5. The mounting structure of a semiconductor device as claimed in claim 4,
wherein each of said connection pads is electrically connected to said other end of a corresponding one of said leads.
6. The mounting structure of a semiconductor device as claimed in claim 4,
wherein said leads are formed of a resilient conductive material.
7. The mounting structure of a semiconductor device as claimed in claim 4,
wherein said insulating sheet is made of any one of polyimide resin, Teflon resin, epoxy resin, and alumina resin.
8. A mounting structure of a semiconductor device, comprising:
a semiconductor chip having a plurality of solder balls arranged in a grid array;
a wiring substrate having a plurality of connection pads; and
an insulating sheet having a plurality of holes therethrough and leads passing through said holes, said insulating sheet being arranged between said semiconductor chip and said wiring substrate, wherein,
said leads connect said solder balls and said connection pads through said holes, and
a gap between said insulating sheet and said wiring substrate is filled with resin and a gap between solder balls is free of resin.
9. An insulating sheet provided between a semiconductor chip and a wiring substrate, comprising:
a plurality of holes therethrough; and
a plurality of leads, one end of each of said leads being fixed on a first surface of said insulating sheet and the other end of each of said leads being shaped to be afloat in said holes,
wherein said fixed one end of each of said leads includes a portion shaped to receive by direct contact, a corresponding one of a plurality of solder balls of a semiconductor chip, and said other end of each of said plurality of leads is shaped to contact with a corresponding one of a plurality of connection pads of a wiring substrate,
said portion being in contact with the first surface.
10. A mounting structure of a semiconductor device, comprising:
a semiconductor chip having a chip surface with a grid array of solder balls, the grid array being a first pattern;
a wiring substrate having a substrate surface with connection pads in a grid array of the first pattern,
the grid array of connection pads being out of vertical alignment with the grid array of the solder balls; and
an insulating sheet having a plurality of leads located intermediate the semiconductor chip and the wiring substrate,
the plurality of leads connecting ones of the solder balls with corresponding ones of the connection pads, wherein,
the leads pass through the holes; and
the leads include a fixed portion in contact with the solder balls, the fixed portion also being in contact with a surface of the insulating sheet.
11. The structure of claim 10, wherein the grid array of the first pattern comprises at least three parallel rows of array positions.
12. The structure of claim 10, wherein,
the insulating sheet comprises holes;
the leads pass through the holes; and
the leads include a fixed portion in contact with the solder balls, the fixed portion also being in contact with a surface of the insulating sheet.
13. The structure of claim 10, wherein the insulating sheet comprises an elongate hole corresponding to each of the parallel rows.
14. The structure of claim 10, wherein at least some of the connection pads of the grid array of connection pads are located within a vertical extension of a perimeter of the semiconductor chip.
15. A mounting structure of a semiconductor device, comprising:
a semiconductor chip having a chip surface with a grid array of solder balls, the grid array being a first pattern;
a wiring substrate having a substrate surface with connection pads in a grid array of the first pattern, the first pattern comprising a plurality of parallel rows
the grid array of connection pads being out of vertical alignment with the grid array of the solder balls; and
an insulating sheet having a plurality of leads located intermediate the semiconductor chip and the wiring substrate, the insulating sheet having elongate holes corresponding to each of the parallel row
the plurality of leads connecting ones of the solder balls with corresponding ones of the connection pads, wherein,
the elongate holes are filled with resin; and
a volume between the grid array of solder balls is free of resin.
16. A mounting structure of a semiconductor device, comprising:
a semiconductor chip having a chip surface with a grid array of solder balls, the grid array being a first pattern;
a wiring substrate having a substrate surface with connection pads in a grid array of the first pattern, the first pattern comprising a plurality of parallel rows
the grid array of connection pads being out of vertical alignment with the grid array of the solder balls; and
an insulating sheet having a plurality of leads located intermediate the semiconductor chip and the wiring substrate, the insulating sheet having holes corresponding to each of the parallel row
the plurality of leads connecting ones of the solder balls with corresponding ones of the connection pads, wherein,
the holes are filled with resin; and
a volume between the grid array of solder balls is free of resin.
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US6958262B2 (en) 2005-10-25
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US20040227224A1 (en) 2004-11-18
US20010017425A1 (en) 2001-08-30

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