US6867459B2 - Isotopically pure silicon-on-insulator wafers and method of making same - Google Patents

Isotopically pure silicon-on-insulator wafers and method of making same Download PDF

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US6867459B2
US6867459B2 US10/189,732 US18973202A US6867459B2 US 6867459 B2 US6867459 B2 US 6867459B2 US 18973202 A US18973202 A US 18973202A US 6867459 B2 US6867459 B2 US 6867459B2
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enriched
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Stephen J. Burden
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Tenoroc LLC
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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
    • C30B23/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/08—Germanium
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/52—Alloys
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64—Heat extraction or cooling elements
    • H01L33/641—Heat extraction or cooling elements characterized by the materials

Definitions

  • the present invention provides improved semiconductor wafer structures having isotopically-enriched layers and methods of making such wafers.
  • the invention provides a method of producing a semiconductor wafer structure by forming an isotopically-enriched semiconductor material layer on one surface of an electrically-insulating material.
  • the isotopically-enriched semiconductor material layer may be isotopically-enriched silicon, isotopically-enriched germanium, isotopically-enriched silicon-germanium alloys and combinations and alloys thereof.
  • the electrically-insulating material may be silicon dioxide or silicon nitride.

Abstract

The present invention provides improved semiconductor wafer structures having isotopically-enriched layers and methods of making the same.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of U.S. Provisional Application No. 60/303,455 filed Jul. 5, 2001, which is incorporated herein in its entirety by this reference.
FIELD OF THE INVENTION
The present invention relates to methods of making an improved semiconductor wafer structures having isotopically-enriched layers.
BACKGROUND OF THE INVENTION
Silicon on insulator (SOI) wafers are becoming an increasingly accepted form of silicon wafers for the manufacture of semiconductor devices. SOI wafers have a thin layer of silicon dioxide below the surface of the single crystal silicon wafer. This layer electrically isolates the surface layer from the bulk of the wafer and allows semiconductor devices to operate at higher speeds with lower power consumption. Thus, the wafer structure consists of a top single crystal silicon layer (the device layer), an amorphous silicon dioxide layer (the buried oxide or BOX layer), and a substrate or handle wafer. The handle wafer is typically a single crystal silicon wafer. A typical wafer structure is shown in FIG. 1 in which layer 1 is the top silicon layer, called the device layer wherein the semiconductor device is fabricated; layer 2 is the BOX or insulator layer; and layer 3 is the substrate.
Power dissipation in a semiconductor device is limited by the thermal conductivity of the materials from which it is made. This thermal conductivity in turn limits the packing density of the transistors on a semiconductor wafer or the amount of power that can be generated in a circuit without inducing circuit failure. Thus, one side effect of electrically isolating the top silicon layer with silicon dioxide is that the top layer is also thermally insulated from the silicon substrate. This accentuates the self-heating of circuits and can cause problems with high power devices such as microprocessors. Several designs have been proposed to overcome the detrimental effects of this thermal isolation including the use of local thermal paths to transport the heat through the oxide layer or the fabrication of a “partial” SOI wafer having areas of wafer without an oxide layer.
These designs are difficult and therefore expensive to implement. A novel solution provided by this invention is the use of high thermal conductivity silicon-28 in the manufacture of SOI wafers. By utilizing an isotopically-enriched silicon-28 device layer and/or an isotopically-enriched silicon-28 layer under the oxide, lateral heat spreading can be maximized. This is particularly true for thin-film SOI wafers where the top silicon layer is much less than one micron thick. With these wafers, the device layer can be natural silicon since the thermal transport in the device layer is controlled by interface scattering effects and not by the bulk properties of the silicon. In this case an underlayer of isotopically-enriched silicon helps greatly to spread the heat generated in the device layer. Silicon-28 can be incorporated without changing the device design and at relatively modest cost since the amount of silicon-28 in these thin layers is small. Fabricating isotopically modified SOI wafers allows for increased power densities in these devices, thereby enhancing the performance of many electronic devices now on the market.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides improved semiconductor wafer structures having isotopically-enriched layers and methods of making such wafers. In one embodiment, the invention provides a method of producing a semiconductor wafer structure by forming an isotopically-enriched semiconductor material layer on one surface of an electrically-insulating material. The isotopically-enriched semiconductor material layer may be isotopically-enriched silicon, isotopically-enriched germanium, isotopically-enriched silicon-germanium alloys and combinations and alloys thereof. The electrically-insulating material may be silicon dioxide or silicon nitride.
In another embodiment of the present invention, the semiconductor wafer structure has an isotopically-enriched 28Si layer on top of a layer composed of 28SiO2 or 28Si3N4 on top of an isotopically-enriched 28Si layer on top of a natural silicon substrate. The invention provides a method of making these wafers by forming an isotopically-enriched silicon semiconductor layer on one surface of a natural silicon substrate and implanting oxygen or nitrogen atoms into the isotopically-enriched silicon layer. The wafer is then annealed to form an isotopically-enriched 28Si layer on top of a layer having 28SiO2 or 28Si3N4 on top of an isotopically-enriched 28Si layer on top of a natural silicon substrate.
Another embodiment of the present invention is a method of forming a wafer structure having an isotopically-enriched layer and an electrically-insulating layer by bonding together an electrically-insulating layer between two substrates, each substrate comprising a semiconductor layer formed on the surface of the substrate. At least one of the semiconductor layers is isotopically-enriched. The substrate may then be removed to form a semiconductor wafer comprising a semiconductor device layer on an electrically-insulating layer on an isotopically-enriched semiconductor layer on a substrate.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic of the typical prior art wafer structure in which layer 1 is the top silicon layer, layer 2 is the BOX or insulator layer and layer 3 is the substrate.
FIG. 2 is a schematic of one wafer structure of the present invention in which Layer 4 is the top silicon layer or device layer, layer 5 is the buried oxide or insulator layer; layer 6 is the isotopically-enriched semiconductor material and layer 7 is the substrate.
 DETAILED DESCRIPTION OF THE INVENTION
In the naturally occurring form, silicon is composed of three stable isotopes; approximately 92.2% 28Si, 4.7% 29Si and 3.1% 30Si, which is roughly the composition of crystals and wafers used by the semiconductor industry. The presence of multiple isotopes contributes to phonon scattering which decreases the thermal conductivity of naturally occurring silicon.
Isotopically-enriched 28Si has been shown to have a thermal conductivity 60% to 600% higher than naturally occurring silicon as described in Capinski et al., Thermal Conductivity of Isotopically-enriched Si, Applied Physics Letters, v71, pp. 2109-11 (1997), and Ruf et al., Thermal Conductivity of Isotopically-enriched Silicon, Solid State Communications, v115, pp. 243-47 (2000), both of which are incorporated herein in their entirety by this reference. Isotopically-enriched means the silicon has a higher proportion of one of the isotopes of silicon than is present in naturally occurring silicon (e.g., it is composed of at least 98% 28Si).
Isotopically pure germanium has also demonstrated improved thermal conductivity over naturally occurring germanium crystals as described in Ozhogin et al, Isotope Effects in the Thermal Conductivity of Germanium Single Crystals, JETP Letters, Vol. 63, No. 6, pp490-494, (1996), and in Asen-Palmer et al, Thermal Conductivity of Germanium Crystals with different Isotopic Compositions, Physical Review B, Vol. 56, No. 15, pp 9431-9447, (1997) incorporated herein in its entirety by this reference. In the case of germanium, isotopically-enriched means the enriched germanium has a higher proportion of one of the isotopes of Ge than is present in naturally occurring germanium (e.g., it is composed of at least 80% 74Ge).
Higher thermal conductivity means devices fabricated from the high thermal conductivity wafer exhibit lower peak temperatures, faster device speeds and higher frequency performance than previous, conventional wafers. Lower temperatures will result in higher carrier mobility and reduced leakage currents which result in lower heat generation within the material. In addition, higher thermal conductivity means that it is possible to increase device packing densities within integrated circuit chip designs and to increase power output per unit area of power devices. Furthermore, the invention has applicability in device structures such as semiconductor laser arrays, micro-electromechanical devices(MEMS), micro-opto-electromechanical devices (MOEMS), optical switches, light emitting diodes, and laser diodes which utilize silicon substrates or silicon layers primarily for heat dissipation. The use of the present invention in such cases improves the thermal performance of the devices.
Any electronic device which relies on silicon, germanium, or Si—Ge alloys can be enhanced by the use of components made from the enriched isotopes to the extent that they impart improved thermal conductivity. Examples of such devices include integrated circuits, lasers, and diodes as described in U.S. Pat. No. 5,144,409 which is incorporated herein in its entirety by this reference.
One embodiment of the present invention is a wafer structure having a substrate and an isotopically-enriched layer formed on one surface of the substrate. The isotopically-enriched layer is composed of isotopically-enriched silicon, isotopically-enriched germanium, isotopically-enriched silicon-germanium alloys or combinations and alloys thereof. The isotopically-enriched layer serves to provide increased heat dissipation for the device. The wafer structure can be fabricated by forming a single-crystal layer composed of isotopically-enriched semiconductor materials on a layer of silicon dioxide, silicon nitride or other electrically insulating materials. The isotopically-enriched semiconductor layer is formed as a layer on one surface of a substrate by means of epitaxial deposition, layer transfer, wafer bonding of an isotopically-enriched semiconductor wafer, or other methods well known to those skilled in the art of semiconductor wafer manufacture.
In another embodiment of the present invention, a substantially pure silicon isotope (e.g. having a purity of at least 95%, more preferably at least 98%, more preferably at least 99.5%, and most preferably at least 99.9% silicon-28) is formed as a thin layer on one surface of a natural silicon substrate by epitaxial deposition. The epitaxial layer can be formed by techniques well known to those skilled in the art, such as chemical vapor deposition, molecular beam epitaxy, vapor phase epitaxy, liquid phase epitaxy, atomic layer deposition, or physical vapor deposition techniques. Oxygen or nitrogen atoms are then implanted into the top silicon layer using a standard silicon implantation of oxides (SIMOX) process to produce a silicon dioxide/silicon nitride layer under the surface after an annealing step at a temperature in the range of about 1100° C. to about 1300° C. The resulting wafer structure has a silicon-28 top layer, a 28SiO2 or 28Si3N4 layer, an underlying silicon-28 layer, and a natural silicon substrate. The starting silicon-28 epitaxial layer is preferably between about 0.5 and about 500 microns thick, depending on the heat removal required. A semiconductor device is formed in the top silicon-28 layer and the underlying silicon-28 layer acts a heat spreading layer to minimize the temperature build-up in the top device layer.
Another embodiment of the present invention provides a method of fabricating an isotopically-enriched semiconductor wafer in which two substrates having semiconductor layer on at least one surface, at least one of which is an isotopically-enriched semiconductor layer, are bonded together with an electrically-insulating layer between them. The substrate underlying the isotopically-enriched semiconductor layer is then removed to leave an isotopically-enriched layer bonded to the insulating layer on the remaining substrate. The final wafer structure consists of a natural or isotopically-enriched semiconductor device layer, an electrically-insulating layer, an isotopically-enriched semiconductor material and a substrate.
The top semiconductor material can be composed of two layers, one of pure silicon and a second layer of silicon-germanium alloy, and the bottom isotopically-enriched semiconductor material can be isotopically-enriched silicon to maximize thermal conductivity through the insulating layer. The first underlying substrate is substantially removed by means known to those skilled in the art including, for example, mechanical grinding, chemical etching, plasma etching, or a combination of these processes. The resulting semiconductor wafer produced by this method has a top semiconductor material layer that can be as thin or as thick as desired for electrical/device performance, and a second enriched semiconductor material layer that can be as thick as desired for thermal performance.
Another embodiment of the present invention is directed to a wafer structure including a substrate composed of an inexpensive material of suitable composition such as polycrystalline silicon, an electrically-insulating layer such as silicon dioxide, and an isotopically-enriched single-crystal silicon layer composed of at least 98% 28Si as a top layer. The isotopically-enriched semiconductor layer is formed as a layer on one surface of a natural silicon substrate by means of epitaxial deposition, this wafer is bonded to the polysilicon substrate material which has an oxidized surface, and the first natural silicon substrate is removed. Another fabrication method uses layer transfer technology, as described in U.S. Pat. Nos. 5,374,564, 6,391,740, 6,372,609, or 6,352,909, to bond a thin layer of a semiconductor material to a second wafer. The substrate is composed of one or more of a naturally-occurring single crystal or polycrystalline silicon substrate, or a silicon dioxide substrate in which the silicon may be naturally occurring silicon or an isotopically-enriched silicon. The silicon dioxide layer can be formed by thermal oxidation, chemical vapor deposition, or by oxygen implantation (SIMOX method). In one particularly preferred embodiment, an isotopically-enriched silicon layer is formed on a silicon dioxide layer on a natural silicon substrate.

Claims (5)

1. A semiconductor wafer structure comprising:
an isotopically-enriched semiconductor material layer on a first surface of silicon nitride; and
a layer of semiconductor material having natural isotopic ratios on a second surface of said silicon nitride, said second surface opposite said first surface, wherein:
said isotopically-enriched semiconductor material layer has a higher thermal conductivity than said layer of semiconductor material having natural isotopic ratios.
2. The wafer structure of claim 1, wherein the isotopically-enriched semiconductor material layer comprises a semiconductor material selected from the group consisting of isotopically-enriched silicon, isotopically-enriched germanium, silicon-germanium alloys and combinations and alloys thereof.
3. The semiconductor wafer structure of claim 1, wherein the isotopically-enriched semiconductor comprises silicon enriched to at least 98% 28Si.
4. The semiconductor wafer structure of claim 1, wherein the isotopically-enriched semiconductor comprises geranium enriched to at least 85% 74Ge.
5. The semiconductor wafer structure of claim 1, wherein the isotopically-enriched semiconductor comprises geranium enriched to at least 80% of one of the germanium isotopes.
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US10/746,426 US20040171226A1 (en) 2001-07-05 2003-12-24 Isotopically pure silicon-on-insulator wafers and method of making same
US10/746,427 US7119400B2 (en) 2001-07-05 2003-12-24 Isotopically pure silicon-on-insulator wafers and method of making same
US11/298,440 US20060091393A1 (en) 2001-07-05 2005-12-09 Isotopically pure silicon-on-insulator wafers and methods of making same

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US20160107879A1 (en) * 2014-10-20 2016-04-21 Infineon Technologies Ag Electronic device with suspended mass
US20170186693A1 (en) * 2015-12-29 2017-06-29 Globalfoundries Inc. Soi wafers with buried dielectric layers to prevent cu diffusion
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US10627696B1 (en) 2019-03-18 2020-04-21 Psiwuantum, Corp. Active photonic devices incorporating high dielectric constant materials
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