Patente US6950338 - Method for operating a memory device having an amorphous silicon carbide ...

A floating gate transistor has a reduced barrier energy at an interface with an adjacent amorphous silicon carbide (a-SiC) gate insulator, allowing faster charge transfer across the gate insulator at lower voltages. Data is stored as charge on the floating gate. The data charge retention time on the floating gate is reduced. The data stored on the floating gate is dynamically refreshed. The floating gate transistor provides a dense and planar dynamic electrically alterable and programmable read only memory (DEAPROM) cell adapted for uses such as for a dynamic random access memory (DRAM) or a dynamically refreshed flash EEPROM memory. The floating gate transistor provides a high gain memory cell and low voltage operation.

Inventores: Leonard Forbes, Joseph E. Geusic, Kie Y. Ahn
Cesionario original: Micron Technology Inc.
Examinador principal: Viet Q. Nguyen
Abogado: Schwegman, Lundberg, Woessner & Kluth, P.A.
Clasificación actual de EE.UU.: 36518514; 36518529; 36518501; 257/77; 257/316
Clasificación internacional: G11C016/04

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Reclamaciones

1. A method of using a floating gate transistor having a floating gate electrode and an adjacent amorphous silicon carbide (a-SiC) gate insulator between the floating gate electrode and substrate, the method comprising:

storing data by changing a charge of the floating gate electrode;

reading data by detecting a current between a source and a drain in the substrate; and

refreshing data based on a data charge retention time for the floating gate transistor that depends upon a barrier energy at an interface between the floating gate electrode and the gate insulator.

2. The method of claim 1, wherein reading data further comprises detecting an amplified current signal between the source and the drain.

3. The method of claim 1, wherein the detected current is based on the charge of the floating gate electrode and a transconductance gain of the floating gate transistor.

4. A method of using a floating gate transistor, comprising:

programming a floating gate electrode of the following gate transistor by placing a charge on the floating gate electrode, wherein the floating gate transistor has a barrier energy between the floating gate electrode and a silicon carbide (SiC) gate insulator separating the floating gate electrode from a substrate, the barrier energy being less than approximately 3.3 eV; and

reading the floating gate transistor by placing a read voltage on a control gate and detecting current in a channel between a source region and a drain region in the substrate.

5. The method of claim 4 wherein programming a floating gate electrode further comprises causing hot electron injection from the channel through an amorphous silicon carbide (a-SiC) gate insulator to the floating gate electrode.

6. The method of claim 4, further comprising erasing the floating gate transistor by applying an erase voltage to the floating gate transistor which is less than 12 Volts.

7. The method of claim 4, further comprising refreshing the charge placed on the floating gate electrode.

8. The method of claim 7, wherein refreshing the charge placed on the floating gate electrode further comprises refreshing the charge at regular time intervals of less than 40 seconds.

9. The method of claim 7, wherein refreshing the charge placed on the floating gate electrode further comprises refreshing the charge at regular time intervals.

10. A method for operating a floating gate transistor connected to a control line and a data line, the method comprising:

storing data on a floating gate electrode in the floating gate transistor by providing a control voltage on the control line and a write voltage on the data line such that charge is carried from a substrate to the floating gate electrode through a silicon carbide (SiC) gate insulator, wherein a barrier energy between the silicon carbide (SiC) gate insulator and the floating gate electrode is less than 3.3 eV;

reading the data stored on the floating gate electrode by placing a read voltage on the control line and detecting the current in the floating gate transistor at the data line; and

erasing the floating gate transistor by applying an erase voltage to the floating gate transistor which is less than 12 Volts.

11. The method of claim 10 wherein storing data further comprises causing the charge to be carried from the substrate to the floating gate electrode through an amorphous silicon carbide (a-SiC) gate insulator.

12. The method of claim 10, further comprising refreshing the charge placed on the floating gate electrode.

13. The method of calim 12 wherein refreshing the charge placed on the floating gate electrode further comprises refreshing the charge at regular time intervals of less than 40 seconds.

14. The method of claim 12 wherein refreshing the charge placed on the floating gate electrode further comprises refreshing the charge at regular time intervals.

15. A method for operating a floating gate transistor comprising:

programming the floating gate transistor by inducing charge to migrate from a channel in a substrate through an amorphous silicon carbide (a-SiC) gate insulator to a floating gate electrode in the floating gate transistor; and

erasing the floating gate transistor by inducing charge to migrate from the floating gate electrode through the amorphous silicon carbide (a-SiC) gate insulator to the channel.

16. The method of claim 15 wherein:

programming comprises programming the floating gate transistor by inducing hot electron injection from a channel in a substrate through the amorphous silicon carbide (a-SiC) gate insulator to a polysilicon floating gate electrode in the floating gate transistor; and

erasing comprises erasing the floating gate transistor by inducing charge to migrate from the polysilicon floating gate electrode through the amorphous silicon carbide (a-SiC) gate insulator to the channel through Fowler-Nordheim tunneling.

17. The method of claim 15, further comprising reading the floating gate transistor by detecting current in the floating gate transistor.

18. The method of claim 15, further comprising refreshing the floating gate transistor at regular time intervals.

19. A method for operating a floating gate transistor connected to a control line and a data line, the method comprising:

programming the floating gate transistor by providing a control voltage on the control line and a write voltage on the data line to induce charge to migrate from a channel in a substrate through an amorphous silicon carbide (a-SiC) gate insulator to a floating gate electrode in the floating gate transistor; and

erasing the floating gate transistor by inducing charge to migrate from the floating gate electrode through the amorphous silicon carbide (a-SiC) gate insulator to the channel.

20. The method of claim 19 wherein:

programming comprises programming the floating gate transistor by providing a control voltage on the control line and a write voltage on the data line to induce hot electron injection from a channel in a substrate through the amorphous silicon carbide (a-SiC) gate insulator to a polysilicon floating gate electrode in the floating gate transistor; and

erasing comprises applying an erase voltage of less than 12 Volts to the floating gate transistor to erase the floating gate transistor by inducing charge to migrate from the polysilicon floating gate electrode through the amorphous silicon carbide (a-SiC) gate insulator to the channel through Fowler-Nordheim tunneling.

21. The method of claim 19, further comprising reading the floating gate transistor by placing a read voltage on the control line and detecting current in the floating gate transistor.

22. The method of claim 19, further comprising refreshing the floating gate transistor at regular time intervals of less than 40 seconds.

23. The method of claim 1 wherein reading data comprises reading data by detecting a current between a source and a drain in a silicon substrate.

24. The method of claim 15 wherein programming comprises programming the floating gate transistor by inducing charge to migrate from a channel between a source and a drain in a silicon substrate through an amorphous silicon carbide (a-SiC) gate insulator to a floating gate electrode in the floating gate transistor.

25. The method of claim 19 wherein programming comprises programming the floating gate transistor by providing a control voltage on the control line and a write voltage on the data line to induce charge to migrate from a channel between a source and a drain in a silicon substrate through an amorphous silicon carbide (a-SiC) gate insulator to o floating gate electrode.

26. A method of using a floating gate transistor, comprising:

programming a floating gate electrode of the floating gate transistor by placing a charge on the floating gate electrode, wherein the floating gate transistor has a barrier energy between the floating gate electrode and an amorphous silicon carbide (a-SiC) gate insulator separating the floating gate electrode from a substrate, the barrier energy being less than approximately 3.3 eV; and

reading the floating gate transistor by placing a read voltage on a control gate and detecting current in a channel between a source region and a drain region in the substrate.

27. The method of claim 26, further comprising erasing the floating gate transistor by applying an erase voltage to the floating gate transistor which is less than 12 Volts.

28. The method of claim 26, further comprising refreshing the charge placed on the floating gate electrode.

29. The method of claim 28, wherein refreshing the charge placed on the floating gate electrode further comprises refreshing the charge at regular time intervals.

30. The method of claim 26 wherein programming further comprises programming the floating gate electrode by inducing charge to migrate from a channel between a source region and a drain region in a silicon substrate through the amorphous silicon carbide (a-SiC) gate insulator to the floating gate electrode.

31. A method for operating a floating gate transistor connected to a control line and a data line, the method comprising:

storing data on a floating gate electrode in the floating gate transistor by providing a control voltage on the control line and a write voltage on the data line such that charge is carried from a substrate to the floating gate electrode through an amorphous silicon carbide (a-SiC) gate insulator, wherein a barrier energy between the amorphous silicon carbide (a-SiC) gate insulator and the floating gate electrode is less than 3.3 eV;

reading the data stored on the floating gate electrode by placing a read voltage on the control line and detecting the current in the floating gate transistor at the data line; and

erasing the floating gate transistor by applying an erase voltage to the floating gate transistor.

32. The method of claim 31, further comprising refreshing the charge placed on the floating gate electrode.

33. The method of claim 32 wherein refreshing the charge placed on the floating gate electrode further comprises refreshing the charge at regular time intervals.

34. The method of claim 31 wherein erasing comprises erasing the floating gate transistor by applying an erase voltage to the floating gate transistor which is less than 12 Volts.

35. The method of claim 31 wherein storing data further comprises storing data on the floating gate electrode in the floating gate transistor by providing a control voltage on the control line and a write voltage on the data line such that charge is carried from a channel between a source region and a drain region in a silicon substrate to the floating gate electrode through the amorphous silicon carbide (a-SiC) gate insulator.

36. A method of using a floating gate transistor, comprising:

programming a floating gate electrode of the floating gate transistor by placing a charge on the floating gate electrode, wherein the floating gate transistor has a barrier energy between the floating gate electrode and a silicon carbide (SiC) gate insulator separating the floating gate electrode from a substrate, the barrier energy being less than approximately 3.3 eV;

reading the floating gate transistor by placing a read voltage on a control gate and detecting current in a channel between a source region and a drain region in the substrate; and

erasing the floating gate transistor.

37. The method of claim 36 wherein:

programming a floating gate electrode further comprises causing hot electron injection from the channel through an amorphous silicon carbide (a-SiC) gate insulator to the floating gate electrode;

erasing the floating gate transistor comprises erasing the floating gate transistor by applying an erase voltage to the floating gate transistor which is less than 12 Volts; and

further comprising refreshing the charge placed on the floating gate electrode at regular time intervals.

38. A method of using a floating gate transistor, comprising:

programming a floating gate electrode of the floating gate transistor by placing a charge on the floating gate electrode, wherein the floating gate transistor has a barrier energy between the floating gate electrode and a silicon carbide (SiC) gate insulator separating the floating gate electrode from a substrate, the barrier energy being less than approximately 3.3 eV;

reading the floating gate transistor by placing a read voltage on a control gate and detecting current in a channel between a source region and a drain region in the substrate; and

refreshing the charge placed on the floating gate electrode.

39. The method of claim 38 wherein:

programming a floating gate electrode further comprises causing hot electron injection from the channel through an amorphous silicon carbide (a-SiC) gate insulator to the floating gate electrode;

refreshing the charge comprises refreshing the charge placed on the floating gate electrode at regular time intervals; and

further comprising erasing the floating gate transistor by applying an erase voltage to the floating gate transistor which is less than 12 Volts.

40. A method of using a floating gate transistor, comprising:

programming a floating gate electrode of the floating gate transistor by placing a charge on the floating gate electrode, wherein the floating gate transistor has a barrier energy between the floating gate electrode and a silicon carbide (SiC) gate insulator separating the floating gate electrode from a substrate, the barrier energy being less than approximately 3.3 eV;

reading the floating gate transistor by placing a read voltage on a control gate and detecting current in a channel between a source region and a drain region in the substrate;

refreshing the charge placed on the floating gate electrode; and

erasing the floating gate transistor.

41. The method of claim 40 wherein:

programming a floating gate electrode further comprises causing hot electron injection from the channel through an amorphous silicon carbide (a-SiC) gate insulator to the floating gate electrode;

refreshing the charge comprises refreshing the charge placed on the floating gate electrode at regular time intervals; and

erasing the floating gate transistor comprises erasing the floating gate transistor by applying an erase voltage to the floating gate transistor which is less than 12 Volts.

42. A method for operating a floating gate transistor comprising:

reading the floating gate transistor; and

erasing the floating gate by inducing charge to migrate from the floating gate electrode through the amorphous silicon carbide (a-SiC) gate insulator to the channel.

43. The method of claim 42 wherein:

reading the floating gate transistor comprises reading the floating gate transistor by detecting current in the floating gate transistor;

further comprising refreshing the floating gate transistor at regular time intervals.

44. A method for operating a floating gate transistor comprising:

refreshing the floating gate transistor; and

erasing the floating gate transistor by inducing charge to migrate from the floating gate electrode through the amorphous silicon carbide (a-SiC) gate insulator to the channel.

45. The method of claim 44 wherein:

refreshing the floating gate transistor comprises refreshing the floating gate transistor at regular time intervals; and

further comprising reading the floating gate transistor by detecting current in the floating gate transistor.

46. A method for operating a floating gate transistor comprising:

refreshing the floating gate transistor;

reading the floating gate transistor; and

erasing the floating gate transistor by inducing charge to migrate from the floating gate electrode through the amorphous silicon carbide (a-SiC) gate insulator to the channel.

47. The method of claim 46 wherein:

refreshing the floating gate transistor comprises refreshing the floating gate transistor at regular time intervals; and

reading the floating gate transistor comprises reading the floating gate transistor by detecting current in the floating gate transistor.

Dibujos

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Method for operating a memory device having an amorphous silicon carbide ...

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