|Número de publicación||US6960931 B2|
|Tipo de publicación||Concesión|
|Número de solicitud||US 10/283,721|
|Fecha de publicación||1 Nov 2005|
|Fecha de presentación||30 Oct 2002|
|Fecha de prioridad||30 Oct 2002|
|También publicado como||US20050073338|
|Número de publicación||10283721, 283721, US 6960931 B2, US 6960931B2, US-B2-6960931, US6960931 B2, US6960931B2|
|Cesionario original||International Business Machines Corporation|
|Exportar cita||BiBTeX, EndNote, RefMan|
|Citas de patentes (5), Otras citas (1), Citada por (9), Clasificaciones (10), Eventos legales (4)|
|Enlaces externos: USPTO, Cesión de USPTO, Espacenet|
1. Technical Field
The current invention relates to low voltage differential signal (LVDS) drivers. In particular, this invention relates to a LVDS circuit and method that generate the output signals using a network of matched resistors that are configured based on a switching sequencer.
2. Background Art
Current trends in computer hardware are toward higher frequency applications. As a result, bandwidth interfaces in excess of one gigabit per second are now becoming more common. However, the speed in which board components in hardware such as routers, ethernet communications, and cellular telephone base stations interface is limited by physical constraints including board space, chip pin quantities, etc. As a result, currently available bandwidth capabilities exceed the limitations of current printed circuit board and chip packaging technologies.
LVDS drivers provide one solution to this problem. An LVDS driver represents a digital value as a differential voltage signal. The differential voltage signal is represented by the voltage difference between two output lines. The signals on the two output lines always complement each other with a higher voltage on a first line representing a digital value of one, and a higher voltage on the second line representing a digital value of zero.
The Institute for Electrical and Electronic Engineers, Inc. (IEEE) Standard 1596 addresses LVDS performance requirements. Under the standard, an LVDS driver transmits a low voltage differential signal to a resistively terminated differential receiver. The differential receiver resolves the true signal by amplifying the voltage difference across the termination resistor. The amplified signal is clamped to ground or to the power supply voltage (Vdd), and is available for use by the internal logic elements on the receiver.
Current implementations of the LVDS circuit typically include one or more current sources and sinks. The current source is used to provide the ‘Hi’ signal, and the current sink provides the ‘Lo’ signal. The ‘Hi’ and ‘Lo’ signals are matched using a current mirror. However, implementation of the current mirror includes several limitations that make compliance with IEEE Std 1596 difficult. For example, the standard specifies that an impedance at each output be between 40 Ohms and 140 Ohms. Because an ideal current source represents infinite impedance, it is difficult to construct current source and sink elements that meet this standard. Similarly, it is difficult to construct a circuit having an impedance difference between both output signals within the ten percent error specified by IEEE.
Additionally, IEEE Std 1596 specifies that the output offset voltage (Vos) must be regulated between 1.125 V and 1.275 V. Current LVDS circuit implementations frequently use a feedback circuit in conjunction with a voltage reference to satisfy this IEEE specification. In this case, a driver's output voltages are sensed and compared with a reference voltage. The output voltages are then modified as required to match the reference value. However, the addition of a feedback stage requires considerable analysis in order to insure stability and to minimize drift in the output voltages. Further, the use of a feedback amplifier also requires considerable time (i.e., more than 10 nanoseconds) for the circuit to recover from being tristated (disabled).
As a result, there exists a need for a LVDS circuit and method that eliminate the complexities and deficiencies of the current techniques. In particular, there exists a need for an LVDS circuit in which a desired impedance value and balance can be easily obtained. Further, there exists a need for a LVDS circuit and method that allow for quicker recovery from tristate. Still further, there exists a need for a LVDS circuit and method that solve the above needs while being compatible with the relevant specifications of IEEE Std 1596.
The current invention provides a method and circuit for generating a differential voltage signal. A digital input is provided to a switching sequencer that provides for uniform transitions between voltage signals at the output pads. A driver generates each voltage signal using a network of matched resistors.
A first aspect of the invention provides a differential signal driver, comprising: a driver for generating a first output signal and a second output signal, the driver including an output stage comprising a network of matched resistors; and a switching sequencer for ensuring uniform transitions of the first output signal and the second output signal.
A second aspect of the invention provides a circuit for generating a differential voltage signal, comprising: a first resistor network for generating a first voltage level at a first output; and a second resistor network for generating a second voltage level at a second output; wherein the first resistor network and the second resistor network are substantially identical, and wherein the first voltage level and the second voltage level transitions are based on a plurality of sequencing signals.
A third aspect of the invention provides a method of generating a differential voltage signal, comprising: receiving a digital input; providing a plurality of sequencing signals based on the digital input; configuring a first resistor network and a second resistor network based on the plurality of sequencing signals; generating a first voltage at a first output based on the first resistor network; and generating a second voltage at a second output based on the second resistor network, wherein a difference of the first voltage and the second voltage comprises the differential voltage signal.
The illustrative aspects of the present invention are designed to solve the problems herein described and other problems not discussed, which are discoverable by a skilled artisan.
These and other features of this invention will be more readily understood from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings in which:
It is noted that the drawings of the invention are not to scale. The drawings are intended to depict only typical aspects of the invention, and therefore should not be considered as limiting the scope of the invention. In the drawings, like numbering represents like elements between the drawings.
The current invention provides a LVDS circuit and method that generate the output signals using a network of matched resistors for generating the output signals, and a switching sequencer for ensuring uniform transitions of the output signals.
Turning to the figures,
Circuit 10 includes a switching sequencer 20 and a driver 22. Switching sequencer 20 accepts input 12 and produces a plurality of sequencing signals 24. Sequencing signals 24 are provided to driver 22 for generating uniform transitions of the output signals between high and low voltages at outputs 16, 18.
The output of each inverter 40 is provided as one of sequencing signals 24. For example, inverter 40A provides sequencing signal 24A, while inverter 40B provides sequencing signal 24B. As a result, half of sequencing signals 24 provide the true value of input 12, while half provide the complement of the value of input 12. Further, since each inverter 40 takes a finite amount of time to process an input signal and produce an output signal, sequencing signals 24 are provided at different times. For example, sequencing signal 24A only passes through inverter 40A before being produced, while sequencing signal 24B passes through inverters 40A, 40B before being produced. The size and loading of each inverter 40 is matched to provide a uniform propagation of sequencing signals 24. The size, loading, and number of inverters 40 is selected so that the outputs transition between high and low voltages within a desired minimum and maximum transition time, i.e., to obtain the desired slew rate.
For precise control of the output signals, control stage 26 should produce the four control signals 30 for each sequencing signal 24 as close in time as possible. However, NAND and NOR circuits do not behave symmetrically. To minimize the time window during which the four control signals are produced, the NAND and NOR circuits can be implemented using a passgate technique. Using this technique, the NAND and NOR logic functions can be implemented in functionally balanced circuits.
Using this circuit, the signal at junction 43 is equivalent to NOT input 12 since switching signal 24B represents the true value of input 12. The passgate technique generates a signal at junction 42 that is either high when enable 14 is low, or is the value of NOT input 12. Therefore, the signal at junction 42 represents the logical expression: NOT input 12 OR NOT enable 14. This value is logically equivalent to the desired signal at control signal 30A of: enable 14 NAND input 12, and its complement at control signal 30B can be logically stated as: enable 14 AND input 12.
Similarly, the passgate technique generates a signal at junction 44 that is only high when enable 14 is high and the value of NOT input 12 is high. Therefore, the signal at junction 44 represents the logical expression: NOT input 12 AND enable 14. This is logically equivalent to the desired signal at control signal 30D of: NOT enable 14 NOR input 12, and its complement signal at control signal 30C can be represented as: NOT enable 14 OR input 12.
The signal 24A represents the complement of input 12. Consequently the value at junction 47 is equivalent to input 12. Based on the discussion above, the value at junction 46 is the complement of the value at junction 44, and the value at junction 48 is the complement of the value at junction 42. As a result, control signals 30A and 30B are generated from junction 48, while control signals 30C and 30D are generated from junction 46.
As depicted, the network for generating the output signal at output 16 can be reduced to the parallel combination of resistors 50, 52 connected to Vdd, and a resistor 54 connected to ground. Each resistor 50, 52, 54 is gated using switches 56, 58, 60, respectively. In operation, switch 56 is only open when the enable signal goes low, i.e., the device is tristated, switch 58 is closed when the device is not tristated and the input is high, and switch 60 is closed when the device is not tristated and the input is low. Consequently, during normal operation, switch 58 and switch 60 are complementary, while switch 56 is always closed. Therefore, current always flows through resistor 50, current flows through resistor 52 when the input is high, and current flows through resistor 54 when the input is low. This operation results in the signal at output 16 being pulled high when the input is high, and pulled low when the input is low.
Since the signal at output 18 is low when the input is high, and high when the input is low, the network for generating the output signal at output 18 functions in a similar manner, but in the reverse. The network also can be reduced to the parallel combination of resistors 62, 64 connected to Vdd, a resistor 66 connected to ground, and switches 68, 70, 72 controlling current flow through resistors 62, 64, 66, respectively. When tristated, switches 68, 70, 72 are all open. During normal operation, switch 70 is closed, switch 68 is closed when the input is low, and switch 72 is closed when the input is high.
As shown, resistor 50 is connected in parallel with resistor 52. When the circuit is viewed from an AC standpoint, the Vdd node can be considered as being connected to an ideal voltage source across Vdd and ground. Since an ideal voltage source has zero impedance, resistor 50 and resistor 54 can also be viewed as a parallel combination of resistors. The parallel combination of resistors can be selected to result in a desired effective impedance and the desired offset voltage.
The circuit is also shown including nfet devices 61, 73 in series with nfet devices 60, 72 respectively. The enables of nfet devices 61, 73 are shown tied to Vdd so that the devices are always enabled and do not impact operation of output stage 28. The inclusion of nfet devices 61, 73 simplifies the matching of impedances and predriver loadings with the pfet devices since nfet devices generally perform substantially better than pfet devices. Additionally, nfet devices have a lower stress tolerance to external voltages than pfet devices. Consequently, the inclusion of the second nfet devices 61, 73 also provides additional tolerance to withstand external voltage spikes.
Because of the balanced configuration of the network of matched resistors, the transition between voltages at outputs 16, 18 occurs in a highly symmetric fashion. Using the passgate implementation shown in
The illustrative circuit and method described above have been configured to perform according to the standards required in IEEE Std 1596 and are not meant to limit the invention to this particular circuit and method. Consequently, it is optimized to support system applications in which a 100 Ohm termination resistor is connected across the input pins of a differential receiver. Obviously, numerous modifications to the circuit and method can be made to improve/reduce performance abilities. For example, in
Similarly, under IEEE Std 1596, outputs 16, 18 must maintain voltages roughly between 1.0 V and 1.4 V. As shown in
The foregoing description of various aspects of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously, many modifications and variations are possible. Such modifications and variations that may be apparent to a person skilled in the art are intended to be included within the scope of the invention as defined by the accompanying claims.
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|Clasificación de EE.UU.||326/30, 326/32, 326/34|
|Clasificación internacional||H03K17/16, H04L25/02|
|Clasificación cooperativa||H03K17/164, H04L25/0286, H04L25/0272|
|Clasificación europea||H03K17/16B2B2, H04L25/02K7E|
|30 Oct 2002||AS||Assignment|
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TURCOTTE, MARC;REEL/FRAME:013473/0381
Effective date: 20021030
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