US6974735B2 - Dual layer Semiconductor Devices - Google Patents
Dual layer Semiconductor Devices Download PDFInfo
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- US6974735B2 US6974735B2 US10/216,085 US21608502A US6974735B2 US 6974735 B2 US6974735 B2 US 6974735B2 US 21608502 A US21608502 A US 21608502A US 6974735 B2 US6974735 B2 US 6974735B2
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 239000002355 dual-layer Substances 0.000 title description 3
- 230000005428 wave function Effects 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 description 218
- 229910052710 silicon Inorganic materials 0.000 description 60
- 239000010703 silicon Substances 0.000 description 60
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 50
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 43
- 239000000758 substrate Substances 0.000 description 42
- 230000037230 mobility Effects 0.000 description 37
- 229910052732 germanium Inorganic materials 0.000 description 31
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 26
- 239000000203 mixture Substances 0.000 description 13
- 235000012431 wafers Nutrition 0.000 description 9
- 229910006990 Si1-xGex Inorganic materials 0.000 description 8
- 229910007020 Si1−xGex Inorganic materials 0.000 description 8
- 229910045601 alloy Inorganic materials 0.000 description 6
- 239000000956 alloy Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 230000008859 change Effects 0.000 description 5
- 230000007423 decrease Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000002955 isolation Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000006872 improvement Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 239000007795 chemical reaction product Substances 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- -1 e.g. Substances 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/933—Germanium or silicon or Ge-Si on III-V
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
where Ki=CvsatCoxWi, “i” represents p or n, and tp is the total inverter delay time. The delay is related to the ability of the NMOS and PMOS transistors to drive the inverter capacitance, CL. Kp and Kn are, respectively, related to the transconductance of the PMOS and NMOS transistors. C is a constant, Vsat is the saturation velocity of the carrier in the channel, Cox is the gate capacitance per unit area, and Wi is the width of the corresponding NMOS or PMOS transistor (i.e., the width of the gate).
where B is a constant, ep is the enhancement factor in PMOS drive current due to channel improvement relative to a standard silicon component (e.g., through use of strained-silicon), en is the enhancement factor in NMOS drive current, ωp is any relative width change in the PMOS transistor (new width divided by the width of standard a standard silicon PMOS component in a reference standard inverter), and ωn is any relative width change in the NMOS transistor. This expression is an approximation because any large change in device width can affect the constant B, which is associated with the overall inverter capacitance.
TABLE I | |||||||
Row | ωn | ωp | en | ep | |
||
1 | 1 | 1 | 1 | 1 | 1 | ||
2 | 1 | 1 | 1.8 | 1 | 0.78 | ||
3 | 1 | 1 | 1.8 | 1.8 | 0.56 | ||
4 | 1 | 1 | 1.8 | 7 | 0.35 | ||
5 | 2 | 1 | 1.8 | 7 | 0.21 | ||
6 | 2 | 1 | 2.17 | 7 | 0.19 | ||
7 | 2 | 1.17 | 2.17 | 7 | 0.176 | ||
Claims (2)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/216,085 US6974735B2 (en) | 2001-08-09 | 2002-08-09 | Dual layer Semiconductor Devices |
US11/130,575 US7465619B2 (en) | 2001-08-09 | 2005-05-17 | Methods of fabricating dual layer semiconductor devices |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US31118801P | 2001-08-09 | 2001-08-09 | |
US10/216,085 US6974735B2 (en) | 2001-08-09 | 2002-08-09 | Dual layer Semiconductor Devices |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US11/130,575 Continuation US7465619B2 (en) | 2001-08-09 | 2005-05-17 | Methods of fabricating dual layer semiconductor devices |
Publications (2)
Publication Number | Publication Date |
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US20030057439A1 US20030057439A1 (en) | 2003-03-27 |
US6974735B2 true US6974735B2 (en) | 2005-12-13 |
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Application Number | Title | Priority Date | Filing Date |
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US10/216,085 Expired - Lifetime US6974735B2 (en) | 2001-08-09 | 2002-08-09 | Dual layer Semiconductor Devices |
US11/130,575 Expired - Lifetime US7465619B2 (en) | 2001-08-09 | 2005-05-17 | Methods of fabricating dual layer semiconductor devices |
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US11/130,575 Expired - Lifetime US7465619B2 (en) | 2001-08-09 | 2005-05-17 | Methods of fabricating dual layer semiconductor devices |
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US20050151134A1 (en) * | 2003-01-15 | 2005-07-14 | Sharp Laboratories Of America, Inc. | Method for isolating silicon germanium dislocation regions in strained-silicon CMOS applications |
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US7253045B1 (en) * | 2004-07-13 | 2007-08-07 | Advanced Micro Devices, Inc. | Selective P-channel VT adjustment in SiGe system for leakage optimization |
US20080128747A1 (en) * | 2001-06-18 | 2008-06-05 | Lee Minjoo L | STRUCTURE AND METHOD FOR A HIGH-SPEED SEMICONDUCTOR DEVICE HAVING A Ge CHANNEL LAYER |
US20080274626A1 (en) * | 2007-05-04 | 2008-11-06 | Frederique Glowacki | Method for depositing a high quality silicon dielectric film on a germanium substrate with high quality interface |
US7566606B2 (en) | 2002-06-07 | 2009-07-28 | Amberwave Systems Corporation | Methods of fabricating semiconductor devices having strained dual channel layers |
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US20030057439A1 (en) | 2003-03-27 |
US7465619B2 (en) | 2008-12-16 |
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