|Número de publicación||US7057882 B2|
|Tipo de publicación||Concesión|
|Número de solicitud||US 11/222,964|
|Fecha de publicación||6 Jun 2006|
|Fecha de presentación||12 Sep 2005|
|Fecha de prioridad||13 Sep 2004|
|También publicado como||CN1750194A, CN100538941C, US20060056136|
|Número de publicación||11222964, 222964, US 7057882 B2, US 7057882B2, US-B2-7057882, US7057882 B2, US7057882B2|
|Inventores||Tatsuo Fujii, Junichi Kurita, Yuji Midou, Tsuyoshi Yoshino|
|Cesionario original||Matsushita Electric Industrial Co., Ltd.|
|Exportar cita||BiBTeX, EndNote, RefMan|
|Citas de patentes (5), Citada por (25), Clasificaciones (14), Eventos legales (4)|
|Enlaces externos: USPTO, Cesión de USPTO, Espacenet|
1. Field of the Invention
The present invention relates to a capacitor used in various types of electronic appliances, and more specifically, to a chip solid electrolytic capacitor having a solid electrolyte made of conductive polymer.
2. Background Art
Electronic appliances are being designed to operate at higher and higher frequencies; consequently, capacitors as an electronic component are being required to have excellent impedance characteristics in higher frequencies than before. In order to meet this demand, various types of solid electrolytic capacitors are being developed which have a solid electrolyte made of conductive polymer high in electric conductivity.
On the other hand, solid electrolytic capacitors used in the CPU periphery of personal computers are strongly expected to shrink in size and grow in capacity. Furthermore, as circuits are operated at higher and higher frequencies, capacitors are strongly required to have not only lower ESR (Equivalent Series Resistance) but also lower ESL (Equivalent Series Inductance) as well as excellent noise rejection and excellent transient response.
Anode terminal 18 includes anode electrode connection 18A to be connected to anode electrodes 14 of laminated body 17. Cathode terminal 19 includes cathode electrode connection 19A to be connected to cathode electrodes 16 of laminated body 17. Packaging resin 21 covers laminated body 17, anode electrode connection 18A and cathode electrode connection 19A.
In the conventional chip solid electrolytic capacitor thus structured, anode terminal 18 and cathode terminal 19 are aligned in a same plane with a distance of 0.2 to 2.0 mm between them. This arrangement allows the current for charging the chip solid electrolytic capacitor to flow in a loop, passing through anode terminal 18, anode electrode connection 18A, laminated body 17, cathode electrode connection 19A and cathode terminal 19 in this order. The loop area is so small that the ESL can be reduced to about 580 pH, for example. Such a chip solid electrolytic capacitor is disclosed in Japanese Patent Unexamined Publication No. 2004-95816.
Thus, in the conventional chip solid electrolytic capacitor, the ESL is reduced by aligning anode terminal 18 and cathode terminal 19 flush with and close to each other. However, further reduction in ESL is required in order to meet the recent demand in the market.
An object of the present invention is to provide a chip solid electrolytic capacitor with lower ESL than before. The chip solid electrolytic capacitor of the present invention includes a capacitor element, an anode lead frame, a cathode lead frame and packaging resin. The capacitor element has an anode portion and a cathode portion. The anode lead frame includes a plane, an anode junction and an anode terminal for surface mounting. The anode junction is formed on one end of the plane so as to be connected to the anode portion of the capacitor element. The anode terminal is formed on the side opposite to the anode junction with respect to the plane. The cathode lead frame has a plane and a cathode terminal for surface mounting. The plane of the cathode lead frame mounts the cathode portion of the capacitor element thereon in such a manner as to be connected to the cathode portion, and is stacked on the plane of the anode lead frame, while being insulated from it. The cathode terminal is formed on the same side as the anode terminal with respect to the plane. The packaging resin has a surface to be mounted, and covers at least the capacitor element, with the anode terminal and the cathode terminal exposed on the surface to be mounted. In the chip solid electrolytic capacitor of the present invention, the cathode lead frame and the anode lead frame are stacked with each other so as to make currents flowing through them in opposite directions. This cancels out the electromagnetic effects of the currents flowing through these lead frames, thereby greatly reducing the ESL.
Exemplary Embodiments of the present invention will be described as follows with reference to accompanying drawings. Note that the components which are substantially the same are labeled with the same reference marks in the embodiments, and the detailed description is not repeated.
Each of capacitor elements 1 includes anode body 30, which is made of aluminum foil as a valve metal and is formed by roughening the surface of the aluminum foil and applying dielectric oxide film 31 on the surface. Anode body 30 is provided with insulating portion 32 in a predetermined position so as to be divided into anode portion 1A and cathode portion 1B. On dielectric oxide film 31 in cathode portion 1B are formed solid electrolyte layer 33 made of conductive polymer and cathode layer 34 made of carbon and silver paste. Solid electrolyte layer 33 and cathode layer 34 are laminated in this order.
Anode lead frame 2 has anode junction 2B to be connected to anode portions 1A of capacitor elements 1 on one end of plane 2A, which is a first plane. Anode lead frame 2 further has, on its bottom surface, anode terminals 2C for surface mounting. Anode terminals 2C are projected from plane 2A towards the side of bottom surface 4A of packaging resin 4 by bending the frame substrate. Bottom surface 4A is a surface to be mounted. Thus, anode junction 2B and anode terminals 2C are formed on opposite sides with respect to plane 2A.
Cathode lead frame 3 has plane 3A, which is a second plane, cathode terminals 3B for surface mounting, and guide walls 3C. Plane 3A mounts cathode portions 1B of capacitor elements 1 thereon in such a manner as to be connected to cathode portions 1B. Plane 3A is stacked on plane 2A of anode lead frame 2 via an unillustrated insulating layer disposed on plane 2A. In other words, plane 2A and plane 3A are insulated from each other. This insulating layer can be formed of polyimide film having a thickness of about 10 μm or by printing resin. Cathode terminals 3B are provided on the bottom surface of cathode lead frame 3. Cathode terminals 3B are projected from plane 3A towards the side of bottom surface 4A in such a manner as to have U-shaped side faces by bending the frame substrate. In other words, cathode terminals 3B are formed on the same side as anode terminals 2C with respect to plane 3A. Guide walls 3C stand on the top surface of plane 3A so as to position cathode portions 1B of capacitor elements 1. Guide walls 3C may be fixed to cathode portions 1B. Thus, cathode terminals 3B and guide walls 3C are formed on opposite sides relative to each other with respect to plane 3A.
Packaging resin 4, which is electrically insulating, covers capacitor elements 1, anode lead frame 2 and cathode lead frame 3 collectively in such a manner as to expose anode terminals 2C and cathode terminals 3B on bottom surface 4, which is the surface to be mounted. In other words, packaging resin 4 covers at least capacitor elements 1.
A method for manufacturing the chip solid electrolytic capacitor of the present embodiment will be described as follows. As a first step, cathode portions 1B of capacitor elements 1 are mounted on plane 3A of cathode lead frame 3, and then capacitor elements 1 and cathode lead frame 3 are connected to each other electrically and mechanically with a conductive adhesive. In this case, a single capacitor element may be used or a plurality of capacitor elements may be laminated as shown in
As a next step, plane 3A is stacked on plane 2A of anode lead frame 2 via an unillustrated insulating layer disposed between these planes. Then, anode portions 1A projected from cathode lead frame 3 are mounted on anode junction 2B formed on anode lead frame 2. Anode junction 2B is then bent to hold anode portions 1A and subjected to laser welding. As a result, anode lead frame 2 is connected to anode portions 1A of capacitor elements 1 electrically and mechanically.
As a final step, capacitor elements 1, anode lead frame 2 and cathode lead frame 3 are collectively covered with insulating packaging resin 4 in such a manner as to expose anode terminals 2C and cathode terminals 3B on bottom surface 4, which is the surface to be mounted. This is the completion of the chip solid electrolytic capacitor of the present embodiment.
In the chip solid electrolytic capacitor of the present embodiment thus structured, cathode lead frame 3 and anode lead frame 2 are stacked with each other. Furthermore, the direction in which current flows through cathode lead frame 3 and the direction in which current flows through anode lead frame 2 are opposite to each other. This structure cancels out the electromagnetic effects of the currents flowing through these lead frames, thereby greatly reducing the ESL. When a capacitor having the same capacity as the capacitor described above in the Background Art section is manufactured and measured for its ESL value, the obtained ESL value is as low as 271 pH, which indicates a reduction of about 53%.
In order to obtain great effects in ESL reduction with this structure, it is preferable that plane 2A and plane 3A have substantially the same shape and substantially the same area size. It is also preferable that the surfaces to be mounted of anode terminals 2C and those of cathode terminals 3B be in the same plane and close to each other. This can reduce the ESL.
At least one of anode terminals 2C and cathode terminals 3B are preferably provided in plural. The effects of this will be described in detail in a second exemplary embodiment.
Anode lead frame 5 has anode junction 5B and anode terminals 5C for surface mounting on the opposite sides of plane 5A, which is a first plane. Anode junction 5B is formed on one end of plane 5A and is connected to anode portions 1A of capacitor elements 1. Similar to the first exemplary embodiment, anode terminals 5C are provided on the bottom surface of anode lead frame 5. Anode terminals 5C of the present embodiment are formed together with plane 5A by etching the area of the frame substrate other than anode terminals 5C. In other words, anode terminals 5C are thick-walled parts projected from plane 5A towards the side of bottom surface 4A, which is a surface to be mounted. Thus, anode terminals 5C are projected from plane 5A towards the side of the surface to be mounted.
Cathode lead frame 6 has plane 6A, which is a second plane, cathode terminals 6B for surface mounting, and guide walls 6C. Plane 6A and guide walls 6C are substantially the same as plane 3A and guide walls 3C, respectively, described in the first exemplary embodiment. More specifically, plane 6A mounts cathode portions 1B of capacitor elements 1 thereon, and is connected to cathode portions 1B. Plane 6A is then stacked on plane 5A of anode lead frame 5 via an unillustrated insulating layer disposed between these planes. Guide walls 6C are provided on the top surface side of plane 6A so as to position and fix cathode portions 1B of capacitor elements 1. Cathode terminals 6B are formed together with plane 6A by etching the area of the frame substrate other than cathode terminals 6B. In other words, cathode terminals 6B are thick-walled parts projected from plane 6A towards the side of bottom surface 4A, which is the surface to be mounted.
The chip solid electrolytic capacitor of the present embodiment thus structured has an ESL value as low as 248 pH. Thus, the chip solid electrolytic capacitor of the present embodiment has a greatly reduced ESL level in the same manner as in the first exemplary embodiment. Furthermore, since being formed by etching the frame substrate, anode terminals 5C and cathode terminals 6B have better dimensional precision and are simpler in assembly than in the first exemplary embodiment.
In the present embodiment, anode terminals 5C and cathode terminals 6B are formed by etching the respective frame substrates and being projected from planes 5A and 6A, respectively, towards the side of the surface to be mounted. However, the present invention is not limited to this structure. Terminals 5C and 6B, which are thick-walled parts, may be formed by press working instead of etching. Although both of anode terminals 5C and cathode terminals 6B are formed as thick-walled parts in the present embodiment, one may be formed as thick-walled parts and the other may be formed as bent parts as in the first exemplary embodiment.
The more anode and cathode terminals 5C and 6B that are provided, the better.
Note that increasing the number of the anode and cathode terminals and disposing them as close to each other as possible may be applied to the structure of the first exemplary embodiment.
The chip solid electrolytic capacitor of the present embodiment is identical to either of that of the first and second exemplary embodiment except that the anode terminals and the cathode terminals are exposed on both bottom surface 4A and side surface 4B of packaging resin 4. In the case where the chip solid electrolytic capacitor is mounted on an unillustrated circuit board, it is easy to check solder fillets.
As shown in the bottom view of
Similar to the third exemplary embodiment, this structure facilitates the checking of solder fillets from the top view when the chip solid electrolytic capacitor is mounted on an unillustrated circuit board.
It is preferable that depressions, which are not illustrated, be formed on side surface 4B of packaging resin 4 in order to accommodate parts of anode terminals 11 and cathode terminals 12 bent upward along side surface 4B. The provision of the depressions can downsize the chip solid electrolytic capacitor of the present embodiment.
As described above, in the chip solid electrolytic capacitor of the present invention, the cathode lead frame and the anode lead frame are stacked with each other so as to make currents flowing through them in opposite directions. This structure cancels out the electromagnetic effects of the currents flowing through these lead frames, thereby greatly reducing the ESL. This chip solid electrolytic capacitor is particularly useful to applications where high frequency response is required.
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|Clasificación de EE.UU.||361/540, 361/528, 361/538|
|Clasificación internacional||H01G4/228, H01G9/10, H01G9/00|
|Clasificación cooperativa||H01G9/012, H01G9/14, H01G9/042, H01G9/08|
|Clasificación europea||H01G9/08, H01G9/14, H01G9/042, H01G9/012|
|4 Oct 2005||AS||Assignment|
Owner name: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FUJII, TATSUO;KURITA, JUNICHI;MIDOU, YUJI;AND OTHERS;REEL/FRAME:016618/0272;SIGNING DATES FROM 20050818 TO 20050822
|11 Ene 2010||REMI||Maintenance fee reminder mailed|
|6 Jun 2010||LAPS||Lapse for failure to pay maintenance fees|
|27 Jul 2010||FP||Expired due to failure to pay maintenance fee|
Effective date: 20100606