|Número de publicación||US7084027 B2|
|Tipo de publicación||Concesión|
|Número de solicitud||US 10/399,985|
|Número de PCT||PCT/EP2001/010783|
|Fecha de publicación||1 Ago 2006|
|Fecha de presentación||18 Sep 2001|
|Fecha de prioridad||8 Nov 2000|
|También publicado como||DE10055290C1, US20040014310, WO2002039488A2, WO2002039488A3|
|Número de publicación||10399985, 399985, PCT/2001/10783, PCT/EP/1/010783, PCT/EP/1/10783, PCT/EP/2001/010783, PCT/EP/2001/10783, PCT/EP1/010783, PCT/EP1/10783, PCT/EP1010783, PCT/EP110783, PCT/EP2001/010783, PCT/EP2001/10783, PCT/EP2001010783, PCT/EP200110783, US 7084027 B2, US 7084027B2, US-B2-7084027, US7084027 B2, US7084027B2|
|Inventores||Andreas Hilliger, Ralf Staub, Eike Lüken|
|Cesionario original||Infineon Technologies Ag|
|Exportar cita||BiBTeX, EndNote, RefMan|
|Citas de patentes (15), Otras citas (4), Citada por (1), Clasificaciones (19), Eventos legales (6)|
|Enlaces externos: USPTO, Cesión de USPTO, Espacenet|
The present invention relates to a method for fabricating an integrated circuit.
U.S. Pat. No. 5,864,156 discloses lining the upper region of the sidewalls of contact holes with a spacer material.
U.S. Pat. No. 5,792,687 discloses a method for forming contact holes, spacers being formed on the sidewalls of contact holes on an interlevel dielectric.
IBM Technical Disclosure Bulletin, Vol. 34, No. 4B, Sep. 1, 1991, pages 277 to 279, discloses the fabrication of contact plugs which are placed beside one another with the interposition of a spacer.
Although applicable to arbitrary integrated circuits, in principle, the present invention and the problem area on which it is based are explained with regard to integrated DRAM circuits using silicon technology.
The general problem area on which the present invention is based is that, during the fabrication of a common self-aligned bit line contact of a DRAM memory cell pair, the widening of the contact hole or its lateral offset leads to a risk of short circuits with respect to adjacent bit lines, which risk grows as design rules become smaller. What is increasingly problematic is the rising aspect ratio of the bit line contact owing to the decreasing horizontal and increasing vertical dimensions, i.e. the height of the gate stack.
An insulation layer IS, for example made of BPSG or SiO2, is situated above the circuit region SS and the isolation trenches STI. A contact hole KL is introduced into the insulation layer IS, said contact hole containing a contact which has a polysilicon contact plug PP in the lower region and a bit line BL2 in the upper region. Situated adjacent to the bit line BL2 are further bit lines BL1 and BL3 in corresponding bit line trenches BG1 and BG3, respectively.
What is problematic in the case of this arrangement is the fact that the contact hole KL may have a certain offset with respect to the circuit region SS and with respect to the adjacent bit lines, a displacement toward the left-hand side of
In this case, the bit line contact hole plane, which is relatively non critical lithographically in terms of the design, is fabricated with minimal contact hole dimensions in order to alleviate the problem of short-circuiting with respect to the adjacent bit line fabricated in a separate lithography. The overlay requirements are very high in this case. This complicates the lithography and the contact hole etching and makes them more expensive without fundamentally solving the problem. Moreover, there is an increase in the risk of inadequately opened bit line contacts at the contact base. The requirements made of the alignment of the bit line contact with respect to the active region or circuit region SS are increased. This results in a general contradiction which becomes more and more problematic with further shrinks.
Therefore, it is an object of the present invention to provide a method for fabricating an integrated circuit of this type, the risk of line short circuits of adjacent lines being reduced.
According to the invention, this object is achieved by means of the fabrication method specified in claim 1.
The idea on which the present invention is based consists in applying an insulating suitable layer to the sidewalls in the upper region of the contact hole, which layer prevents short circuits with respect to adjacent bit lines.
The fabrication method according to the invention has the advantage, inter alia, over the known solution approach, through the addition of a few technologically noncritical processes, the actual contact-connection of the silicon is decoupled from the contact-connection of the passing bit line. Thus, it is then possible to relax the fabrication of the contact hole mask with regard to dimension and overlay, to separately optimize the contact hole etching and nevertheless to avoid short circuits between the bit lines.
Advantageous developments and improvements of the fabrication method specified in claim 1 are found in the subclaims.
In accordance with one preferred development, a contact plug made of a conductive material is provided in the lower region of the contact hole.
In accordance with a further preferred development, the spacer region is fabricated by the deposition and anisotropic etching-back of an insulating spacer layer, as a result of which the spacer layer is left only on the sidewalls of the contact hole.
In accordance with a further preferred development, after the provision of the spacer region, an antireflection coating is deposited on the entire structure, which essentially fills the contact hole.
In accordance with a further preferred development, a mask for the line trenches is applied on the antireflection coating; the first and third line trenches are etched into the insulation layer after the removal of the overlying antireflection coating using the mask; and the second line trench is formed using the mask and after the removal of the antireflection coating from the upper region of the contact hole.
In accordance with a further preferred development, an insulating spacer layer is deposited above the structure and a mask for the line trenches is applied on the insulating spacer layer; the first, second and third line trenches are etched into the insulation layer after the removal of the overlying insulation spacer layer using the mask, at the same time the insulating spacer layer being removed at least partly from the contact hole during the formation of the second line trench.
In accordance with a further preferred development, the line trenches have a distance and a width corresponding to the minimum structure width.
In accordance with a further preferred development, the circuit region is surrounded by STI trenches.
In accordance with a further preferred development, the line material is tungsten.
In accordance with a further preferred development, the upper region of the spacer region is removed during the chemical mechanical polishing.
In accordance with a further preferred development, the spacer regions are fabricated from CVD silicon dioxide.
In accordance with a further preferred development, the lines are bit lines of an integrated memory circuit.
Exemplary embodiments of the invention are illustrated in the drawings and explained in more detail in the description below.
In the figures:
In the figures, identical reference symbols designate identical or functionally identical component parts.
In accordance with
The polysilicon contact plug PP is then provided by polysilicon being deposited over the whole area and subsequently being etched back to a predetermined depth.
In a subsequent process step, a CVD-SiO2 layer having a thickness of approximately 20 nm to 70 nm is deposited, which layer is designated by 10 in
In a subsequent process step, the SiO2 is etched anisotropically by means of a separate etching process in order to form from the spacer layer 10 spacer regions 10′ on the sidewalls of the upper region of the contact hole KL on the polysilicon contact plug PP, as illustrated in
In a subsequent process step, an antireflection coating 20 is applied over the entire structure, which essentially fills the contact hole KL, as illustrated in
As illustrated in
In a subsequent process step, tungsten is deposited over the whole area of the resulting structure and then removed by a chemical mechanical polishing step in such a way that separate bit lines BL1, BL2, BL3 are formed.
The second embodiment, described with reference to
The starting point of the second embodiment corresponds to the state illustrated in
In a subsequent etching step, by means of the mask 110, firstly the spacer layer 10 and then the underlying insulation layer IS are etched in a corresponding anisotropic etching process, the polysilicon contact plug PP acting as an etching stop within the contact hole KL. This leads to the process stage shown in
Removal of the mask 110 yields a structure in accordance with
In this case, too, the region designated by BBI is noncritical because the bit line BL2 is isolated from the bit line BL1 by a wide spacer region BBI and the short-circuit risk is thus minimized.
Although the present invention has been described above using preferred exemplary embodiments, it is not restricted thereto, but rather can be modified in diverse ways.
In particular, the selection of the layer materials and the concrete circuit are only by way of example and can be varied in many different ways.
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|US20030127677 *||21 Ene 2003||10 Jul 2003||Samsung Electronics Co., Ltd.||Semiconductor device having a self-aligned contact structure and methods of forming the same|
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|KR20000065823A||Título no disponible|
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|1||"Fabricating One Semiconductor Contact Stud Borderless to Another," IBM Technical Disclosure Bulletin, vol. 34, No. 4B, Sep. 1991, pp. 277-279.|
|2||German Office Action dated Jun. 8, 2001.|
|3||International Search Report dated May 2, 2002.|
|4||Korean Office Action dated Mar. 14, 2005.|
|Patente citante||Fecha de presentación||Fecha de publicación||Solicitante||Título|
|US8492269||16 Sep 2011||23 Jul 2013||Globalfoundries Inc.||Hybrid contact structure with low aspect ratio contacts in a semiconductor device|
|Clasificación de EE.UU.||438/239, 438/386, 438/256, 438/243, 438/399, 438/387, 438/244, 257/E21.657, 438/396, 438/250, 257/E21.507|
|Clasificación internacional||H01L21/768, H01L27/108, H01L21/8242, H01L21/60|
|Clasificación cooperativa||H01L27/10885, H01L21/76897|
|Clasificación europea||H01L27/108M4D2, H01L21/768S|
|18 Feb 2004||AS||Assignment|
Owner name: INFINEON TECHNOLOGIES, AG, GERMANY
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