US7107383B1 - Method and system for multi-channel transfer of data and control information - Google Patents
Method and system for multi-channel transfer of data and control information Download PDFInfo
- Publication number
- US7107383B1 US7107383B1 US09/564,592 US56459200A US7107383B1 US 7107383 B1 US7107383 B1 US 7107383B1 US 56459200 A US56459200 A US 56459200A US 7107383 B1 US7107383 B1 US 7107383B1
- Authority
- US
- United States
- Prior art keywords
- cell
- bridge
- bus
- memory
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
- G06F13/128—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine for dedicated transfers to a network
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/40—Network security protocols
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/14—Multichannel or multilink protocols
Abstract
Description
Number of Clocks Per Slot*Number of Slots*Number of Data Channels Per Slot
Number of Clocks Per Slot*Number of Slots*Number of GCN Channels Per Slot
Number of Clocks Per Slot*Number of Slots*Number of Data Channels Per Slot
Number of Clocks Per Slot*Number of Slots*Number of GCN Channels Per Slot
Claims (31)
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/564,592 US7107383B1 (en) | 2000-05-03 | 2000-05-03 | Method and system for multi-channel transfer of data and control information |
DE60115010T DE60115010T2 (en) | 2000-05-03 | 2001-05-03 | BUS BRIDGE AND SYSTEM FOR MULTI-CHANNEL TRANSMISSION OF DATA AND CONTROL INFORMATION |
EP01932961A EP1279103B1 (en) | 2000-05-03 | 2001-05-03 | Bridge and system for multi-channel transfer of data and control information |
AU2001259440A AU2001259440A1 (en) | 2000-05-03 | 2001-05-03 | A method and system for multi-channel transfer of data and control information |
PCT/US2001/014336 WO2001084330A2 (en) | 2000-05-03 | 2001-05-03 | A method and system for multi-channel transfer of data and control information |
AT01932961T ATE310276T1 (en) | 2000-05-03 | 2001-05-03 | BUS BRIDGE AND SYSTEM FOR MULTI-CHANNEL TRANSMISSION OF DATA AND CONTROL INFORMATION |
US11/518,122 US7334074B2 (en) | 2000-05-03 | 2006-09-08 | Method and system for multi-channel transfer of data and control |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/564,592 US7107383B1 (en) | 2000-05-03 | 2000-05-03 | Method and system for multi-channel transfer of data and control information |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/518,122 Continuation US7334074B2 (en) | 2000-05-03 | 2006-09-08 | Method and system for multi-channel transfer of data and control |
Publications (1)
Publication Number | Publication Date |
---|---|
US7107383B1 true US7107383B1 (en) | 2006-09-12 |
Family
ID=24255107
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/564,592 Expired - Fee Related US7107383B1 (en) | 2000-05-03 | 2000-05-03 | Method and system for multi-channel transfer of data and control information |
US11/518,122 Expired - Fee Related US7334074B2 (en) | 2000-05-03 | 2006-09-08 | Method and system for multi-channel transfer of data and control |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/518,122 Expired - Fee Related US7334074B2 (en) | 2000-05-03 | 2006-09-08 | Method and system for multi-channel transfer of data and control |
Country Status (6)
Country | Link |
---|---|
US (2) | US7107383B1 (en) |
EP (1) | EP1279103B1 (en) |
AT (1) | ATE310276T1 (en) |
AU (1) | AU2001259440A1 (en) |
DE (1) | DE60115010T2 (en) |
WO (1) | WO2001084330A2 (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060262630A1 (en) * | 2003-12-31 | 2006-11-23 | Ho Duc V | Apparatus and method for managing voltage buses |
US20060265533A1 (en) * | 2002-02-19 | 2006-11-23 | Schism Electronics, L.L.C. | Hierarchical bus structure and memory access protocol for multiprocessor systems |
US20070016713A1 (en) * | 2000-05-03 | 2007-01-18 | Sundar Rajan | Method and system for multi-channel transfer of data and control |
US20070113038A1 (en) * | 2002-02-19 | 2007-05-17 | Hobson Richard F | Processor cluster architecture and associated parallel processing methods |
US20100165692A1 (en) * | 2008-12-30 | 2010-07-01 | Micron Technology, Inc. | Variable memory refresh devices and methods |
US20110161543A1 (en) * | 2009-12-24 | 2011-06-30 | St-Ericsson Sa | Memory Management |
US9838500B1 (en) * | 2014-03-11 | 2017-12-05 | Marvell Israel (M.I.S.L) Ltd. | Network device and method for packet processing |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201308200A (en) * | 2011-08-12 | 2013-02-16 | Ite Tech Inc | Bridge, system and the method for prefetching and discarding data thereof |
Citations (40)
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EP0654743A1 (en) | 1993-11-19 | 1995-05-24 | International Business Machines Corporation | Computer system having a DSP local bus |
WO1996022571A1 (en) | 1995-01-20 | 1996-07-25 | Intel Corporation | Bus bridge circuit and method using snoop ahead operations |
US5588125A (en) * | 1993-10-20 | 1996-12-24 | Ast Research, Inc. | Method and apparatus for increasing bus bandwidth on a system bus by inhibiting interrupts while posted I/O write operations are pending |
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US5826048A (en) * | 1997-01-31 | 1998-10-20 | Vlsi Technology, Inc. | PCI bus with reduced number of signals |
US5832245A (en) * | 1996-10-21 | 1998-11-03 | Advanced Micro Devices, Inc. | Method for isochronous flow control across an inter-chip bus |
US5911055A (en) * | 1996-06-05 | 1999-06-08 | Compaq Computer Corporation | Using subordinate bus devices that are connected to a common bus |
US5964859A (en) * | 1997-10-30 | 1999-10-12 | Advanced Micro Devices, Inc. | Allocatable post and prefetch buffers for bus bridges |
US5983291A (en) * | 1996-09-24 | 1999-11-09 | Cirrus Logic, Inc. | System for storing each of streams of data bits corresponding from a separator thereby allowing an input port accommodating plurality of data frame sub-functions concurrently |
GB2337403A (en) | 1998-05-11 | 1999-11-17 | Gen Datacomm Adv Res | Data communication |
US5996034A (en) * | 1997-10-14 | 1999-11-30 | Advanced Micro Devices, Inc. | Bus bridge verification system including device independent bus monitors |
US6044225A (en) | 1996-03-13 | 2000-03-28 | Diamond Multimedia Systems, Inc. | Multiple parallel digital data stream channel controller |
US6078980A (en) * | 1998-12-29 | 2000-06-20 | Intel Corporation | Regulating a data transfer time |
US6078976A (en) * | 1997-06-24 | 2000-06-20 | Matsushita Electric Industrial Co., Ltd. | Bridge device that prevents decrease in the data transfer efficiency of buses |
US6081863A (en) * | 1998-03-13 | 2000-06-27 | International Business Machines Corporation | Method and system for supporting multiple peripheral component interconnect PCI buses by a single PCI host bridge within a computer system |
US6085269A (en) * | 1996-10-31 | 2000-07-04 | Texas Instruments Incorporated | Configurable expansion bus controller in a microprocessor-based system |
US6108736A (en) * | 1997-09-22 | 2000-08-22 | Intel Corporation | System and method of flow control for a high speed bus |
US6112311A (en) * | 1998-02-20 | 2000-08-29 | International Business Machines Corporation | Bridge failover system |
US6189063B1 (en) * | 1997-09-30 | 2001-02-13 | Texas Instruments Incorporated | Method and apparatus for intelligent configuration register access on a PCI to PCI bridge |
US6247086B1 (en) * | 1998-11-12 | 2001-06-12 | Adaptec, Inc. | PCI bridge for optimized command delivery |
US6272582B1 (en) * | 1998-02-20 | 2001-08-07 | Mitsubishi Denki Kabushiki Kaisha | PCI-PCI bridge allowing controlling of a plurality of PCI agents including a VGA device |
US6286074B1 (en) * | 1999-03-24 | 2001-09-04 | International Business Machines Corporation | Method and system for reading prefetched data across a bridge system |
US6295568B1 (en) * | 1998-04-06 | 2001-09-25 | International Business Machines Corporation | Method and system for supporting multiple local buses operating at different frequencies |
US6311247B1 (en) * | 1999-01-15 | 2001-10-30 | Hewlett Packard Company | System for bridging a system bus with multiple PCI buses |
US6330241B1 (en) * | 1995-02-06 | 2001-12-11 | Adc Telecommunications, Inc. | Multi-point to point communication system with remote unit burst identification |
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US6404928B1 (en) * | 1991-04-17 | 2002-06-11 | Venson M. Shaw | System for producing a quantized signal |
US6425033B1 (en) * | 1997-06-20 | 2002-07-23 | National Instruments Corporation | System and method for connecting peripheral buses through a serial bus |
US6457091B1 (en) * | 1999-05-14 | 2002-09-24 | Koninklijke Philips Electronics N.V. | PCI bridge configuration having physically separate parts |
US6466541B1 (en) * | 2000-05-31 | 2002-10-15 | Fujitsu Network Communications, Inc. | Cell pacing on a network link employing a rate-based flow control protocol with underlying credit-based flow control mechanisms |
US6477646B1 (en) * | 1999-07-08 | 2002-11-05 | Broadcom Corporation | Security chip architecture and implementations for cryptography acceleration |
US6484222B1 (en) * | 1999-12-06 | 2002-11-19 | Compaq Information Technologies Group, L.P. | System for incorporating multiple expansion slots in a variable speed peripheral bus |
US20030070018A1 (en) * | 1999-04-23 | 2003-04-10 | Jiin Lai | Delayed transaction method and device used in a PCI system |
US6567882B1 (en) * | 1998-11-12 | 2003-05-20 | Nec Corporation | PCI function extension control device and method of PCI function extension control |
US6636929B1 (en) * | 2000-04-06 | 2003-10-21 | Hewlett-Packard Development Company, L.P. | USB virtual devices |
US6668299B1 (en) * | 1999-09-08 | 2003-12-23 | Mellanox Technologies Ltd. | Software interface between a parallel bus and a packet network |
Family Cites Families (3)
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---|---|---|---|---|
US5696910A (en) * | 1995-09-26 | 1997-12-09 | Intel Corporation | Method and apparatus for tracking transactions in a pipelined bus |
US5761462A (en) * | 1996-12-13 | 1998-06-02 | International Business Machines Corporation | Method and system for supporting peripheral component interconnect (PCI) peer-to-peer access across multiple PCI host bridges within a data-processing system |
US7107383B1 (en) | 2000-05-03 | 2006-09-12 | Broadcom Corporation | Method and system for multi-channel transfer of data and control information |
-
2000
- 2000-05-03 US US09/564,592 patent/US7107383B1/en not_active Expired - Fee Related
-
2001
- 2001-05-03 AU AU2001259440A patent/AU2001259440A1/en not_active Abandoned
- 2001-05-03 AT AT01932961T patent/ATE310276T1/en not_active IP Right Cessation
- 2001-05-03 WO PCT/US2001/014336 patent/WO2001084330A2/en active IP Right Grant
- 2001-05-03 EP EP01932961A patent/EP1279103B1/en not_active Expired - Lifetime
- 2001-05-03 DE DE60115010T patent/DE60115010T2/en not_active Expired - Lifetime
-
2006
- 2006-09-08 US US11/518,122 patent/US7334074B2/en not_active Expired - Fee Related
Patent Citations (42)
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US6404928B1 (en) * | 1991-04-17 | 2002-06-11 | Venson M. Shaw | System for producing a quantized signal |
US5588125A (en) * | 1993-10-20 | 1996-12-24 | Ast Research, Inc. | Method and apparatus for increasing bus bandwidth on a system bus by inhibiting interrupts while posted I/O write operations are pending |
EP0654743A1 (en) | 1993-11-19 | 1995-05-24 | International Business Machines Corporation | Computer system having a DSP local bus |
WO1996022571A1 (en) | 1995-01-20 | 1996-07-25 | Intel Corporation | Bus bridge circuit and method using snoop ahead operations |
US5600646A (en) * | 1995-01-27 | 1997-02-04 | Videoserver, Inc. | Video teleconferencing system with digital transcoding |
US6330241B1 (en) * | 1995-02-06 | 2001-12-11 | Adc Telecommunications, Inc. | Multi-point to point communication system with remote unit burst identification |
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Cited By (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070016713A1 (en) * | 2000-05-03 | 2007-01-18 | Sundar Rajan | Method and system for multi-channel transfer of data and control |
US7334074B2 (en) * | 2000-05-03 | 2008-02-19 | Broadcom Corporation | Method and system for multi-channel transfer of data and control |
US20110047354A1 (en) * | 2002-02-19 | 2011-02-24 | Schism Electronics, L.L.C. | Processor Cluster Architecture and Associated Parallel Processing Methods |
US20060265533A1 (en) * | 2002-02-19 | 2006-11-23 | Schism Electronics, L.L.C. | Hierarchical bus structure and memory access protocol for multiprocessor systems |
US20070113038A1 (en) * | 2002-02-19 | 2007-05-17 | Hobson Richard F | Processor cluster architecture and associated parallel processing methods |
US8489857B2 (en) | 2002-02-19 | 2013-07-16 | Schism Electronics, L.L.C. | Processor cluster architecture and associated parallel processing methods |
US7469308B2 (en) * | 2002-02-19 | 2008-12-23 | Schism Electronics, Llc | Hierarchical bus structure and memory access protocol for multiprocessor systems |
US20090106468A1 (en) * | 2002-02-19 | 2009-04-23 | Schism Electronics, L.L.C. | Hierarchical Bus Structure and Memory Access Protocol for Multiprocessor Systems |
US8190803B2 (en) | 2002-02-19 | 2012-05-29 | Schism Electronics, L.L.C. | Hierarchical bus structure and memory access protocol for multiprocessor systems |
US7840778B2 (en) | 2002-02-19 | 2010-11-23 | Hobson Richard F | Processor cluster architecture and associated parallel processing methods |
US7360006B2 (en) * | 2003-12-31 | 2008-04-15 | Micron Technology, Inc. | Apparatus and method for managing voltage buses |
US20060262630A1 (en) * | 2003-12-31 | 2006-11-23 | Ho Duc V | Apparatus and method for managing voltage buses |
US7929368B2 (en) * | 2008-12-30 | 2011-04-19 | Micron Technology, Inc. | Variable memory refresh devices and methods |
US20110194369A1 (en) * | 2008-12-30 | 2011-08-11 | Jeddeloh Joe M | Variable memory refresh devices and methods |
US20100165692A1 (en) * | 2008-12-30 | 2010-07-01 | Micron Technology, Inc. | Variable memory refresh devices and methods |
US8199599B2 (en) | 2008-12-30 | 2012-06-12 | Micron Technology, Inc. | Variable memory refresh devices and methods |
US8797818B2 (en) | 2008-12-30 | 2014-08-05 | Micron Technology, Inc. | Variable memory refresh devices and methods |
US20110161543A1 (en) * | 2009-12-24 | 2011-06-30 | St-Ericsson Sa | Memory Management |
US8615621B2 (en) * | 2009-12-24 | 2013-12-24 | St-Ericsson Sa | Memory management |
US9838500B1 (en) * | 2014-03-11 | 2017-12-05 | Marvell Israel (M.I.S.L) Ltd. | Network device and method for packet processing |
Also Published As
Publication number | Publication date |
---|---|
DE60115010T2 (en) | 2006-08-03 |
AU2001259440A1 (en) | 2001-11-12 |
DE60115010D1 (en) | 2005-12-22 |
US7334074B2 (en) | 2008-02-19 |
ATE310276T1 (en) | 2005-12-15 |
EP1279103B1 (en) | 2005-11-16 |
WO2001084330A3 (en) | 2002-06-13 |
EP1279103A2 (en) | 2003-01-29 |
WO2001084330A2 (en) | 2001-11-08 |
US20070016713A1 (en) | 2007-01-18 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SILICON SPICE, A CALIFORNIA CORPORATION, CALIFORNI Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:RAJAN, SUNDAR;REEL/FRAME:010771/0196 Effective date: 20000502 |
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